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IP-First, LLC Patents
Assignee:
IP-First, LLC
Address:
Fremont, CA
No. of patents:
159
Patents:


1 2 3 4










Patent Number Title Of Patent Date Issued
8296345 Microprocessor with selectively available random number generator based on self-test result October 23, 2012
A microprocessor including a random number generator within its instruction set architecture and made selectively available to program instructions of the instruction set architecture depending upon results of a self-test of the random number generator performed is disclosed. The mic
7849120 Microprocessor with random number generator and instruction for storing random data December 7, 2010
A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. An instruction transla
7844053 Microprocessor apparatus and method for performing block cipher cryptographic functions November 30, 2010
A microprocessor apparatus is provided, for performing a cryptographic operation. The microprocessor apparatus includes an x86-compatible microprocessor that has fetch logic, a cryptography unit, and an integer unit. The fetch logic is configured to fetch an application program from
7818358 Microprocessor with random number generator and instruction for storing random data October 19, 2010
A microprocessor includes a storage element that accumulates a variable number of bytes of random data. The microprocessor also includes a counter that maintains a count of the variable number of bytes accumulated in the storage element. The microprocessor also includes an instructio
7712105 Microprocessor including random number generator supporting operating system-independent multita May 4, 2010
A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The C
7647479 Non-temporal memory reference control mechanism January 12, 2010
An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into
7647478 Suppression of store checking January 12, 2010
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended
7631172 Apparatus and method for selectively overriding return stack prediction in response to detection December 8, 2009
A microprocessor for predicting return instruction target addresses is disclosed. A branch target address cache stores a plurality of target address predictions and a corresponding plurality of override indicators for a corresponding plurality of return instructions, and provides a p
7546446 Selective interrupt suppression June 9, 2009
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction
7543134 Apparatus and method for extending a microprocessor instruction set June 2, 2009
An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an e
7542566 Apparatus and method for performing transparent cipher block chaining mode cryptographic functio June 2, 2009
An apparatus and method for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, CBC block pointer logic, and execution logic. The cryptographic instruction is received by a pipeline microprocessor as part of an application program exec
7532722 Apparatus and method for performing transparent block cipher cryptographic functions May 12, 2009
The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instructi
7398377 Apparatus and method for target address replacement in speculative branch target address cache July 8, 2008
An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used entry is replaced. If
7395412 Apparatus and method for extending data modes in a microprocessor July 1, 2008
An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in the microprocessor instruction set. The apparatus includes translation logic and extende
7383394 Microprocessor, apparatus and method for selective prefetch retire June 3, 2008
An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor includes a cache memory, comprising an
7380109 Apparatus and method for providing extended address modes in an existing instruction set for a m May 27, 2008
An apparatus and method are provided for extending a microprocessor instruction set to allow for extended size addresses. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into an associated micro instructi
7380103 Apparatus and method for selective control of results write back May 27, 2008
A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended
7373483 Mechanism for extending the number of registers in a microprocessor May 13, 2008
An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the mi
7334009 Microprocessor with random number generator and instruction for storing random data February 19, 2008
A microprocessor that includes a random number generator (RNG) and an instruction for storing random data bytes generated by the generator. The RNG includes multiple buffers for buffering the random bytes and counters associated with each buffer for keeping a count of the number of bytes
7328328 Non-temporal memory reference control mechanism February 5, 2008
An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into
7321910 Microprocessor apparatus and method for performing block cipher cryptographic functions January 22, 2008
The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instructi
7315921 Apparatus and method for selective memory attribute control January 1, 2008
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective override of memory traits at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction
7302551 Suppression of store checking November 27, 2007
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended
7288980 Multiple mode clock receiver October 30, 2007
A multiple mode clock receiver including first and second input AC-coupled capacitors, first and second voltage dividers and a differential amplifier. The voltage dividers each include first and second junctions, respectively, coupled to the first and second AC-coupled capacitors, re
7263585 Store-induced instruction coherency mechanism August 28, 2007
An apparatus and method for ensuring coherency of instructions within stages of the pipeline microprocessor. The apparatus includes instruction cache management logic and synchronization logic. The instruction cache management logic receives an address corresponding to a next instruction
7240163 Microprocessor, apparatus and method for selective prefetch retire July 3, 2007
An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the c
7237098 Apparatus and method for selectively overriding return stack prediction in response to detection June 26, 2007
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address. Typically the return stack is more accurate. However, if the return stack mispredicts, update l
7234045 Apparatus and method for handling BTAC branches that wrap across instruction cache lines June 19, 2007
A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of
7234025 Microprocessor with repeat prefetch instruction June 19, 2007
A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP stri
7219112 Microprocessor with instruction translator for translating an instruction for storing random dat May 15, 2007
A microprocessor that includes a random number generator (RNG) and an instruction for storing random data bytes generated by the generator. The RNG includes multiple buffers for buffering the random bytes and counters associated with each buffer for keeping a count of the number of bytes
7203824 Apparatus and method for handling BTAC branches that wrap across instruction cache lines April 10, 2007
A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of
7200740 Apparatus and method for speculatively performing a return instruction in a microprocessor April 3, 2007
A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branch target address c
7193445 Non-inverting domino register March 20, 2007
A non-inverting domino register including a domino stage, a storage stage, a keeper circuit and an output stage. The domino stage includes evaluation logic, coupled between evaluation devices at a pre-charged node, which evaluates a logic function. The storage stage drives a first pr
7191291 Microprocessor with variable latency stack cache March 13, 2007
A variable latency cache memory is disclosed. The cache memory includes a plurality of storage elements for storing stack memory data in a first-in-first-out manner. The cache memory distinguishes between pop and load instruction requests and provides pop data faster than load data by
7188215 Apparatus and method for renaming a cache line March 6, 2007
A microprocessor apparatus is provided that enables exclusive allocation and renaming a cache line. The apparatus includes translation logic and execution logic. The translation logic translates an allocate and rename instruction into a micro instruction sequence that directs a micro
7185186 Apparatus and method for resolving deadlock fetch conditions involving branch target address cac February 27, 2007
An apparatus for avoiding a deadlock condition in a microprocessor with a speculative branch target address cache (BTAC) that predicts a target address of a branch instruction contained in a cache line output by an instruction cache in response to a fetch address is disclosed. The BTAC
7185180 Apparatus and method for selective control of condition code write back February 27, 2007
A microprocessor apparatus and method are provided, for selectively controlling write back of condition codes. The microprocessor apparatus has translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions.
7181596 Apparatus and method for extending a microprocessor instruction set February 20, 2007
An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an e
7178010 Method and apparatus for correcting an internal call/return stack in a microprocessor that detec February 13, 2007
An internal call/return stack (CRS) correction apparatus in a pipelined microprocessor is disclosed. Each time the microprocessor updates the CRS in response to a call or return instruction (call/ret), the microprocessor also stores correction information into a first correction stac
7174355 Random number generator with selectable dual random bit string engines February 6, 2007
A microprocessor with multiple random bit generators is disclosed. The multiple random bit generators each generate a stream of random bits. One of the streams of random bits is selected to be used to accumulate into random bytes for provision to application programs. Which of the multip
7173456 Dynamic logic return-to-zero latching mechanism February 6, 2007
A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation d
7165169 Speculative branch target address cache with selective override by secondary predictor based on January 16, 2007
A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target address cache in the primary branch predictor speculatively predicts a branch target addres
7165168 Microprocessor with branch target address cache update queue January 16, 2007
A microprocessor with a write queue for a branch target address cache (BTAC) is disclosed. The BTAC is read in parallel with an instruction cache in order to predict a target address of a branch instruction in the accessed cache line. In one embodiment, the BTAC is single-ported; hence,
7165084 Microprocessor with selectivity available random number generator based on self-test result January 16, 2007
A microprocessor including a random number generator (RNG) that performs a self-test on reset and selectively enables/disables itself based on the self-test results is disclosed. The RNG includes a self-test unit that performs the self-test to determine whether the RNG is functioning
7162619 Apparatus and method for densely packing a branch instruction predicted by a branch target addre January 9, 2007
A branch control apparatus in a microprocessor. A register receives a first cache line containing a branch instruction from an instruction cache in response to a fetch address. The fetch address hits in a BTAC that provides a target address of the branch instruction. The BTAC also pr
7162612 Mechanism in a microprocessor for executing native instructions directly from memory January 9, 2007
An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus,
7159098 Selecting next instruction line buffer stage based on current instruction line boundary wraparou January 2, 2007
A branch control apparatus in a microprocessor. The branch control apparatus includes an instruction buffer having a plurality of stages that buffer cache lines of instruction bytes received from an instruction cache. A multiplexer selects one of the bottom three stages in the instru
7159097 Apparatus and method for buffering instructions and late-generated related information using his January 2, 2007
An instruction buffering apparatus is disclosed. The apparatus includes an early queue and a late queue. The early queue receives an instruction generated during a first clock cycle. The late queue receives information related to the instruction during a second clock cycle subsequent to
7155598 Apparatus and method for conditional instruction execution December 26, 2006
A conditional execution apparatus in a microprocessor is provided. The conditional execution apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and
7152154 Apparatus and method for invalidation of redundant branch target address cache entries December 19, 2006
An apparatus for invalidating redundant entries in an N-way set associative branch target address cache (BTAC) for the same branch instruction is disclosed. An index portion of an instruction cache fetch address is applied to the BTAC to select a set of N ways therein. Control logic
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