US Patent 6253312: Method and apparatus for double operand load

An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.