United States Patent
US Patent 4035601: Electrical circuit arrangements responsive to…
US 4035601 · granted 1977-07-12
Abstract
Envisages the use of a format of serial digital signalling in which each data word comprises a predetermined number of bytes formed by bits of substantially uniform duration and in which each byte comprises a "start" bit of a first binary significance (e.g. 0) a "stop" bit having a second binary significance (e.g. 1) and an identical plurality of "data" bits immediately succeeding said "start" bit and in which the final byte of the data-word is characterized in that it has an additional bit having said first binary significance 0 interposed between last "data" bit and the "stop" bit thereof. The reading of that bit immediately succeeding the last "data" bit of each byte of each data-word of a transmission produce a so-called synchronizing pulse-sequence comprising bits of said second significance for all bytes except that last and a bit of said first significance for the last byte.A response circuit is provided normally to maintain byte-to-byte synchronization. If de-synchronization is detected the data-word involved is completely cancelled and the circuit is set for re-synchronization preparatory to commencement of next data-word.
| Patent Number | 4035601 |
|---|---|
| Title | Electrical circuit arrangements responsive to serial digital signals forming multi-byte data-words |
| Filed | 1975-06-17 |
| Granted | 1977-07-12 |
| Inventor(s) | Isaacs; Charles Allan |
| Assignee | Plessey Handel und Investments A.G. |
| Number of Claims | 11 |
Abstract
Envisages the use of a format of serial digital signalling in which each data word comprises a predetermined number of bytes formed by bits of substantially uniform duration and in which each byte comprises a "start" bit of a first binary significance (e.g. 0) a "stop" bit having a second binary significance (e.g. 1) and an identical plurality of "data" bits immediately succeeding said "start" bit and in which the final byte of the data-word is characterized in that it has an additional bit having said first binary significance 0 interposed between last "data" bit and the "stop" bit thereof. The reading of that bit immediately succeeding the last "data" bit of each byte of each data-word of a transmission produce a so-called synchronizing pulse-sequence comprising bits of said second significance for all bytes except that last and a bit of said first significance for the last byte.A response circuit is provided normally to maintain byte-to-byte synchronization. If de-synchronization is detected the data-word involved is completely cancelled and the circuit is set for re-synchronization preparatory to commencement of next data-word.
Claim 1
In or for use in a digital-data transmission system, a signalling response circuit for incoming signals having a signalling format of the kind referred to and characterisedin that it includes (i) register means for the storing of the data content of each byte of a received data-word, (ii) control logic means for producing, preparatory to reception of each byte of the data-word, either a first condition indicating that thebyte currently expected is other than the last byte of a data-word or a second condition indicating that the byte expected is the last byte of a data-word and producing control signals connected to said register means, (iii) detector means for extractingfrom said incoming signals, pulses having time appearances appropriate to a synchronising-pulse sequence, (iv) a comparison device operative under control of each aforesaid extracted pulse and the prevailing said first or second condition to assess thepresence or absence of a synchronisation error in relation to any currently received byte of a data-word and to produce a first or second output signal appropriate to said presence and absence respectively, said output signal being applied to saidcontrol logic means to
Claims
11 totalIn or for use in a digital-data transmission system, a signalling response circuit for incoming signals having a signalling format of the kind referred to and characterisedin that it includes (i) register means for the storing of the data content of each byte of a received data-word, (ii) control logic means for producing, preparatory to reception of each byte of the data-word, either a first condition indicating that thebyte currently expected is other than the last byte of a data-word or a second condition indicating that the byte expected is the last byte of a data-word and producing control signals connected to said register means, (iii) detector means for extractingfrom said incoming signals, pulses having time appearances appropriate to a synchronising-pulse sequence, (iv) a comparison device operative under control of each aforesaid extracted pulse and the prevailing said first or second condition to assess thepresence or absence of a synchronisation error in relation to any currently received byte of a data-word and to produce a first or second output signal appropriate to said presence and absence respectively, said output signal being applied to saidcontrol logic means to