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Delay circuits using negative resistance CMOS circuits
T955006 Delay circuits using negative resistance CMOS circuits

Patent Drawings:
Inventor: Cavaliere, et al.
Date Issued: February 1, 1977
Application: 05/695,716
Filed: June 14, 1976
Inventors: Cavaliere; Joseph Richard (Hopewell Junction, NY)
Eardley; David Barry (Stanfordville, NY)
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner:
Assistant Examiner:
Attorney Or Agent:
U.S. Class: 327/399; 327/437; 327/568
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U.S Patent Documents:
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Abstract: A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.
Claim:
Description:
 
 
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