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Master image chip organization technique or method |
| T106201 |
Master image chip organization technique or method
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| Inventor: |
Balyoz, et al. |
| Date Issued: |
March 4, 1986 |
| Application: |
06/457,786 |
| Filed: |
January 13, 1983 |
| Inventors: |
Balyoz; John (Hopewell Junction, NY)
Chang; Chi S. (Wappingers Falls, NY)
Fox; Barry C. (Poughkeepsie, NY)
Ghafghaichi; Majid (Poughkeepsie, NY)
Jen; Teh-Sen (Fishkill, NY)
Mooney; Donald B. (Poughkeepsie, NY)
Palmieri; John A. (Wappingers Falls, NY)
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| U.S. Class: |
257/E23.151; 257/E27.106; 438/384 |
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| Abstract: |
A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern of conductors, and each of said connections occurring exclusively at points in space corresponding to X-Y intersections of an X-Y coordinate system, where said X-Y coordinate system geometrically corresponds identically to said X-Y pattern of conductors. |
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