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Clock phase detecting circuit and clock regenerating circuit each arranged in receiving unit of multiplex radio equipment |
| RE40695 |
Clock phase detecting circuit and clock regenerating circuit each arranged in receiving unit of multiplex radio equipment
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| Patent Drawings: | |
| Inventor: |
Iwamatsu, et al. |
| Date Issued: |
April 7, 2009 |
| Application: |
09/771,229 |
| Filed: |
January 26, 2001 |
| Inventors: |
Iwamatsu; Takanori (Kawasaki, JP)
Kiyanagi; Hiroyuki (Sendai, JP)
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| Assignee: |
Fujitsu Limited (Kawasaki, JP) |
| Primary Examiner: |
Tse; Young T. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Katten Muchin Rosenman LLP |
| U.S. Class: |
375/354; 329/304; 375/326; 375/332; 375/344 |
| Field Of Search: |
375/279; 375/280; 375/281; 375/326; 375/327; 375/329; 375/332; 375/344; 375/354; 375/371; 375/373; 375/376; 329/304; 329/307; 329/308 |
| International Class: |
H04L 7/02; H04L 27/22 |
| U.S Patent Documents: |
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| Foreign Patent Documents: |
3124329; 0 173 298; 0 184 805; 0 249 931; 0 368 307; 63-215235; 2-84834; 6-311193; 9-98198 |
| Other References: |
Sailer, "Timing Recovery in Data Transmissions Systems Using Multilevel Partial Responese Signaling" International Conference onCommunications Conference Record ICC '92, Jun. 14-18, 1992: vol. 2, Jun. 1975, pp. 24-27, XP000579359. cited by other.
"Offset Binary Simplifies Timing Control In a Priv Communication Channel" IBM Technical Disclosure Bulleting, vol. 33, No. 12 May 1, 1991, pp. 5-8, XP000121439. cited by other. |
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| Abstract: |
The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit for identifying a signal obtained by demodulating a multilevel orthogonal modulation signal; a clock regenerating circuit for regenerating a signal identification clock for the identifying circuit to supply the clock to the identifying circuit; an equalizing circuit for subjecting the signal obtained by demodulating a multilevel orthogonal modulation signal to an equalizing process. A clock phase detecting unit detects the phase component of the signal identification clock based on signals input to or output from the equalizing circuit and then supplies the phase component to the clock regenerating circuit. The phase component of a signal identification clock can be certainly detected and accurately adjusted so that the signal identification clock can be regenerated with high accuracy. |
| Claim: |
What is claimed is:
.[.1. A clock phase detecting circuit arranged in a receiving unit of multiplex radio equipment, comprising: an identifying circuit for identifying a signal at apredetermined identification level, said signal being obtained by demodulating a multilevel orthogonal modulated signal; a clock regenerating circuit for regenerating a signal identification clock for said identifying circuit to supply said clock tosaid identifying circuit; an equalizing circuit for subjecting said signal obtained by demodulating the multilevel orthogonal modulated signal to an equalizing process; and a clock phase detecting unit for detecting a phase component of said signalidentification clock based on errors between input and output signals of said equalizing circuit and then for supplying said phase component to said clock regenerating circuit; wherein said clock phase detecting unit includes: an error detecting unitfor detecting a signal error between said input and output signals of said equalizing circuit: and a clock phase calculating unit for detecting the phase component of said signal identification clock by calculating the detection outputs from said errordetecting unit..].
2. .[.A clock phase detecting circuit arranged in a receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, comprising: an identifying circuit for identifying a .Iadd.demodulated.Iaddend.signal at a predetermined identification level, said .Iadd.demodulated .Iaddend.signal being obtained by demodulating a multilevel orthogonal modulated signal; a clock regenerating circuit for regenerating a signal identification clock for saididentifying circuit to supply said .Iadd.signal identification .Iaddend.clock to said identifying circuit; an equalizing circuit for subjecting said .Iadd.demodulated .Iaddend.signal obtained by demodulating the multilevel orthogonal modulated signal toan equalizing process; and a clock phase detecting unit for detecting a phase component of said signal identification clock based on input and output signals of said equalizing circuit and then for supplying said phase component to said clockregenerating circuit; wherein said clock phase detecting unit comprising: an error detecting unit for detecting a signal error between said input and output signals of said .[.equilizing.]. .Iadd.equalizing .Iaddend.circuit; a signal inclinationdetecting unit for detecting the inclination of said demodulated signal; and a clock phase calculating unit for operating the phase component of said signal identification clock by calculating based on respective outputs from said error detecting unitand said signal inclination detecting unit.
3. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 2, wherein said signal inclination detecting unit comprising:a delaying unit for delaying the output from said identifying circuit; and a comparing unit for comparing the output from said identifying circuit with the output from said delaying unit to detect the inclination of said demodulated signal.
4. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 2, wherein said identifying circuit is operated with highspeed clocks; and wherein said signal inclination detecting unit comprising: a delaying unit for delaying the output from said identifying circuit, said delaying unit being operated with said high speed clocks; a latching unit for holding the outputfrom said identifying circuit and the output from said delaying unit with clocks slower than said high speed clocks; and a comparing unit for comparing the output of said identifying circuit held in said latching unit with the output from said delayingunit to detect the inclination of said demodulated signal.
5. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 2, wherein said identifying circuit comprises pluralidentifying units corresponding to the number of plural demodulated signals obtained by demodulating said multilevel orthogonal modulated signal; and wherein said signal inclination detecting unit includes a comparing unit that compares outputs of saidplural identifying units with each other to detect the inclination of the demodulated signal when clocks with different predetermined phase shift between said .Iadd.plural .Iaddend.identifying units are supplied to said plural identifying units.
6. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 2, wherein said clock phase calculating unit is formed as amultiplying unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to a multiplying calculating process.
7. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 2, wherein said clock phase calculating unit is formed as anexclusive OR calculating unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to an exclusive OR calculation process.
8. .[.A clock phase detecting circuit arranged in a receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, comprising: an identifying circuit for identifying a .Iadd.demodulated.Iaddend.signal at a predetermined identification level, said .Iadd.demodulated .Iaddend.signal being obtained by demodulating a multilevel orthogonal modulated signal; a clock regenerating circuit for regenerating a signal identification clock for saididentifying circuit to supply said .Iadd.signal identification .Iaddend.clock to said identifying circuit; an equalizing circuit for subjecting said .Iadd.demodulated .Iaddend.signal obtained by demodulating the multilevel orthogonal modulated signal toan equalizing process; and a clock phase detecting unit for detecting a phase component of said signal identification clock based on input and output signals of said equalizing circuit and then for supplying said phase component to said clockregenerating circuit; wherein said clock phase detecting unit comprises: an error detecting unit for detecting .[.an.]. .Iadd.the .Iaddend.input .[.signal to output signal error.]. .Iadd.and output signals .Iaddend.of said .[.equilizing.]. .Iadd.equalizing .Iaddend.circuit; a signal inclination detecting unit for detecting the inclination of said demodulated signal; a clock phase calculating unit for detecting the phase component of said signal identification clock by calculating basedon the respective outputs from said error detecting unit and said signal inclination detecting unit; a specific signal judging unit for judging whether a specific signal exists; and a gating unit for .[.producting.]. .Iadd.producing .Iaddend.the phasecomponent of said signal identification clock obtained by said clock phase calculating unit when said specific signal judging unit judges that said specific signal exists.
9. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 8, wherein said signal inclination detecting unit comprising:a delaying unit for delaying the output from said identifying circuit; and a comparing unit for comparing the output from said identifying circuit with the output from said delaying unit to detect the inclination of said demodulated signal.
10. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 8, wherein said identifying circuit is operated with highspeed clocks; and wherein said signal inclination detecting unit comprising: a delaying unit for delaying the output from said identifying circuit, said delaying unit being operated with said high speed clocks; a latching unit for holding the outputfrom said identifying circuit and the output from said delaying unit with clocks slower than said high speed clocks; and a comparing unit for comparing the output of said identifying circuit held in said latching unit with the output from said delayingunit to detect the inclination of said demodulated signal.
11. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 8, wherein said identifying circuit comprises pluralidentifying units corresponding to the number of plural demodulated signals obtained by demodulating said multilevel orthogonal modulation signal; and wherein said signal inclination detecting unit includes a comparing unit that compares outputs of saidplural identifying units with each other to detect the inclination of the demodulated signal when clocks with different predetermined phase amount between said .Iadd.plural .Iaddend.identifying units are supplied to said plural identifying units.
12. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 8, wherein said clock phase calculating unit is formed as amultiplying unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to a multiplying calculating process.
13. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 8, wherein said clock phase calculating unit is formed as anexclusive OR calculating unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to an exclusive OR calculation process.
14. .[.The clock phase detecting circuit arranged in the receiving.]. .Iadd.A receiver circuit arranged in a receiving .Iaddend.unit of multiplex radio equipment, according to claim 8, wherein said specific signal judging unit includes pluralsignal judging units that judge plural kinds of specific signals, and further comprising a selecting unit arranged between said .[.specific signal judging unit.]. .Iadd.plural signal judging units .Iaddend.and said .[.gate.]. .Iadd.gating.Iaddend.unit, for selecting decision results from said plural signal judging units. |
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