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Semiconductor device and timing control circuit |
| RE40205 |
Semiconductor device and timing control circuit
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| Patent Drawings: | |
| Inventor: |
Funaba, et al. |
| Date Issued: |
April 1, 2008 |
| Application: |
10/226,019 |
| Filed: |
August 23, 2002 |
| Inventors: |
Funaba; Seiji (Chiyoda-ku, JP)
Nishio; Yoji (Chiyoda-ku, JP)
Okuda; Yuichi (Chiyoda-ku, JP)
Nakagome; Yoshinobu (Chiyoda-ku, JP)
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| Assignee: |
Elpida Memory, Inc. (Tokyo, JP) |
| Primary Examiner: |
Nguyen; Tan T. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Reed Smith LLPFisher, Esq.; Stanley P.Marquez, Esq.; Juan Carlos A. |
| U.S. Class: |
365/194; 327/158; 327/161 |
| Field Of Search: |
327/161 |
| International Class: |
G11C 11/4076 |
| U.S Patent Documents: |
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| Foreign Patent Documents: |
10-112182; 10-283060; 11-127062; 11-127063 |
| Other References: |
JPO Notice of Reason of Refusal dated Oct. 26, 2007, in Japanese with English translation. cited by other. |
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| Abstract: |
.[.Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals..]. .Iadd.Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals..Iaddend. |
| Claim: |
What is claimed is:
1. A clock signal generating circuit comprising: a first delay circuit which receives a first clock signal and outputs a second clock signal, said second clock being adelayed signal to said first clock signal; a first circuit which outputs a third clock signal, said third clock signal being a frequency-divided signal to said first clock signal; a second circuit which outputs a fourth clock signal, said fourth clocksignal being a frequency-divided signal to said second clock signal; a second delay circuit which receives a fourth clock signal and outputs a fifth clock signal, said fifth clock signal being a delayed signal to said fourth clock signal; and a controlcircuit which compares said third clock signal and said fifth clock signal and controls said first delay circuit so that an output timing of said second clock signal is changed.
2. A clock signal generating circuit according to claim 1, further including a memory array having a plurality of memory cells and an output circuit which receives data read from said memory array, and wherein said output circuit is controlledbased on the second clock.
3. A clock signal generating circuit comprising: a clock forming circuit including, a first delay circuit which receives a first clock having a first cycle and thereby outputs a second clock obtained by delaying the first clock; a second delaycircuit which outputs a second signal obtaining by delaying a first signal in response to the second signal; and a control circuit which determines the state of the second signal at the time that a third clock having a second cycle has changed from afirst level to a second level, in response to the third clock and the second signal, and outputs a control signal based on the result of determination to said first delay circuit; and wherein said second delay circuit is set to an initial state inresponse to a fourth clock having the second cycle and formed on one semiconductor substrate.
4. A clock signal generating circuit according to claim 3, wherein said second delay circuit includes a plurality of inverter circuits, and an input terminal of at least one inverter circuit of said plurality of inverter circuits is set to apredetermined potential in response to the fourth clock.
.Iadd.5. A semiconductor memory, comprising: a clock forming circuit including a first variable delay circuit which receives a first clock signal and outputs a second clock signal obtained by delaying said first clock signal; a second variabledelay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal; a first delay circuit which receives said second signal and outputs a third signal; a control circuit which compares said third signal and afourth signal and controls said first variable delay circuit in accordance with the compared result; and a signal generator which outputs said first and fourth signals, wherein said second variable delay circuit is able to be reset so that the remainingsignal in said second variable delay circuit is erased after said control circuit compares said third signal and said fourth signal..Iaddend.
.Iadd.6. A semiconductor memory according to claim 5, wherein a circuit configuration of said first variable delay circuit is identical to that of said second variable delay circuit..Iaddend.
.Iadd.7. A semiconductor memory according to claim 5, further comprising an output circuit which performs a data output operation in synchronism with a change in said second clock..Iaddend.
.Iadd.8. A semiconductor memory, comprising: a clock forming circuit including, a first variable delay circuit which receives a first clock and outputs a second clock obtained by delaying said first clock; a second variable delay circuit whichreceives a first signal and outputs a second signal obtained by delaying said first signal; a first delay circuit which receives said second signal and outputs a third signal; a control circuit which compares said third signal and a fourth signal andcontrols said first variable delay circuits in accordance with the compared result; and a signal generator which outputs said first and fourth signals, wherein said first delay circuit is able to be reset so that the remaining signal in said first delaycircuit is erased after said control circuit compares said third signal and said fourth signal..Iaddend.
.Iadd.9. A semiconductor memory according to claim 8, wherein a circuit configuration of said first variable delay circuit is identical to that of said second variable delay circuit..Iaddend.
.Iadd.10. A semiconductor memory according to claim 8, further comprising an output circuit which performs a data output operation in synchronism with a change in said second clock..Iaddend.
.Iadd.11. A semiconductor memory, comprising: a clock forming circuit including, a first variable delay circuit which receives a first clock and outputs a second clock obtained by delaying said first clock; a first delay circuit which receivesa first signal and outputs a second signal obtained by delaying said first signal, said first delay circuit having a second variable delay circuit and second delay circuit which are connected in series; a control circuit which compares said secondsignal and a third signal and controls said first variable delay circuits in accordance with the compared result; and a signal generator which outputs said first and third signals, wherein said second variable delay circuit is able to be reset therebythe remaining signal in said second variable delay circuit is erased after the comparing operation of said control circuit..Iaddend.
.Iadd.12. A semiconductor memory according to claim 11, wherein said second delay circuit is able to be reset thereby the remaining signal in said second delay circuit is erased after the comparing operation of said control circuit..Iaddend.
.Iadd.13. A semiconductor memory according to claim 11, wherein said second delay circuit receives an output signal of said second variable delay circuit and outputs said second signal..Iaddend.
.Iadd.14. A semiconductor memory according to claim 11, wherein a circuit configuration of said first variable delay circuit is identical to that of said second variable delay circuit..Iaddend.
.Iadd.15. A semiconductor memory according to claim 11, further comprising an output circuit which performs a data output operation in synchronism with said second clock..Iaddend. |
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