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Fast circuit switching system |
| RE32900 |
Fast circuit switching system
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| Patent Drawings: | |
| Inventor: |
Orsic |
| Date Issued: |
April 4, 1989 |
| Application: |
07/059,713 |
| Filed: |
June 8, 1987 |
| Inventors: |
Orsic; Milo (Lincolnwood, IL)
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| Assignee: |
American Telephone and Telegraph Company, AT&T Bell Laboratories (Murray Hill, NJ) |
| Primary Examiner: |
Griffin; Robert L. |
| Assistant Examiner: |
Scutch, III; Frank M. |
| Attorney Or Agent: |
Watland; Ross T. |
| U.S. Class: |
370/359; 370/384 |
| Field Of Search: |
370/54; 370/58; 370/68; 370/89; 379/221; 379/273 |
| International Class: |
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| U.S Patent Documents: |
3956593; 4005272; 4038497; 4123624; 4201889; 4201890; 4201891; 4383315; 4392221; 4680757 |
| Foreign Patent Documents: |
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| Other References: |
"Pulse Code Modulation Tandem Exchange Field Trial Model", by D. J. Rose, Electrical Communication, vol. 46, No. 4, 1971..
"A Review of Classification Schemes for Computer Communication Networks", by William Greene, Computer, Nov. 1977, reprinted in Tutorial: Distributed Processor Communication Architecture, by Kenneth J. Thurber, pp. 135-144..
International Switching Symposium, May 7-11, 1979, paper 20B3, pp. 246-252, Paris (FR) Araki et al.: "The KD 250 M telex and data switching system", see pp. 247-249, paragraph 3..
International Switching Symposium, May 7-11, 1979, paper 40C2, pp. 834-839, Paris (FR), Doret: "A nodal structure switching network", see p. 837, paragraph 4..
National Telecommunications Conference, 11/29/81-12/3/81, paper D.5.1, pp. 1-5, New Orleans (U.S.), Motoyama et al.: "A subscriber loop multiplexing system for integrated service digital networks", see pp. 2 and 3, paragraph III..
"Performance Evaluation of a Distributed Burst-Switched Communications System", by James D. Morse and Stanley J. Kopec, Jr., Conference Proceedings, Phoenix Conference on Computers and Communications, Mar. 1983, pp. 41-46.. |
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| Abstract: |
A fast circuit switching system that establishes a circuit for each packet-sized data communication. Information is conveyed from a number of communications modules in source channels to a number of port controllers and to a network. Information is conveyed from the network to destination channels. Each communications module includes a transmitter that transmits in an associated source channel, circuit setup request signals defining destination channels and also transmits data. Each port controller stores one of a number of status words defining the availability of the destination channels and each of these status words is cycled to each port controller. A port controller responds to one of the circuit setup request signals and to subsequent data, when one of the status words cycled thereto defines as available, a destination channel defined by the circuit setup request signal, by transmitting the circuit setup request signal and the subsequent data to the network. The network responds to circuit setup request signals received from the port controllers by transmitting data received from the port controllers to the destination channels defined by those circuit setup request signals. |
| Claim: |
What is claimed is:
1. A communications system comprising
a plurality of source channels for conveying information,
a plurality of destination channels for conveying information,
a plurality of communications modules each associated with at least one of said source channels and each comprising transmitter means for transmitting, on the at least one associated source channel, circuit setup request signals and data, each ofsaid circuit setup request signals defining at least one of said destination channels,
a plurality of controllers each comprising storage means for storing one of a plurality of status words each defining the availability of at least one of said destination channels,
means for cycling each of said status words to the storage means of each of said controllers and
a network,
wherein each of said controllers is associated with at least one of said source channels and further comprises
means for receiving information on the at least one associated source channel and
means responsive to one of said circuit setup request signals and to subsequent data, when one of said status words cycled to the storage means of that controller defines as available one of said destination channels that is defined by thatcircuit setup request signals, for transmitting that circuit setup request signal and said subsequent data to said network, and
wherein said network comprises means responsive to circuit setup request signals received from said controllers for transmitting data received from said controllers to ones of said destination channels defined by those circuit setup requestsignals.
2. A communications system in accordance with claim 1 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals, when one of said status words cycled to the storage means of that controller defines as available one of said destination channels that is defined by that circuit setup requestsignal, for modifying that status word to define that destination channel as not available.
3. A communications system in accordance with claim 1 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when one of said status words cycled to the storage means of that controller defines as available one of said destinationchannels that is defined by that circuit setup request signal, for transmitting a circuit set response signal in one of said destination channels to said given communications module and
wherein each of said communications modules further comprises
means responsive to a circuit set response signal transmitted by one of said controllers in one of said destination channels, for inhibiting the transmission of circuit setup request signals and initiating the transmission of data by thatcommunications module.
4. A communications system in accordance with claim 1 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when one of said status words cycled to the storage means of that controller defines as not available one of said destinationchannels that is defined by that circuit setup request signal, for transmitting a destination busy response signal in one of said destination channels to said given communications module and
wherein each of said communication modules further comprises
means responsive to a destination busy response signal transmitted by one of said controllers in one of said destination channels, for continuing the transmission of circuit setup request signals by that communications module.
5. A communications system in accordance with claim 1 wherein the transmitter means of each of said communications modules further comprises
means for transmitting on the at least one source channel associated with that communications module, circuit disconnect request signals each defining at least one of said destination channels and
wherein each of said controllers further comprises
means responsive to one of said circuit disconnect request signals, when one of said status words cycled to the storage means of that controller defines as not available one of said destination channels that is defined by that circuit disconnectrequest signal, for modifying that status word to define that destination channel as available.
6. A communications system comprising
a plurality of source channels for conveying information,
a plurality of communications modules each associated with at least one of said source channels and each comprising
transmitter means for transmitting, on the at least one associated source channel, circuit setup request signals and data, each of said circuit setup request signals defining at least one of said communications modules, and
receiver means for receiving data,
a plurality of controllers each comprising storage means for storing one of a plurality of status words each defining the availability of the receiver means of at least one of said communications modules,
means for cycling each of said status words to the storage means of each of said controllers and
a network,
wherein each of said controllers is associated with at least one of said source channels and further comprises
means for receiving information on the at least one associated source channel and
means responsive to one of said circuit setup request signals and to subsequent data, when one of said status words cycled to the storage means of that controller defines as available the receiver means of one of said communications modules thatis defined by that circuit setup request signal, for transmitting that circuit setup request signal and said subsequent data to said network, and
wherein said network comprises means responsive to circuit setup request signals received from said controllers for transmitting data received from said controllers to the receiver means of one of said communications modules defined by thosecircuit setup request signals.
7. A communications system in accordance with claim 6 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals, when one of said status words cycled to the storage means of that controller defines as available the receiver means of one of said communications modules that is defined by thatcircuit setup request signal, for modifying that status word to define the receiver means of that communications module as not available.
8. A communications system in accordance with claim 6 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when one of said status words cycled to the storage means of that controller defines as available the receiver means of one ofsaid communications modules that is defined by that circuit setup request signal, for transmitting a circuit set response signal to the receiver means of said given communications module and
wherein the receiver means of each of said communications modules further comprises
means responsive to a circuit set response signal transmitted by one of said controllers, for inhibiting the transmission of circuit setup request signals and initiating the transmission of data by that communications module.
9. A communications system in accordance with claim 6 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when one of said status words cycled to the storage means of that controller defines as not available the receiver means ofone of said communications modules that is defined by that circuit setup request signal, for transmitting a destination busy response signal to the receiver means of said given communications module and
wherein the receiver means of each of said communications modules further comprises
means responsive to a destination busy response signal transmitted by one of said controllers, for continuing the transmission of circuit setup request signals by that communications module.
10. A communications system in accordance with claim 6 wherein the transmitter means of each of said communications modules further comprises
means for transmitting, on the at least one source channel associated with that communications module, receiver available signals defining the receiver means of that communications module as available and wherein each of said controllers furthercomprises
means responsive to one of said receiver available signals received on the at least one source channel associated with that controller, when one of said status words cycled to the storage means of that controller defines the receiver means of thecommunications module associated with that source channel as not available, for modifying that status word to define the receiver means of that communications module as available.
11. A communications system comprising
a plurality of source channels for conveying information,
a plurality of destination channels for conveying information,
a plurality of communications modules each associated with at least one of said source channels and at least one of said destination channels and each comprising
transmitter means for transmitting, on the at least one associated source channel, circuit setup request signals and data, each of said circuit setup request signals defining at least one of said communications modules, and
receiver means for receiving data on the at least one associated destination channel,
a plurality of controllers each comprising storage means of storing one of a plurality of status words each defining the availability of the receiver means of at least one of said communications modules and defining the availability of the atleast one destination channel associated with that communications module,
means for cycling each of said status words to the storage means of each of said controllers and
a network
wherein each of said controllers is associated with at least one of said source channels and further comprises
means for receiving information on the at least one associated source channel and
means responsive to one of said circuit setup request signals and to subsequent data, when one of said status words cycled to the storage means of that controller defines as available the receiver means of one of said communications modules thatis defined by that circuit setup request signal and defines as available the at least one destination channel associated with that communications module, for transmitting that circuit setup request signal and said subsequent data to said network, and
wherein said network comprises means responsive to circuit setup request signals received from said controllers for transmitting data received from said controllers to ones of said destination channels defined by those circuit setup requestsignals.
12. A communications system in accordance with claim 11 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals, when one of said status words cycled to the storage means of that controller defines as available the receiver means of one of said communications modules that is defined by thatcircuit setup request signal and defines as available the at least one destination channel associated with that communications module, for modifying that status word to define the receiver means of that communications module as not available and todefine that destination channel as not available.
13. A communications system in accordance with claim 11 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when one of said status words cycled to the storage means of that controller defines as available the receiver means of one ofsaid communications modules that is defined by that circuit setup request signal and defines as available the at least one destination channel associated with that communications module, for transmitting a circuit set response signal in the at least onedestination channel associated with said given communications module and
wherein the receiver means of each of said communications modules further comprises
means responsive to a circuit set response signal transmitted by one of said controllers in the at least one destination channel associated with that communications module, for inhibiting the transmission of circuit setup request signals andinitiating the transmission of data by that communications module.
14. A communications system in accordance with claim 11 wherein each of said controllers further comprises
means responsive to one of said circuit system request signals received from a given one of said communications modules, both when one of said status words cycled to the storage means of that controller defines as not available the receiver meansof one of said communications modules that is defined by that circuit setup request signal and also when one of said status words cycle to the storage means of that controller defines as not available the at least one destination channel associated withsaid last-mentioned communications module, for transmitting a destination busy response signal in the at least one destination channel associated with said given communications module and
wherein the receiver means of each of said communications modules further comprises
means responsive to a destination busy response signal transmitted by one of said controllers in the at least one destination channel associated with that communications module, for continuing the transmission of circuit setup request signals bythat communications module.
15. A communications system in accordance with claim 11 wherein the transmitter means of each of said communications modules further comprises
means for transmitting, on that at least one source channel associated with that communications module, receiver available signals defining the receiver means of that communications modules as available and wherein each of said controllersfurther comprises
means responsive to one of said receiver available signals received on the at least one source channel associated with that controller, when one of said status words cycled to the storage means of that controller defines the receiver means of thecommunications module associated with that source channel as not available, for modifying that status word to define the receiver means of that communication module as available.
16. A communication system in accordance with claim 11 wherein the transmitter means of each of said communications modules further comprises
means for transmitting, on the at least one source channel associated with that communications module, circuit disconnect request signals each defining at least one of said destination channels and wherein each of said controllers furthercomprises
means responsive to one of said circuit disconnect request signals, when one of said status words cycled to the storage means of that controller defines as not available one of said destination channels that is defined by that circuit disconnectrequest signal, for modifying that status word to define that destination channel as available.
17. A communications system comprising
a plurality of source channels for conveying information,
a plurality of destination channels for conveying information,
a plurality of communications modules each associated with at least one of said source channels and each comprising transmitter means for transmitting, on the at least one associated source channel, circuit setup request signals and data, each ofsaid circuit setup request signals defining one of said destination channels,
a network and
an N-plurality of controllers each associated with at least one of said source channels, N being a positive integer greater than one, wherein each of said controllers comprises
storage means for storing one of a plurality of status words each defining the availability of at least one of said destination channels,
a status word transmitter,
means for receiving information on the at least one source channel associated with that controller and
means responsive to one of said circuit setup request signals and to subsequent data, when the status word stored in the storage means of that controller defines as available the destination channel that is defined by that circuit setup requestsignal, for transmitting that circuit setup request signal and said subsequent data to said network,
wherein, for each integer j from zero through N-l, with k being the integer resulting from the modulo-N addition of one to the integer j and with l being the integer resulting from the modulo-N addition of one to the integer k, the status wordtransmitter of the kth controller comprises means for transmitting each status word stored by the storage means of the kth controller to the lth controller and wherein the storage means of the kth controller further comprises means for receiving forstorage each status word transmitted by the status word transmitter of the jth controller and
wherein said network comprises means responsive to circuit setup request signals received from said controllers for transmitting data received from said controllers to ones of said destination channels defined by those circuit setup requestsignals.
18. A communications system in accordance with claim 17 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals, when the status word stored in the storage means of that controller defines as available the destination channel that is defined by that circuit setup request signal, for modifyingthat status word to define that destination channel as not available.
19. A communication system in accordance with claim 17 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when the status word stored in the storage means of that controller defines as available the destination channel that isdefined by that circuit setup request signal, for transmitting a circuit set response signal in one of said destination channels to said given communications module and
wherein each of said communications modules further comprises
means responsive to a circuit set response signal transmitted by one of said controllers in one of said destination channels, for inhibiting the transmission of circuit setup request signals and initiating the transmission of data by thatcommunications module.
20. A communications system in accordance with claim 17 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when the status word stored in the storage means of that controller defines as not available the destination channel that isdefined by that circuit setup request signal, for transmitting a destination busy response signal in one of said destination channels to said given communications module and
wherein each of said communications modules further comprises
means responsive to a destination busy response signal transmitted by one of said controllers in one of said destination channels, for continuing the transmission of circuit setup request signals by that communications module.
21. A communication system in accordance with claim 17
wherein the transmitter means of each of said communications modules further comprises
means for transmitting, on the at least one source channel associated with that communications module, circuit disconnect request signals each defining one of said destination channels and
wherein each of said controllers further comprises
means responsive to one of said circuit disconnect request signals, when the status word stored in the storage means of that controller defines as not available the destination channel that is defined by that circuit disconnect request signal,for modifying that status word to define that destination channel as available.
22. A communications system comprising
a plurality of source channels for conveying information,
a plurality of communications modules each associated with at least one of said source channels and each comprising
transmitter means for transmitting, on the at least one associated source channel, circuit setup request signals and data, each of said circuit setup request signals defining one of said communications modules, and
receiver means for receiving data,
a network and
an N-plurality of controllers each associated with at least one of said source channels, N being a positive integer greater than one, wherein each of said controllers comprises
storage means for storing one of a plurality of status words each defining the availability of the receiver means of at least one of said communications modules,
a status word transmitter,
means for receiving information on the at least one source channel associated with that controller and
means responsive to one of said circuit setup request signals and to subsequent data, when the status word stored in the storage means of that controller defines as available the receiver means of the communications module that is defined by thatcircuit setup request signal, for transmitting that circuit setup request signal and said subsequent data to said network.
wherein, for each integer j from zero through N-l, with k being the integer resulting from the modulo-N addition of one to the integer j and with l being the integer resulting from the modulo-N addition of one to the integer k, the status wordtransmitter of the kth controller comprises means for transmitting each status word stored by the storage means of the kth controller to the lth controller and wherein the storage means of the kth controller further comprises means for receiving forstorage each status word transmitted by the status word transmitter of the jth controller and
wherein said network comprises means responsive to circuit setup request signals received from said controllers for transmitting data received from said controllers to the receiver means of ones of said communications modules defined by thosecircuit setup request signals.
23. A communications system in accordance with claim 22 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals and to subsequent data, when the status word stored in the storage means of that controller defines as available the receiver means of the communications module that is defined by thatcircuit setup request signal, for modifying that status word to define the receiver means of that communications module as not available.
24. A communications system in accordance with claim 22 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when the status word stored in the storage means of that controller defines as available the receiver means of thecommunications module that is defined by that circuit setup request signal, for transmitting a circuit set response signal to the receiver means of said given communications module and
wherein the receiver means of each of said communications modules further comprises
means responsive to a circuit set response signal transmitted by one of said controllers, for inhibiting the transmission of circuit setup request signals and initiating the transmission of data by that communications module.
25. A communication system in accordance with claim 22 wherein each of said controllers further comprises
means responsive to one of said circuit setup request signals received from a given one of said communications modules, when the status word stored in the storage means of that controller defines as not available the receiver means of thecommunications module defined by the circuit setup request signal, for transmitting a destination busy response signal to the receiver means of said given communications module and
wherein the receiver means of each of said communications modules further comprises
means responsive to a destination busy response signal transmitted by one of said controllers, for continuing the transmission of circuit setup request signals by that communications module.
26. A communications system in accordance with claim 22 wherein the transmitter means of each of said communications modules further comprises
means for transmitting, on the at least one source channel associated with that communications module, receiver available signals defining the receiver means of that communications module as available and
wherein each of said controllers further comprises
means responsive to a given receiver available signal received on the at least one source channel associated with that controller, when the status word stored in the storage means of that controller defines the receiver means of thecommunications module associated with that source channel as not available, for modifying that status word to define the receiver means of that communications module as available.
27. An arrangement comprising
a plurality of communications modules each comprising means for transmitting circuit setup request signals and data, each of said circuit setup request signals defining one of a plurality of destinations,
a plurality of controllers each comprising storage means for storing one of a plurality of status words each defining the availability of at least one of said destinations and
means for cycling each of said status words to the storage means of each of said controllers,
wherein each of said controllers is associated with at least one of said modules and further comprises means for receiving information from said at least one of said modules and
means responsive to one of said request signals and to one of said status words cycled to the storage means of said each of said controllers and defining as available one of said destinations defined by said one of said request signals, fortransmitting a circuit set response signal to said at least one of said modules, and
wherein each of said modules further comprises
means responsive to a receipt of a circuit set response signal from one of said controllers, for inhibiting the transmission of circuit setup request signals and initiating the transmission of data by said each of said modulus.
28. An arrangement comprising
a plurality of communications modules each comprising means for transmitting circuit setup request signals and data, each of said circuit setup request signals defining one of a plurality of destinations,
a plurality of controllers each comprising storage means for storing one of a plurality of status words each defining the availability of at least one of said destinations and
means for cycling each of said status words to the storage means of each of said controllers,
wherein each of said controllers is associated with at least one of said modules and further comprises
means for receiving information from said at least one of said modules and
means responsive to one of said request signals and to one of said status words cycled to the storage means of said each of said controllers and defining as not available one of said destinations defined by said one of said request signals, fortransmitting a destination busy response signal to said at least one of said modules, and
wherein each of said modules further comprises means responsive to a receipt of a destination busy response signal from one of said controllers, for continuing the transmission of circuit setup request signals by said each of said modules. .Iadd.29. An arrangement comprising
a plurality of communications modules each comprising means for transmitting circuit setup request signals and data, each of said circuit setup request signals defining one of a plurality of destinations,
a plurality of controllers each comprising storage means for storing one of a plurality of status words each defining the availability of at least one of said destinations and
means for cycling, independently of transmission of circuit setup request signals by said modules, each of said status words among the storage means of each of said controllers in sequence,
wherein each of said controllers is associated with at least one of said modules and further comprises means for receiving information from said at least one of said modules and
means responsive to one of said request signals and to one of said status words cycled to the storage means of said each of said controllers and defining as available one of said destinations defined by said one of said request signals, fortransmitting a circuit set response signal to said at least one of said modules, and
wherein each of said modules further comprises means responsive to a receipt of a circuit set response signal from one of said controllers, for initiating the transmission of data by said each of said modules. .Iaddend. .Iadd.30. Anarrangement comprising
a plurality of means for transmitting data,
a plurality of controllers each comprising storage means for storing one of a plurality of status words each defining the availability status of at least one of a plurality of destinations and
means for cycling, independently of transmission requests by said transmitting means, each of said status words among the storage means of each of said controllers in sequence,
wherein each of said controllers is associated with at least one of said transmitting means and further comprises means, responsive to one of said status words cycled to the storage means of said each controller and defining one of saiddestinations as available, for enabling a transmission of data to said defined available destination by said at least one of said transmitting means associated with said each controller.
.Iaddend. .Iadd.31. An arrangement comprising
a plurality of means for transmitting data,
a plurality of controllers each associated with at least one of said transmitting means and
means for cycling, independently of transmission requests by said transmitting means, status information, defining the availability of at least one of a plurality of destinations, among said controllers in sequence,
wherein each of said controllers comprises means, responsive to status information cycled to said each controller and defining one of said destinations as available, for controlling a transmission of data to said defined available destination byone of said transmitting means that is associated with said each controller. .Iaddend. |
| Description: |
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to the application of M. Orsic, Ser. No. 558,504, filed Dec. 6, 1983, entitled, "Time-Slot Interchanger for Fast Circuit Switching".
TECHNICAL FIELD
This invention relates to circuit switching systems and, more particularly, to such systems that have significantly shorter circuit setup times and less central control involvement that prior systems and that ensure reliable data communicationwithout requiring complex flow control protocols.
BACKGROUND OF THE INVENTION
Circuit switching is a method of network switching where a dedicated circuit, e.g., a physical path from transmitter to receiver or a particular time slot on such physical path, is established before and maintained throughout each communication. Circuit switching has long been used for voice communication. However, because of the long circuit setup times and the dedication of switch resources for call duration that are involved with known circuit switching networks, packet switching istypically used for data communication since such communication usually occurs in short, high-rate bursts, with long pauses between bursts. Packet switching networks are characterized in that messages are broken down into standard-size packets which areindividually routed through the network and in that computers using sophisticated software packages are employed to perform the packet switching functions at the nodes within the network. Flow control protocols are frequently used to relieve thecongestion that can occur within the network. With buffer storage allocation, a known flow control protocol discussed in an article by W. Green and U. W. Pooch, "A Review of Classification Schemes for Computer Communication Networks," Computer, November1977, a data transmitter requests allocation of message reassembly space in the destination data receiver before transmitting the message. This prevents packets from accumulating in the network when the receiver buffer is full. A second alternative, tohave the receiver notify the transmitter when a received packet must be discarded, requires each such packet, to be transmitted at least twice. Both protocol alternatives require relatively complex software implementations.
Because of evolving technological advances useful in implementng circuit switching networks and because of the complexity of known packet switching systems, circuit switching is sometimes a preferable alternative for use in many datacommunication applications. However, the long circuit setup times associated with known telephone switching systems make such systems impractical for applications requiring that a circuit be established for each packet-sized data communication. In suchsystems, circuits are typically established by a central control complex only after an available network path is found by hunting through a large, centralized database. Not only is such a path hunt slow, but many additional communications are requiredboth to request circuits and to keep the centralized database informed of every network status change.
In view of the foregoing, two recognized problems in the art are the undesirably long circuit setup times in known circuit switching systems and the considerable degree of central control involvement required to use a centralized database forcircuit setups. Another problem is the complexity of the flow control mechanisms used in known data communication systems.
SUMMARY OF THE INVENTION
The aforementioned problems are solved and a technical advance is achieved in accordance with the principles of an illustrative embodiment of the invention in a fast circuit switching system having a departure in the art including a specificexemplary arrangement that achieves fast circuit setups by repetitively making available to a number of controllers connected to the data transmitters, each status word in a small distributed database defining the availability of the data receivers andthe communication channels thereto. A given data transmitter begins transmitting data only after having transmitted one or more circuit setup request signals to its controller and after having been informed thereby that a circuit has been established inresponse. Advantageously, such a circuit is established as soon as a status word subsequently made available to that controller defines both the requested destination receiver and the requested destination channel as available. Therefore, circuit setuptime is limited only by the periodic rate at which status words are made available to the controllers and no complex flow control protocols are required since data is queued by the transmitters until reliable transmission to destination data receivers isassured.
An arrangement in accordance with the invention has a number of communications modules that transmit circuit setup request signals defining destinations, and also transmit data. A number of controllers each store one of a number of status wordsdefining the availability of destinations and each of the status words is cycled to each controller. Each controller receives information from an associated communications module. A controller responds to one of the circuit setup request signals whenone of the status words cycled to that controller defines as available a destination defined by the circuit setup request signal, by transmitting a circuit set response signal to the associated communication module. The communication modules respond tocircuit set response signals by inhibiting the transmission of circuit setup request signals and initiating the transmission of data. In another arrangement in accordance with the invention, a controller responds to a circuit setup request signal whenone of the status words cycled to that controller defines as not available the destination defined by the circuit setup request signal, by transmitting a destination busy response signal to the associated communications module. Communications modulesresponse to destination busy response signals by continuing the transmission of circuit setup request signals.
In a communications system in accordance with the invention, information is conveyed from a number of communications modules in source channels to a number of controllers and to a network. Information is conveyed from the network to destinationchannels. Each communications module includes a transmitter that transmits in an associated source channel, circuit setup request signals defining destination channels, and also transmits data. Each controller stores one of a number of status wordsdefining the availability of the destination channels and each of these status words is cycled to each controller. A controller responds to one of the circuit setup request signals and to subsequent data, when one of the status words cycled theretodefines as available a destination channel defined by the circuit setup request signal, by transmitting the circuit setup request signal and the subsequent data to the network. The network responds to circuit setup request signals received from thecontrollers by transmitting data received from the controllers to the destination channels defined by those circuit setup request signals.
In a communications system in accordance with a second aspect of the invention, information is again conveyed from a number of communications modules in source channels to a number of controllers and to a network. Information is conveyed fromthe network to receivers included in the communications modules. Each communications module further includes a transmitter that transmits in an associated source channel, circuit setup request signals defining communications modules, and also transmitsdata. Each controller stores one of a number of status words defining the availability of the communications module receivers and each of these status words is cycled to each controller. A controller responds to one of the circuit setup request signalsand to subsequent data, when one of the status words cycled thereto defines as available the receiver included in a communications module defined by the circuit setup request signal, by transmitting the circuit setup request signal and the subsequentdata to the network. The network responds to circuit setup request signals received from the controllers by transmitting data received from the controllers to the receivers of the communications modules defined by those circuit setup request signals.
In an illustration embodiment of a communications system in accordance with the invention, the status words define both the availability of the communications module receivers and the availability of the destination channels. A controllerresponds to one of the circuit setup request signals and to subsequent data, when one of the status words cycled thereto defines as available the receiver of a communications module defined by the circuit setup request signal and defines as available adestination channel associated with that communications module, by transmitting the circuit setup request signal and the subsequent data to the network. The controllers also modify status words and transmit circuit set and destination busy responsesignals in response to circuit setup request signals. A controller responds to a circuit setup request signal received from a given communications module, when one of the status words cycled to the controller defines as available the receiver of acommunications module defined by the circuit setup request signal and defines as available a destination channel associated with that communications module, by modifying the status word to define that destination channel and the receiver of thatcommunications module as not available and by transmitting a circuit set response signal in a destination channel to the given communication module. The communications modules respond to circuit set response signals by inhibiting the transmission ofcircuit setup request signals and initiating the transmission of data. A controller responds to a circuit setup request signal received from a given communications module, both when one of the status words cycled to the controller defines as notavailable the receiver of a communications module defined by the circuit setup request signal and also when one of the status words cycled to the controller defines as not available an associated destination channel, by transmitting a destination busyresponse signal in a destination channel to the given communications module. The communications modules respond to destination busy response signals by continuing the transmission of circuit setup request signals. The communications module transmittersalso transmit in their associated source channels, circuit disconnect request signals defining destination channels. A controller responds to one of the circuit disconnect request signals, when one of the status words cycled thereto defines as notavailable a destination channel defined by that circuit disconnect request signal, by modifying the status word to define that destination channel as available. The communications module transmitters also transmit in their associated source channels,receiver available signals defining the communications module receivers as available. A controller responds to a receiver available signal received in one of the source channels, when one of the status words cycled thereto defines the receiver of thecommunications module associated with that source channel as not available, by modifying that status word to define the receiver of that communications module as available.
DRAWING DESCRIPTION
FIG. 1 is a block diagram of an illustrative fast circuit switching system in accordance with the present invention that advantageously establishes a circuit for each packet-sized data communication without the long setup times and centralcontrol involvement of known circuit switching systems;
FIG. 2 is a block diagram of a time-slot interchanger included in a network which is a part of the system of FIG. 1;
FIG. 3 is a block diagram of a communications module included in the system of FIG. 1;
FIGS. 4 through 9, when arranged in accordance with FIG. 23, is a detailed diagram of a port controller included in the system of FIG. 1, illustrating the mechanism in accordance with the invention that achieves fast circuit setups byrepetitively cycling to each port controller each of a number of status words defining destination availability;
FIG. 10 is a block diagram of the network included in the system of FIG. 1;
FIGS. 11 through 16, when arranged in accordance with FIG. 24, is a more detailed diagram of the time-slot interchanger of FIG. 2;
FIGS. 17 and 18 present digital word formats used on high-speed communication links included in the system of FIG. 1;
FIG. 19 is a timing diagram relevant to the port controller of FIGS. 4 through 9;
FIG. 20 is a timing diagram relevant to the time-slot interchanger of FIGS. 11 through 16;
FIG. 21 is a state diagram for a circuit included in the communications module of FIG. 3; and
FIG. 22 is a truth table for a logic circuit included in the time-slot interchanger of FIGS. 11 through 16.
FIG. 23 illustrates the proper arrangement of FIGS. 4-9.
FIG. 24 illustrates the proper arrangement of FIGS. 11-16.
GENERAL DESCRIPTION
FIG. 1 is a block diagram of an illustrative fast circuit switching system used for data communication among 256 user devices 1000-0 through 1000-255 representing any of a wide variety of devices including teleterminals, printers, computers anddatabases. Each user device 1000-0 through 1000-255 interfaces with the system via an associated one of 256 communications modules 2000-0 through 2000-255. The information transmitted by eight of the communications modules 2000-0 through 2000-7 ismultiplexed by a multiplexer/demultiplexer 3000-0 onto eight time-multiplexed source channels 0 through 7 of a high speed communications link 3001-0, e.g., a fiber optic link, for transmission to a port controller 4000-0. Similarly, the informationtransmitted by the other communications modules 2000-8 though 2000-255 is multiplexed by multiplexer/demultiplexers 3000-1 through 3000-31 onto time-multiplexed source channels 0 through 7 of high speed communications links 3000-1 through 3001-31 to portcontrollers 4000-1 through 4000-31. Information is conveyed among the port controllers 4000-0 through 4000-31 by a switching network 5000. Port controller 4000-0 transmits information received from network 5000, in eight time-multiplexed destinationchannels 0 through 7 on a high speed communications link 3002-0 to multiplexer/demultiplexer 3000-0, which demultiplexes that information for transmission to the eight communications modules 2000-0 through 2000-7. Similarly, port controllers 4000-1through 4000-31 transmit information received from network 5000, in time-multiplexed destination channels 0 through 7 on high speed communications links 3002-1 through 3002-31 to the multiplexer/demultiplexers 3000-1 through 3000-31, which demultiplexthat information for transmission to communications modules 2000-8 through 2000-255. Accordingly, each of the communications modules 2000-0 through 2000-255 is permanently associated with one source channel on one of the 32, eight-channel links 3001-0through 3001-31 and with one destination channel on one of the 32 eight-channel links 3002-0 through 3002-31.
Multiplexer/demultiplexer 3000-0 transmits one 19-bit digital word during each occurrence of a source channel on line 3001-0. The format of the digital words transmitted on lines 3001-0 through 3001-31 is shown in FIG. 17. The format includes areceiver status bit used to define the availability of the communications module to receive data in its associated destination channel, a two-bit control field used to define the digital word as an idle word, a data word, a circuit setup request word ora circuit disconnect request word and a 16-bit data field. Further, for circuit setup request words and circuit disconnect request words, five bits of the data field are used to define the requested destination link of the 32 links 3002-0 through3002-31 and three bits of the data field are used to define the requested destination channel of the eight channels on the requested destination link. Equivalently, those eight data field bits define the requested destination communications module ofthe 256 communications modules 2000-0 though 2000-255.
Port controller 4000-0 transmits one 19-bit digital word during each occurrence of a destination channel on link 3002-0. The format of the digital words transmitted on links 3002-0 through 3002-31 is shown in FIG. 18. The format includes atwo-bit response field used to transmit responses to circuit setup request words or circuit disconnect request words transmitted by a given communications module. The responses to a circuit setup request word are either a circuit set response or adestination busy response and the response to a circuit disconnect request word is a circuit disconnected response. The format also has a control bit defining the digital word as either a command word or a data word and further includes a 16-bit datafield. For command words, two bits of the data field are used to convey the two possible commands, a START RECEIVING DATA command used to command a communications module to begin storing the data words received in its associated destination channel anda STOP RECEIVING DATA command used to command the communications module to stop storing the data words received in its associated destination channel.
The digital words on links 3001-0 through 3001-31, 3002-0 through 3002-31 as well as on the links between the port controllers 4000-0 through 4000-31 and network 5000 further include parity and synchronization bits (not shown) to detect errorsand maintain system synchronization, respectively. The use of such bits is well known and is, therefore, not described herein.
Information is conveyed on links 3001-0 through 3001-31 and 3002-0 through 3002-31 in frames each comprising eight time slots or channels. In contrast to voice switching systems which typically operate in 125-microsecond frames, the presentexemplary system operates in 62.5-microsecond frames. Since each communications module transmits 16 data bits per frame, the effective data rate of each communications module is 256 kilobits per second.
When a given communications module, e.g., 2000-0, wishes to establish communications with a particular destination communications module, e.g., 2000-248, communications module 2000-0 begins transmitting in its associated source channel 0 on line3001-0, circuit setup request words defining the destination channel associated with communications module 2000-248, i.e., channel 0 of link 3002-31. The port controllers 4000-0 through 4003-31 collectively maintain a database comprising thirty-two,17-bit status words defining the availability of destination channels and the availability of destination communications modules to receive data. In the present embodiment, each of the port controllers 4000-0 through 4000-31 stores one of the statuswords. The status words are repetitively cycled through each of the port controllers 4000-0 through 4000-31 via the transmission paths 4001-0 through 4001-31. Each status word includes eight bits that define the availability of the eight destinationchannels on one of the links 3002-0 through 3002-31 and eight bits that define the availability of the communications modules associated with those destination channels to receive data. One status word bit is used to define status word 0 among thesequence of 32 status words 0 through 31. In the present embodiment, port controller 4000-0 is only responsive to circuit setup request or circuit disconnect request words received from a given one of the communications modules 2000-0 through 2000-7,during one frame out of each sequence of eight consecutive frames. Port controller 4000-0 responds to one of the circuit setup request words defining destination channel 0 of link 3002-31 by storing that circuit setup request word until status word 31,defining the availability of the destination channels on link 3002-31 and the availability of the communications modules 2000-248 through 2000-255 to receive data, is cycled to port controller 4000-0 to be stored therein. If that status word indicatesthat either destination channel 0 of link 3002-31 is unavailable or that communications module 2000-248 is presently unavailable to receive data, port controller 4000-0 transmits a destination busy response to communications module 2000-0 which continuesto transmit circuit setup request words to attempt to establish communication with communications modules 2000-248. However, if the status word indicates both that destination channel 0 of link 3002-31 is available and that communications module2000-248 is available to receive data, port controller 4000-0 transmits a circuit set response to communications module 2000-0 and transmits the stored circuit setup request word to input port IP0 to network 5000. Port controller 4000-0 also modifiedstatus word 31 to define destination channel 0 of link 3002-31 as unavailable and the communications module 2000-248 as unavailable to receive data. Communications module 2000-0 receives the circuit set response and begins to transmit data words in itsassociated source channel 0 of link 3001-0 to port controller 4000-0. Port controller 4000-0 also transmits these subsequent data words on to network 5000 input port IP0. Network 5000, which comprises eight time-slot interchangers 5100-0 through 5100-7(FIG. 10), responds to the circuit setup request word by establishing a communication path via network 5000 output port OP31 and port controller 4000-31 to destination channel 0 of link 3002-31 and transmits the circuit setup request word and thesubsequent data words thereon. Port controller 4000-31 responds to the circuit setup request word by transmitting a START RECEIVING DATA command followed by the subsequent data words via destination channel 0 of link 3002-31 to communications module2000-248. Communications module 2000-248 responds to the START RECEIVING DATA command by storing each data word received in destination channel 0 of link 3002-31 for subsequent transmission to user device 1000-248.
Because of the operation of the port controllers 4000-0 through 4000-31 in conjunction with the distributed database of 32 status words, network 5000 only receives circuit setup request words defining destination channels that are available. Advantageously, network 5000 establishes a path in such a manner that the circuit setup request word and each subsequent data word are conveyed thereon with on words being lost due to delay in establishing the path. Further, no network 5000 paths areestablished to communications modules that are occupied with other tasks, e.g., processing interrupts or checking the error check code of previously received data, and are therefore not yet available to receive data. Accordingly, flow control protocolsare not required to assure that transmitted data is received since no data is transmitted until the availability of the destination channel and the availability of the destination communication module are assured.
After communications module 2000-0 has completed its data transmission to communications module 2000-248, communications module 2000-0 begins transmitting circuit disconnect request words defining destination channel 0 of link 3002-31, to portcontroller 4000-0. Port controller 4000-0 responds to one of the circuit disconnect request words by storing that circuit disconnect request word until status word 31, associated with destination channel 0 of link 3002-31 and communications module2004-248, is again cycled to port controller 4000-0 for storage therein. Port controller 4000-0 then modifies status word 31 to define destination channel 0 of link 3002-31 as available. Port controller 4000-0 does not however modify status word 31 todefine communications module 2000-248 as available to receive data. That is left for communications module 2000-248 to do. Port controller 4000-0 then transmits a circuit disconnected response to communications module 2000-0 and transmits the storedcircuit disconnect request word on to input port IP0 of network 5000. Network 5000 responds by deallocating the path to destination channel 0 of link 3002-31 but not before the circuit disconnect request word is conveyed thereon to port controller4000-31. Port controller 4000-31 responds to the circuit disconnect request word by transmitting a STOP RECEIVING DATA command to communications module 2000-248. In response to this command, communications module 2000-248 stops storing the data wordsreceived in destination channel 0 of link 3002-31 and transmits the stored data transmission from communications module 2000-0 to user device 1000-248. Only after communications module 2000-248 has completed its other tasks does it notify portcontroller 4000-31 that it is again available to receive data. Communications module 2000-248 transmits logic one receiver status bits in the digital words transmitted in source channel 0 of link 3002-31 as a receiver available signal. The next timestatus word 31 defining the availability of communications module 2000-248 to receive data is cycled to port controller 4000-31, that status word 31 is modified to define communications module 2000-248 as again available to receive data. Only then willa given communications module transmitting circuit setup request words defining communications module 2000-248 be successful in having a network 5000 path established to destination channel 0 of link 3002-31.
Network 5000 comprises eight time-slot interchangers 5100-0 through 5100-7 (FIG. 10). Each time-slot interchanger receives information from all 32 network 5000 input ports IP0 through IP31 but transmits information to only four of the 32 network5000 output ports OP0 through OP31. Accordingly, a given time-slot interchanger, e.g., 5100-0, receives 256 digital words during a given frame (eight digital words from each of the port controllers 4000-0 through 4000-31) but is required to transmitonly 32 digital words (eight digital words to each of the port controllers 4000-0 through 4000-3). A block diagram of time-slot interchanger 5100-0 is shown in FIG. 2. (A more detailed diagram of time-slot interchanger 5100-0 is shown in FIGS. 11through 16, when arranged in accordance with FIG. 24). The digital words transmitted by port controllers 4000-0 through 4000-31 are received by a TSI input circuit 5200 including a triple-buffered memory arrangement. Digital words are stored in TSIinput circuit 5200 during one frame, during the next frame any of those digital words that are circuit setup request words or circuit disconnect request words are used to appropriately change the contents of a control memory 5445 and then during a thirdframe up to 32 of those digital words are read from TSI input circuit 5200 and are transmitted via a register 5290 to be written in a TSI output circuit 5600. The reading of TSI input circuit 5200 and the writing of TSI output circuit 5600 areaccomplished in accordance with source addresses and destination addresses transmitted from control memory 5445 via paths 5487 and 5488, respectively. TSI output circuit 5600 includes a double-buffered memory arrangement. Accordingly, digital wordswritten into TSI output circuit 5600 during one frame are transmitted to port controllers 4000-0 through 4000-3 during the next frame.
In the present embodiment, a given port controller transmits at most one circuit setup request word or circuit disconnect request word to network 5000 during a given frame. Since TSI input circuit 5200 receives information from all 32 of theport controllers 4000-0 through 4000-31, TSI input circuit 5200 receives at most 32 circuit setup request or circuit disconnect request words during one frame. For each circuit setup request word defining a circuit to one of the communications modules2000-0 through 2000-31 that is received during a given frame, a new connection word is stored in a new connection word storage arrangement 5410. (Recall that time-slot interchanger 5100-0 transmits information to only the 32 communications modules2000-0 through 2000-31.) Each new connection word stored includes a source address defining the one out of 256 communications modules that has initiated the circuit setup request and a destination address that defines the one out of 32 possiblecommunications modules that is the requested destination. For each circuit disconnect request word defining a circuit to one of the communications modules 2000-0 through 2000-31 that is received during the given frame, a disconnection word is stored ina disconnection word storage arrangement 5460. Each disconnection word defines one of the 32 possible destination communications modules 2000-0 through 2000-31 that is to be disconnected. During the next frame, the disconnection words stored inarrangement 5460 are used to address a disconnect memory arrangement 5490 having locations associated with each of the 32 communications modules 2000-0 through 2900-31. Logic one signals are stored in each addressed location indicating that the path tothe associated communications module is to be disconnected.
Control memory 5445 comprises 32, fifteen-bit connection word storage registers: an input register 5446-0, 30 intermediate registers 5446-1 through 5446-30 and an output register 5446-31. Thirty-two times during each frame, the contents of theregisters 5446-0 through 5446-31 are shifted by one register in response to a clock signal X1 (FIG. 20). Each register 5446-0 through 5446-31 stores one digital word comprising a six-bit destination address (bits 0 through 5) and a nine-bit sourceaddress (bits 6 through 14). If a digital word stored in control memoyr 5445 has a logic one in bits 0 and 6 it is a connection word, i.e., it represents an established connection. Otherwise, it is a null word representing no established connection. For connection words, bits 1 through 5 define one of 32 locations of TSI output circuits 5600 associated with the 32 destination communications modules 2000-0 through 2000-31 and bits 7-14 define one of 256 locations of TSI input circuit 5200 associatedwith the 256 source communications modules 2000-0 through 2000-255. When a given connection word is stored in register 5446-30 on the clock signal X1, the source address of that connection word is transmitted to TSI input circuit 5200 via path 5487 andthe digital word stored in the TSI input circuit 5200 location defined by that source address is read and stored in register 5290 on a clock signal X2 (FIG. 20). When the given connection word is then shifted to output register 5446-31 on the next clocksignal X1, the destination address of that connection word is transmitted to TSI output circuit 5600 via path 5488 and the digital word stored in register 5290 is written into TSI output circuit 5600 at the location defined by that destination address. Since TSI output circuit 5600 includes a double-buffered memory arrangement, digital words written into TSI output circuit 5600 during one frame are not transmitted until the following frame and the sequential order in which transfers from TSI inputcircuit 5200 to TSI output circuit 5600 occur is unimportant. Accordingly, connection words may be stored in any sequential order in control memory 5445.
When the given connection word is stored in register 5446-30, the destination address of that connection word is transmitted to disconnect memory arrangement 5490 and the bit stored in the location thus addressed is read and stored in a one-bitdisconnect register 5495 on clock signal X2. Therefore, when the given connection word is shifted to output register 5446-31 on the next clock signal X1, the bit present in register 5495 indicates whether the connection represented by the givenconnection word is to remain connected or to be disconnected during the next frame. The bit stored in register 5495 together with bit 0 of the digital word in output register 5446-31 and bit 0 of a new connection word available on a bus 5440 from newconnection word storage arrangement 5410 are the three input signals to a select logic circuit 5496. A logic one in bit 0 of output register 5446-31 indicates that the digital word stored therein is a connection word rather than a null word. A logicone bit stored in register 5495 indicates that the connection represented by the connection word stored in register 5446-31 is to be disconnected during the next frame. A logic one on bit 0 of bus 5440 indicates that there is a new connection wordavailable to be stored in control memory 5445. Select logic circuit 5496 transmits signals to control three enable gates 5443, 5441 and 5444 in accordance with the truth table given in FIG. 22. When a null word is present in output register 5446-31 andbit 0 of bus 5440 indicates that there is a new connection word available to be stored in control memory 5445, i.e., there is a new connection to be established, select logic circuit 5496 transmits a logic one signal to enable gate 5441 and the newconnection word is transmitted via enable gate 5441 and a control memory input path 5447 and stored by input register 5446-0 on the next clock signal X1. When bit 0 of bus 5440 indicates that there is no new connection word available, select logiccircuit 5496 transmits a logic one signal to enable gate 5443 and a null word comprising all logic zero bits is transmitted via enable gate 5443 from a zero register 5442 and stored by input register 5446-0 on the next clock signal X1. When a connectionword rather than a null word is present in output register 5446-31 and the bit in register 5495 indicates that the connection is not to be disconnected, select logic circuit 5496 transmits a logic one signal to enable gate 5444 and the connection wordstored in output register 5446-31 is shifted via enable gate 5444 to input register 5446-0 on the next clock signal X1. However, when the bit in register 5495 indicates that the connection is to be disconnected and bit 0 of bus 5440 indicates that thereis a new connection word available to be stored in control memory 5445, i.e., there is a new connection to be established, select logic circuit 5496 transmits a logic one signal to enable gate 5441 and the new connection word is transmitted via enablegate 5441 and stored by input register 5446-0 on the next clock signal X1. Finally, when the bit in register 5495 indicates that the connection is to be disconnected but bit 0 of bus 5440 indicates that there is no new connection word available to bestored in control memory 5445, select logic circuit 5496 transmits a logic one signal to enable gate 5443 and a null word comprising all logic zero bits is transmitted via enable gate 5443 from zero register 5442 and stored by input register 5446-0 onthe next clock signal X1.
Control memory 5445 is a sequential access memory rather than a random access memory and is in effect a circulating, multiple-bit shift register wherein the information to be transmitted to input register 5446-0 via control memory input path 5447is selected by select logic circuit 5496. In the present exemplary embodiment, each connection word (or null word) received on control memory input path 5447 is stored in control memory 5445 for one frame. Since the transmission of source anddestination addresses from control memory 5445 to control the transfer of digital words from TSI input circuit 5200 to TSI output circuit 5600 occurs substantially simultaneously with the transmission of connection words (or null words) for storage ininput register 5446-0, digital words are transferred at a relatively higher rate in time-slot interchanger 5100-0 than in a time-slot interchanger utilizing a random access control memory arrangement of comparable technology but having alternate read andwrite access. Advantageously, control memory 5445 can disconnect 32 active connections and establish 32 new connections with any given frame.
DETAILED DESCRIPTION
Certain of the elements of the fast circuit switching system of FIG. 1 are now described in more detail.
Communications Module 2000-0
Communications module 2000-0 (FIG. 3) comprises a user buffer 2003 for storing data for communication with user device 1000-0, a processor 2004 and a memory 2002 interconnected by a bus 2001. Information in memory 2002 is conveyed tomultiplexer/demultiplexer 3000-0 via a direct memory access device 2005 and a DMA transmit control circuit 2006. Information from multiplexer/demultiplexer 3000-0 is conveyed to memory 2002 via a DMA receive control circuit 2007 and direct memory accessdevice 2005.
As an example consider that processor 2004 determines that a given block of data, e.g., 100 eight-bit bytes, received from user device 1000-0 via user buffer 2003 and store in memory 2002 is to be transmitted to user device 1000-248. Processor2004 transmits a START command via bus 2001 to DMA transmit control circuit 2006, which command indicates that the data is to be transmitted to destination channel 0 of link 3002-31 for communication via communications module 2000-248 to user device1000-248. Processor 2004 also notifies DMA transmit control circuit 2006 of the size of the data block. Circuit 2006 has four operating states as shown in the state diagram of FIG. 21. Assuming that circuit 2006 is in the READY state, i.e., it is notinvolved in transmitting other data, it changes to the SETUP state in response to the START command and transmits a given circuit setup request word defining channel 0 of link 3002-31 as the requested destination. The given circuit setup request word istransmitted by multiplexer/demultiplexer 3000-0 in source channel 0 of link 3001-0 to port controller 4000-0. Until DMA receive control circuit 2007 receives a circuit set response from port controller 4000-0 in destination channel 0 of link 3002-0 andinforms circuit 2006 thereof via a path 2008, circuit 2006 remains in the SETUP state. In other words, when DMA receive control circuit 2007 receives either no response or destination busy responses in destination channel 0 of link 3002-0. DMA transmitcontrol circuit 2007 remains in the SETUP state and repetitively transmits the given circuit setup request word in source channel 0 of link 3001-0. Upon being informed by circuit 2007 via path 2008 of the receipt of a circuit set response, circuit 2006changes to the TRANSFER state and transmits a signal via a path 2009 to direct memory access device 2005 which, in response to the signal, begins reading the data block in memory 2002 and transmitting that data via multiplexer/demultiplexer 3000-0 insource channel 0 of link 3001-0 at the rate of two bytes, i.e., 16 bits, per frame.
Recall that processor 2004 notified circuit 2006 of the length of the data block in memory 2002. When the entire block has been transmitted, circuit 2006 changes to the DISCONNECT state and transmits a circuit disconnect request word againdefining destination channel 0 of link 3002-31. The circuit disconnect request word is transmitted in source channel 0 of link 3001-0 to port controller 4000-0. When circuit 2007 receives a circuit disconnected response in destination channel 0 of link3002-0 and notifies circuit 2006 via path 2008, circuit 2006 returns to the READY state where it is available to transmit another data block.
DMA transmit control circuit 2006 is also used to inform port controller 4000-0 that communications module 2000-0 is available to receive data on destination channel 0 of link 3002-0. When processor 2004 determines that circuit 2007 and directmemory access device 2005 are prepared to transfer incoming data from link 3002-0 to memory 2002 for storage therein, processor 2004 so notifies circuit 2006 which transmits logic one receiver status bits (bit 0, FIG. 17) in source channel 0 of link3001-0 thereby information port controller 4000-0 that communications module 2000-0 is ready to receive data from destination channel 0 of link 3002-0. In response, port controller 4000-0 modifies status word 0 defining the availability ofcommunications module 2000-0 to receive data, the next time that status word 0 is cycled to port controller 4000-0.
DMA receive control circuit 2007, in addition to detecting circuit set, circuit disconnected and destination busy responses in destination channel 0 of link 3002-0 and notifying circuit 2006 thereof via path 2008 as described above, detects theSTART RECEIVING DATA and STOP RECEIVING DATA commands (FIG. 18) with regard to the transmission of data to communications module 2000-0 from another communications module of the system. When circuit 2007 detects a START RECEIVING DATA command fromdestination channel 0 of link 3002-0, circuit 2007 notifies direct memory access device 2005 via a path 2010. Circuit 2007 then begins transferring the 16-bit data field of each data word subsequently received in that destination channel, to directmemory access device 2005 for storage in memory 2002. When circuit 2007 subsequently detects a STOP RECEIVING DATA command in that destination channel, circuit 2007 stops transferring data for storage in memory 2002 and notifies processor 2004 anddirect memory access device 2005 that a complete data block has been received and stored in memory 2002. In response, processor 2004 initiates the transfer of the data block to user buffer 2003 for communication to user device 1000-0.
Port Controller 4000-0
Port controller 4000-0, shown in FIG. 4 through 9, arranged in accordance with FIG. 23, includes a port input circuit 4100, a port control circuit 4300 and a port output circuit 4500. The functions of port controller 4000-0 are to detect circuitsetup request and circuit disconnect request words received in source channels of link 3001-0 and to transmit received circuit setup request words and subsequent data words to network 5000 input port IP0 only after the status word defining theavailability of the requested destination channel and the availability of the destination communications module to receive data, has been cycled to port controller 4000-0 and that status word indicates both that the requested destination channel isavailable and that the destination communications module is available to receive data. Port controller 4000-0 appropriately modifies the status word before transmitting it on to port controller 4000-1. Port controller 4000-0 transmits circuit set ordestination busy responses in destination channels on link 3002-0 in response to circuit setup request words received in source channels on link 3001-0. Port controller 4000-0 transmits circuit disconnected responses in destination channels on link3002-0 and appropriately modifies status words in response to circuit disconnect request words received in source channels on link 3001-0. Port controller 4000-0 transmits received circuit disconnect request words on to network 5000 input port IP0. Port controller 4000-0 modifies status words in response to receiver available signals received in source channels on link 3001-0 indicating that the communications modules associated with those source channels are available to receive data. Finally,port controller 4000-0 responds to circuit setup request and circuit disconnect request words received from network 5000 output port OP0 by transmitting START RECEIVING DATA and STOP RECEIVING DATA commands, respectively, to multiplexer/demultiplexer3000-0 in destination channels on link 3002-0.
Port controller 4000-0 operates in frames of eight channels or time slots each. Six clock signals C0 through C5 (FIG. 19), which are used within port controller 4000-0 for timing purposes, all are of a frequency of one pulse per time slot. During each time slot, a 19-bit digital word (FIG. 17) is serially received on link 3001-0 by serial-parallel register 4101. That digital word is stored in a 19-bit register 4103 on the clock signal C0. Clock signal C0 is also used to increment athree-bit time-slot counter 4115 and a modulo-9 counter 4129. Time-slot counter 4115 repetitively generates the three-bit time-slot designations 000 through 111 representing the channels 0 through 7 of link 3001-0 from which the digital words stored inregister 4103 are received. Modulo-9 counter 4129 generates logic one signals on conductors 4130 and 4131 during every ninth time slot (FIG. 19). The logic one signal on conductor 4130 occurs one time slot after the logic one signal on conductor 4131. To simplify the implementation of both port controller 4000-0 and network 5000, at most one circuit setup request or circuit disconnect request word on link 3001-0 will be processed by port controller 4000-0 during each frame. Modulo-9 counter 4129 isused in a manner akin to that of a stroboscope such that when a circuit setup request or circuit disconnect request word received in channel 0 of a given frame is processed by port controller 4000-0, a circuit setup request or circuit disconnect requestword received in channel 1 of the next frame will be processed etc. Accordingly, a given communications module may transmit circuit setup request or circuit disconnect request words in at most eight consecutive frames before one such word is processed byport controller 4000-0.
As an example, assume that a given circuit setup request word defining destination channel 0 of link 3002-31 is received in source channel 0 of link 3001-0 during a frame when modulo-9 counter 4129 transmits a logic one signal on conductor 4130during time slot 0. A decoder 4105, which receives bits 1 and 2 of each digital word stored in register 4103, determines that the word presently stored in register 4103 is a circuit setup request word and transmits a logic one signal on a conductor 4106to an AND gate 4111. The logic one signal generated by modulo-9 counter 4129 on conductor 4130 is transmitted to an AND gate 4113, which receives at its other input terminal the clock signal C1. On clock signal C1, AND gate 4113 transmits a logic onesignal to AND gate 4111, which transmits a logic one signal to an 18-bit register 4109 and a three-bit register 4117 since it is receiving the logic one signal on conductor 4106 from decoder 4105 on its other input terminal. In response to the logic onesignal from AND gate 4111, register 4109 stores bits 1 through 18 of the given circuit setup request word present in register 4103 and register 4117 stores the time-slot designation 000 representing time slot 0 being generated by time-slot counter 4115. The words stored in registers 4109 and 4117 will remain there for nine time slots until modulo-9 counter 4129 again generates a logic one signal on conductor 4130. The logic one signal on conductor 4130 is transmitted to an AND gate 4151, which receivesthe clock signal C0 at its other input terminal. On the clock signal C0 nine time slots later, AND gate 4151 transmits a logic one signal to clear registers 4109 and 4117.
The words stored in registers 4109 and 4117 on the clock signal C1 are conveyed to port control circuit 4300. As will be described further herein, during the next seven time slots, each of the 32 status words 0 through 31 defining theavailability of destination channels and the availability of destination communications modules to receive data, is cycled to port controller 4000-0 at least once. When status word 31 associated with the destination communication module 2000-248 iscycled to port controller 4000-0, either a flip-flop 4371-S or a flip-flop 4372-B is set. Flip-flop 4371-S is set if status word 31 indicates both that destination channel 0 of link 3002-31 is available and that communications module 2000-248 isavailable to receive data. Otherwise, flip-flop 4372-B is set. The output signal generated by flip-flop 4371-S is transmitted to an AND gate 4381-S. The other input terminal of AND gate 4381-S is connected to an AND gate 4375. AND gate 4375 receivesat its two input terminals the clock signal C3 and the logic signal transmitted on conductor 4131 by modulo-9 counter 4129. Accordingly, if flip-flop 4371-S is set indicating that the requested circuit is to be established, on the clock signal C3 of theeighth time slot following the storage of the given circuit setup request word in register 4109, AND gate 4381-S transmits a logic one signal via an OR gate 4385 to a data selector 4119 and an address selector 4123, and via an additional OR gate 4125 toa WRITE input terminal of an 8.times.18 (8 locations of 18 bits each) random access memory 4127. Data selector 4119 and address selector 4123 as well as other data selectors and address selectors described herein operate as follows. When a logic onesignal is transmitted to the upper input terminal on the left-hand side of data selector 4119, the data present at the left input terminal on the upper side of data selector 4119 is transmitted to the DATA IN terminal of memory 4127. When a logic onesignal is transmitted to the lower input terminal on the left-hand side of data selector 4119, the data present at the right input terminal on the upper side of data selector 4119 is transmitted to the DATA IN terminal of memory 4127. Similarly, when alogic one signal is transmitted to the upper input terminal on the left-hand side of address selector 4123, the address present at the left input terminal on the upper side of address selector 4123 is transmitted to the ADDRESS terminal of memory 4127. When a logic one signal is transmitted to the lower input terminal on the left-hand side of address selector 4123, the address present at the right input terminal on the upper side of address selector 4123 is transmitted to the ADDRESS terminal of memory4127. Accordingly, when AND gate 4381-S transmits the logic one signal indicating that the requested circuit is to be established, the given circuit setup request word present in register 4109 is stored in memory 4127 at location 000 as defined by thetime-slot designation stored in register 4117.
An 8.times.1 random access, status memory 4303 included in port control circuit 4300 stores a bit in each of its eight locations indicating whether circuits have been established from the eight source channels on link 3001-0 via network 5000 todestination channels. A logic one bit indicates that a circuit has been established. When AND gate 4381-S generates the logic one signal in response to the given circuit setup request word, that logic one signal is also conveyed via OR gate 4385 to theWRITE terminal of status memory 4303 and to an input terminal of an address selector 4301. The logic one signal was also directly transmitted to the DATA IN terminal of status memory 4303. Accordingly, a logic one bit indicating that a circuit has beenestablished from source channel 0 of link 3001-0 is stored in status memory 4303 location 000 as defined by the time-slot designation stored in register 4117.
If a given circuit disconnect request word is stored in register 4103 during time slot 0 rather than the given circuit setup request word, decoder 4105 again transmits a logic one signal on conductor 4106 and the given circuit disconnect requestword and the time-slot designation 000 are stored in registers 4109 and 4117. When status word 31 associated with communications module 2000-248 is cycled to port controller 4000-0, a flip-flop 4373-D is set and an AND gate 4383-D transmits a logic onesignal via OR gate 4385 to data selector 4119 and address selector 4123 and via OR gate 4125 to the WRITE terminal of memory 4127. Accordingly, the given circuit disconnect request word is stored in memory 4127 location 000. Further, the logic onesignal generated by AND gate 4383-D is transmitted via OR gate 4385 to address selector 4301 and to the WRITE terminal of status memory 4303. However, in this case, flip-flop 4371-S is not set and AND gate 4381-S transmits a logic zero signal to theDATA IN terminal of status memory 4303. Therefore, a logic zero bit is stored in status memory 4303 location 000 indicating that a circuit from source channel 0 of link 3001-0 is not presently established.
On the clock signal C1 during each time slot, the bit stored in the status memory 4303 location associated with that time slot as defined by the time-slot designation transmitted by time-slot counter 4115 is read and stored in a flip-flop 4305. When during given time slot, e.g., time slot 3, a logic one bit, stored in flip-flop 4305 indicating that a circuit is presently established from source channel 3 of link 3001-0, is transmitted to an AND gate 4108 and detector 4105 also transmits a logicone signal on conductor 4107 indicating that the word presently stored in register 4103 is a data word rather than a circuit setup request or circuit disconnect request word, AND gate 4108 transmits, on the clock signal C2, a logic one signal to an inputterminal of data selector 4119, via an OR gate 4121 to an input terminal of address selector 4123 and via OR gate 4125 to the WRITE terminal of memory 4127. In response, the data word present in register 4103 is written into memory 4127 location 011 asdefined by the time-slot designation 011 generated by time-slot counter 4115 time slot 3.
On the clock signal C4 during each time slot, the 18-bit word stored in the memory 4127 location defined by time-slot counter 4115 is read and stored on the clock signal C5 in a parallel-serial register 4128. The stored 18-bit word is thentransmitted serially to network 5000 input port IP0. Memory 4127 is a destructive read memory. Therefore after each memory 4127 location is read, 18 logic zero bits are stored in that memory 4127 location. Further, on the clock signals C5 of each timeslot, flip-flop 4305 is reset. Status memory 4303 is not a destructive read memory. Therefore, once a logic one bit has been written in status memory 4303 indicating that a circuit has been established, the logic one bit remains therein until beingoverwritten by a logic zero bit indicating that the circuit has been disconnected.
Recall that a given circuit setup request or circuit disconnect request word and its associated time-slot designation, once stored in registers 4109 and 4117 respectively, remain therein for nine time slots. Now assume that a given circuit setuprequest word defining destination channel 0 of link 3002-31 is received in source channel 0 on link 2001-0 and that the given circuit setup request word and the source channel time-slot designation 000 are stored in registers 4109 and 4117. Port controlcircuit 4300 of port controller 4000-0 includes a 17-bit status word receive register 4341 for storing status words received from port controller 4000-31 and a 17-bit status word transmit register 4342 for storing modified status words to be transmittedon to port controller 4000-1. The status word present in the status word transmit register 4342 of port controller 4000-31 is stored in the status word receive register 4341 of port controller 4000-0 during each occurrence of a clock signal K0. Thestatus word present in the status word receive register 4341 of port controller 4000-0 is modified and stored in the status word transmit register 4342 of port controller 4000-0 during each occurrence of a clock signal K1. In the present embodiment, theclock signals K0 and K1 are both of a frequency of five pulses per link 3001-0 time slot (FIG. 19). Accordingly each of the 32 status words is cycled to port controller 4000-0 once in a period less than seven time slots.
The mechanism for cycling status words can be equivalently described as follows. Assume that j, k and l are defined as integers with k being the integer resulting from the modulo-32 addition of one to the integer j and with 1 being the integerresulting from the modulo-32 addition of one to the integer k. For any integer j from 0 through 31, the status word transmit register 4342 of the kth port controller (4000-k) transmits each status word stored by the status word receive register 4341 ofthe kth port controller (4000-k) to the lth port controller (4000-l). Further, the status word receive register 4341 of the kth port controller (4000-k) receives for storage each status word transmitted by the status word transmit register 4342 of thejth port controller (4000-j).
A logic one in a bit 16 of a given status word defines that status word as status word 0, i.e., the status word associated with link 3002-0 and communications modules 2000-0 through 2000-7. Bits 0 through 7 of that status word define theavailability of destination channels 0 through 7 respectively of link 3002-0. Bits 8 through 15 of that status word define the availability of communications modules 2000-0 through 2000-7 respectively to receive data. In both cases a logic one bitindicates availability. Bits 0 through 15 of the other 31 status words similarly define the availability of the associated destination channels and the availability of the associated communications modules to receive data. Bit 16 is a logic zero bit inthe other 31 status words. A loop counter 4329 which is incremented on each clock signal K0, generates five-bit status word designations from 00000 to 11111. Loop counter 4329 is reset by the logic one bit in bit 16 of status word 0. Accordingly, whenstatus word 0 is present in status word receive register 4341, loop counter 4329 generates the status word designation 00000, when status word 1 is present in register 4341, loop counter 4329 generates the status word designation 00001, etc. Finally,when status word 31 is present in register 4341, loop counter 4329 generates the status word designation 11111. In the present example, bits 11-15 of the given circuit setup request word are the bits 11111 defining link 3002-31 as the requesteddestination link. Decoder 4311, which receives bits 1 and 2 of the digital word stored in register 4109, determines that the stored digital word is a circuit setup request word and transmits a logic one signal via a conductor 4310 and an OR gate 4317 toan AND gate 4319. During the same time slot that the given circuit setup request word was stored in register 4109 on the clock signal C1, the logic one signal generated by modulo-9 counter 4129 is transmitted on conductor 4130 to AND gate 4319. ANDgate 4319 receives at a third input terminal the clock signal C2. Accordingly on the clock signal C2 of that same time slot, AND gate 4319 transmits a logic one signal to set a flip-flop 4321 to enable a comparator 4323. Comparator 4323 compares thestatus word designations generated by loop counter 4329 with the bits 11-15 of the given circuit setup request word stored in register 4109. When status word 31 is cycled to status word receive register 4341 as indicated by loop counter 4329 generatingthe designation 11111, comparator 4323 generates a logic one signal indicating that the status word relevant to the circuit setup request word being processed is now present in status word receive register 4341. The logic one signal generated bycomparator 4323 is transmitted to three AND gates 4351, 4353 and 4355 of a logic circuit 4350-0 and to similar AND gates included in seven other logic circuits 4350-1 through 4350-7. Bits 16 through 18 of the given circuit setup request word stored inregister 4109 are transmitted to a 1-out-of-8 selector 4331 which transmits a logic one signal of the one of eight conductors SEL0 through SEL7 defined by those bits. In the present example, since the requested destination channel is channel 0, a logicone signal is transmitted on conductor SEL0 to the three AND gates 4351, 4353 and 4355 of the logic circuit 4350-0 only. During the same time slot that the given circuit setup request word was stored in register 4109, i.e., time slot 0, the bit storedin status memory 4303 location 000 was read and stored in a flip-flop 4309. Unlike flip-flop 4305, flip-flop 4309 is not reset every time slot. Assuming that a circuit from source channel 0 of link 3001-0 had not been previously established, flip-flop4309 transmits a logic one signal from its "O" output terminal to an AND gate 4313-CR. The logic one signal generated by decoder 4311 on conductor 4310 indicating that the digital word stored in register 4109 is a circuit setup request word istransmitted to the other input terminal of AND gate 4313-CR. In response, AND gate 4313-CR transmits a logic one signal to AND gates 4351 and 4353 in logic circuit 4350-0 and to similar AND gate 4313-CR generates a logic one signal only when the digitalword stored in register 4109 is a circuit setup request word and when no circuit from the source channel transmitting that circuit setup request word has presently been established.
If bits 0 through 8 of status word 31, which is presently stored in status word receive register 4341, are both logic ones indicating both that destination channel 0 of link 3002-31 is available and that communications module 2000-248 isavailable to receive data, the AND gate 4351 of logic circuit 4350-0 transmits a logic one signal via an eight-input OR gate 4361-S to set flip-flop 4371-S. Recall that setting flip-flop 4371-S results in the given circuit setup request word being storedin memory 4127 location 000 and a logic one bit, indicating that a circuit from source channel 0 of link 3001-0 has been established, being stored in status memory 4303 location 000. OR gate 4361-S receives at its eight input terminals the logic signalstransmitted by AND gate 4351 of logic circuit 4350-0 by similar AND gates in the other seven logic circuits 4350-1 through 4350-7. If either bit 0 or bit 8 of status word 31 is a logic zero indicating that either destination channel 0 of link 3002-31 isunavailable or that communications module 2000-248 is not available to receive data, a NAND gate 4352 transmits a logic one signal to the AND gate 4353 of logic circuit 4350-0 and that AND gate 4353 transmits a logic one signal via an eight-input OR gate4362-B to set flip-flop 4372-B. As will be discussed herein, setting flip-flop 4372-B results in a destination busy response being transmitted in destination channel 0 of link 3002-0 to communications module 2000-0. OR gate 4362-B receives at its eightinput terminals the logic signals transmitted by AND gate 4353 of logic circuit 4350-0 and by similar AND gates in the other seven logic circuits 4350-1 through 4350-7.
Since the digital word stored in register 4109 is a circuit setup request word rather than a circuit disconnect request word, decoder 4311 transmits a logic zero signal on a conductor 4312 to an AND gate 4315-DR and accordingly AND gate 4315-DRtransmits a logic zero signal to the AND gate 4355 of logic circuit 4350-0 and to similar AND gates in the logic circuits 4350-1 through 4350-7. In response, AND gate 4355 transmits a logic zero signal to an OR gate 4356. A comparator 4327 compares thestatus word designations generated by loop counter 4329 with the contents of a five-bit ID register that defines the one of the 32 port controllers 4000-0 through 4000-31 in which it is included. In port controller 4000-0 presently being described, IDregister contains the bits 00000. Accordingly, when status word 31 is present in register 4341 is indicated by loop counter 4329 generating the status word designation 11111, comparator 4327 transmits a logic zero signal to an AND gate 4357 in logiccircuit 4350-0 and to similar AND gates in logic circuits 4350-1 through 4350-7. In response, AND gate 4357 transmits a logic zero signal to an OR gate 4350. When bits 0 and 8 in status word receive register 4341 are both logic ones and AND gate 4351therefore transmits a logic one signal to inverting input terminals of AND gates 4354 and 4358, AND gates 4354 and 4358 transmit logic zero signals to OR gates 4356 and 4359 respectively. Since both OR gates 4356 and 4359 are also receiving logic zerosignals at their other input terminals, they both transmit logic zero signals for storage in bits 0 and 8 os status word transmit register 4342 on the clock signal K1. Accordingly, whenever AND gate 4351 generates a logic one indicating that therequested connection is being established, bits 0 and 8 of the status word in register 4341 are forced to logic zeroes when stored in register 4342. In the case that bits 0 and 8 of status word 31 present in register 4341 are not both logic ones. ANDgate 4351 transmits a logic zero signal to the inverting input terminals of AND gate 4353 and 4358 and accordingly the bits 0 and 8 of register 4341 are conveyed without modification via AND gate 4354 and OR gate 4356 and via AND gate 4358 and OR gate4359 for storage in bits 0 and 8 of register 4342 on the clock signal K1.
When the digital word received in source channel 0 of link 3001-0 and stored in register 4109 is a circuit disconnect request word defining destination channel 0 of link 3002-31, decoder 4311 transmits a logic one signal of conductor 4312 whichis conveyed via OR gate 4317 to AND gate 4319, which again results in flip-flop 4321 being set and comparator 4323 being enabled. In this case assume that a logic one bit indicating that a circuit from source channel 0 of link 3001-0 is presentlyestablished, is present in status memory 4303 location 000. When the bit in that location is read and stored in flip-flop 4309, flip-flop 4309 transmits a logic one signal from its "1" output terminal to AND gate 4315-DR. AND gate 4315-DR receives atits other input terminal the logic one signal transmitted by decoder 4311 on conductor 4312. In response, AND gate 4315-DR transmits a logic one signal to the AND gate 4355 in logic circuit 4350-0 and to similar AND gates in the other logic circuits4350-1 through 4350-7. In logic circuit 4350-0 only, AND gate 4355 transmits a logic one signal via an eight-input OR gate 4363-D to set a flip-flop 4373-D. Recall that setting flip-flop 4373-D results in the circuit disconnect request word present inregister 4109 being written into memory 4127 location 000 and a logic zero bit being stored in status memory 4303 location 000 indicating that the circuit from source channel 0 of link 3001-0 has been disconnected. OR gate 4363-D receives at its eightinput terminals the logic signals transmitted by AND gate 4355 of logic circuit 4350-0 and by similar AND gates in logic circuits 4350-1 through 4350-7. A logic one signal being generated by any one of the OR gates 4361-S, 4362-B and 4363-D effects atransmission of a logic one signal by an OR gate 4365 to reset flip-flop 4321 and thereby disable comparator 4323.
When AND gate 4355 transmits a logic one signal indicating that the requested circuit disconnection is to be effected, that logic one signal is conveyed via OR gate 4356 for storage in bit 0 of register 4342 on the clock signal K1. The logic onein bit 0 indicates that destination channel 0 of link 3002-0 is again available.
Recall that a given communications module, e.g., 2000-0 notifies port controller 4000-0 that it is again available to receive data by transmitting logic one receiver status bits (bit 0, FIG. 17) in source channel 0 of link 3001-0. Bit 0 of eachdigital word received serially on linek 3001-0 by serial-parallel register 4101 and stored in register 4103 is transmitted to eight AND gates 4335-0 through 4335-7. The time-slot designations generated by time-slot counter 4115 are transmitted to a1-out-of-8 selector which transmits a logic one signal on the one of eight conductors S0 through S7 thus defined. When a logic one receiver status bit is received in time slot 0 on link 3001-1 and that logic one bit and the logic one signal generated byselector 4333 on conductor S0 are both conveyed to AND gate 4335-0, AND gate 4335-0 transmits a logic one signal to set a flip-flop 4337-0. Similarly, when logic one receiver status bits are received in time slots 1 through 7 on link 3001-0, flip-flops4337-1 through 4337-7 are set. A given flip-flop, e.g., 4337-0, is not reset until eight time slots later when selector 4333 transmits a logic one signal on conductor S7 to reset flip-flop 4337-0. Similarly, flip-flop 4337-7 is reset when selector 4333transmits a logic one signal on conductor S6. Accordingly, the signals stored by the flip-flops 4337-0 through 4337-7 define the availability of the communications modules 2000-0 through 2000-7 as indicated by the most recently received receiver statusbits.
Recall that ID register 4325 defines the one of 32 port controllers 4000-0 through 4000-31 in which it is included. In port controller 4000-0, comparator 4327 generates a logic one signal only when status word 0 is present in status word receiveregister 4341. The logic one signal is transmitted to AND gate 4357 in logic circuit 4350-0 and to similar AND gates in logic circuits 4350-1 through 4350-7. The bit stored in flip-flop 4337-0 is transmitted via a conductor A0 to AND gate 4357 in logiccircuit 4350-0. The bits stored in the other flip-flops 4337-1 through 4337-7 are conveyed by conductors A1 through A7 to similar AND gates in logic circuits 4350-1 through 4350-7. Bit 0 of the status word present in status word receive register 4341is also transmitted to AND gate 4357 in logic circuit 4350-0. When bit 0 of status word 0 present in register 4341 is a logic one indicating that destination channel 0 of link 3002-0 is available and the bit stored in flip-flop 4337-0 indicates thatcommunications module 2000-0 is available to receive data, AND gate 4357 transmits a logic one signal via OR gate 4359 for storage in bit 8 of status word transmit register 4342 on the clock signal K1. Accordingly status word 0 is modified by storingthe logic one in bit 8 to indicate that communications module 2000-0 is available to receive data.
Recall that for each circuit setup request or circuit disconnect request word stored in register 4109, one of the flip-flops 4371-S, 4373-D and 4372-B is set in response some time during the next seven time slots. Modulo-9 counter 4129 transmitsa logic one signal on conductor 4131 to AND gates 4375 and 4371 during the eighth subsequent time slot. AND gate 4375 receives at its other input terminal the clock signal C3. Accordingly on the clock signal C3 of the eighth subsequent time slot, ANDgate 4375 transmits a logic one signal to the three AND gates 4381-S, 4383-D and 4382-B which receive at their other input terminals the signals stored at the "1" output terminals of flip-flops 4371-S, 4373-D and 4372-B. Accordingly, for any one of theflip-flops 4371-S, 4373-D and 4372-B that has been set, the associated one of the AND gates 4381-S, 4383-D and 4382-B transmits a logic one signal to an encodder 4513 and an OR gate 4515 in port output circuit 4500. AND gate 4371 receives at its otherinput terminal the clock signal C4. On the clock signal C4 of the eighth subsequent time slot. AND gate 4371 transmits a logic one signal to reset flip-flop 4309 and flip-flops 4371-S. 4373-D and 4372-B.
When one of the AND gates 4381-S, 4383-D and 4382-B transmits a logic one signal to OR gate 4515, OR gate 4515 transmits a logic one signal to the WRITE terminal of an 8.times.2 random access memory 4509 and to an address selector 4517. Thememory 4509 location addressed is defined by the time-slot designation stored in register 4117. Consistent with the previous example where the circuit setup request word or circuit disconnect request word stored in register 4109 was received in sourcechannel 0 of link 3001-0, the time-slot designation 000 is stored in register 4117 and memory 4509 location 000 is addressed. When AND gate 4381-S transmits a logic one signal to encoder 4513, encoder 4513 transmits the circuit set response bits 01(FIG. 18) for storage in memory 4509 location 000. When AND gate 4383-D transmits a logic one signal to encoder 4513, encoder 4513 transmits the circuit disconnected response bits 10 (FIG. 18) for storage in memory 4509 location 000. And when AND gate4382-B transmits a logic one signal to encoder 4513, encoder 4513 transmits the destination busy response bits 11 (FIG. 18) for storage in memory 4509 locations 000. Memory 4509 is thus written with response bits on the clock signal C3 of the eighthtime slot after a given circuit setup request or circuit disconnect request word is stored in register 4109.
Eighteen-bit digital words are received serially from network 5000 output port OP0 by a serial-parallel register 4501. When a given digital word received by serial-parallel register 4501 is a circuit setup request word that has been conveyedthrough network 5000, an encoder 4503 transmits the bits representing a START RECEIVING DATA command (FIG. 18) to a register 4505. If the digital word received by register 4501 is a circuit disconnect request word, encoder 4503 transmits the bitsrepresenting a STOP RECEIVING DATA command (FIG. 18) to register 4505. Finally, if the digital word received by register 4501 is a data word, encoder transmits a logic one in bit 2 indicating data rather than command together witih the 16-bit data fieldto register 4505. The information transmitted by encoder 4503 is stored in register 4505 on the clock signal C3. A time-slot counter 4511, which is incremented on the clock signal C2, repetitively generates the time-slot designations 000 through 111representing the destination channels on link 3002-0. The contents of register 4505 are stored in the location of an 8.times.17 random access memory 4507 defined by time-slot counter 4511 on the clock signal C4 of each time slot. The contents of memory4509 and memory 4507 locations defined by time-slot counter 4511 are read therefrom on the clock signal C1 of each time slot and stored as bits 0 through 18 in a parallel-serial register 4519 on the clock signal C2. Each 19-bit word thus stored issubsequently serially transmitted on link 3002-0 to multiplexer/demultiplexer 3000-0.
Network 5000
Network 5000 comprises eight time-slot interchangers 5100-0 through 5100-7 (FIG. 10). Each time-slot interchanger receives information from all 32 network 5000 input ports IP0 through IP31 but transmits information to only four of the 32 network5000 output ports OP0 through OP31. Accordingly, a given time-slot interchanger, e.g., 5100-0, receives 256 digital words during a given frame (eight digital words from each of the port controllers 4000-0 through 4000-31) but is required to transmitonly 32 digital words (eight digital words to each of the port controllers 4000-0 through 4000-3). Network 5000 further includes eight, 3-bit ID registers 5900-0 through 5900-7 each associated with one of the time-slot interchangers 5100-0 through5100-7. ID register 5900-0 contains the bits 000 defining time-slot interchanger 5100-0 as the time-slot interchanger that transmits information to output port OP0 through OP3, ID register 5900-1 contains the bit 001 defining time-slot interchanger5100-1 as the time-slot interchanger that transmits information to output ports OP4 through OP7, etc.
FIG. 20 is a timing diagram showing various clock signals required within network 5000. Since the time-slot interchangers 5100-0 through 5100-7 included pipelined memory arrangements, a number of clock signals are used for frame definition. Clock signals S0, S1, S0' and S1' are used to define alternate frames. Clock signals T0, T1, and T2 define first, second and third frames. Digital words are received at a given input port at a rate of eight digital words per frame corresponding to theeight source channels on each of the links 3001-0 through 3001-31. However, within a given time-slot interchanger, 32 digital word transfers are completed each frame. Accordingly, each frame is herein defined as being divided into eight link time slotsand further divided into 32 TSI time slots. Each of the clock signals Y0 and Y1 are of a frequency of one pulse per link time slot. Each of the clock signals X0, X1 and X2 are of a frequency of one pulse per TSI time slot, or equivalently, four pulsesper link time slot. The transitions of the clock signals S0' and S1' are delayed by one TSI time slot from the transitions of the clock signals S0 and S1 respectively, for a reason to be described later herein. Finally, clock signals FP0 and FP1 areshort duration pulses which occur on the positive transitions of the clock signals S0 and S1 respectively.
Time-slot Interchanger 5100-0
A detailed diagram of time-slot interchanger 5100-0 is shown in FIGS. 11 through 16, arranged in accordance with FIG 24. The digital words transmitted by port controllers 4000-0 through 4000-31 are received by TSI input circuit 5200. Thedigital words transmitted to port controllers 4000-0 through 4000-3 are transmitted by TSI ouptut circuit 5600. Words are transferred from TSI input circuit 5200 via register 5290 to TSI output circuit 5600 in accordance with source and destinationaddresses and read and write signals transmitted by TSI control circuit 5400.
TSI input circuit 5200 includes 96, 8.times.18 random access memories 5206-0 through 5206-31, 5216-0 through 5216-31 and 5226-0 through 5226-31, with only the three memories 5206-0, 5216-0 and 5226-0 associated with input port IP0 being shown inFIG. 11. Digital words are written into memory 5206-0 during the frame defined by the clock signal T0 but are read therefrom two frames later during the frame defined by the clock signal T2. Digital words are written into memory 5216-0 during the framedefined by the clock signal T1 but are read therefrom two frames later during the frame defined by the clock signal T0. Digital words are written into memory 5226-0 during the frame defined by the clock signal T2 but are read therefrom two frames laterduring the frame defined by the clock signal T1. Eighteen-bit digital words are received serially from the input port IP0 through IP31 by 32 serial-parallel registers 5340-0 through 5340-31 and are stored on the clock signal Y0 in 32, eighteen-bitregisters 5241-0 through 5241-31. Only serial-parallel registers 5240-0 and 5240-31 and registers 5241-0 and 5241-31 are shown in FIG. 11. Although each of the TSI input circuit 5200 memories, e.g., 5206-0, has only eight locations, the locations havenine-bit addresses. The first bit of the address is always a logic one bit. The next five bits define the one of the 32 input ports IP0 through IP31 with which that memory is associated. An ID register 5202-0 contains the six bits 100000 which are thefirst six address bits for the memories 5206-0, 5216-0 and 5226-0 associated with input port IP0. Thirty-one other ID registers 5202-1 through 5202-31 (not shown) contain the first six address bits for the other TSI inpur circuit 5200 memories. Atime-slot counter 5201, which is incremented on the clock signal Y0, repetitively generates the link time-slot designations 000 through 111 representing the channels 0 through 7 at the input ports IP0 through IP31. The link time-slot designationsgenerated by time-slot counter 5201 are used as the final three address bits for writing the TSI input circuit 5200 memories. Although the locations of the three memories associated with a given input port, e.g., memories 5206-0, 5216-0 and 5226-0, havethe same addresses, only one of the three memories is written during any given frame. For example, during the frame defined by the clock signal T0, each 18-bit digital word stored in register 5241-0 is written on the clock signal Y1 into the memory5206-0 location defined by ID register 5202-2 and time-slot counter 5201. Similarly only one of the three memories 5206-0, 5216-0 and 5226-0 is read during each frame at a location defined by the source address transmitted from TSI control circuit 5400. The address selectors 5205-0, 5215-0 and 5225-0 and the AND gates 5207-0, 5208-0, 5217-0, 5218-0, 5227-0 and 5228-0 are used in conjunction with the clock signals T0, T1. and T2 are shown in FIG. 11 to achieve the above-described pipelined operation ofmemories 5206-0, 5216-0 and 5226-0.
The TSI input circuit 5200 memories comprise a triple-buffered memory arrangement. Two-hundred-fifty-six digital words are stored in TSI input circuit 5200 during one frame, during the next frame any of those digital words that are circuit setuprequest words or circuit disconnect request words are used to appropriately change the contents of cotnrol memory 5445 as will be described and then during a third frame up to 32 of those digital words are read from TSI input circuit 5200 and aretransmitted via a register 5290 to be written in TSI output circuit 5600.
The contents of the registers 5241-0 through 5241-31 are also made available to new connection word storage arrangement 5410 and disconnection word storage arrangement 5460. Only the portion of new connection word storage arrangement 5410 usedfor storing new connection words in response to circuit step request words stored in register 5241-0 from input port IP0 is explicitly shown in FIG. 15. Recall that port controller 4000-0 transmits at most on circuit setup request word in each frame tonetwork 5000 input port IP0. If one of the eight digital words stored in register 5241-0 during a given frame is a circuit setup request word defining a destination channel of one the links 3002-0 through 3002-3, 15 bits of that circuit setup requestword are stored as a new connection word in one the two 15-bit registers 5401-0 and 5402-0. A selector 5410-0 associated with input port IP0 monitors the digital words stored in register 5241-0. (Thirty-one selectors 5410-1 through 5410-31substantially identical to selector 5410-0 are associated with input ports IP1 through IP31 but are not shown in FIG. 15.) Selector 5410-0 includes a comparator 5406-0 and a decoder 5405-0. Decoder 5405-0 receives bits 1 and 2 of each digital wordstored in register 5241-0 which define the digital word as an idle word, a data word, a circuit setup request word or a circuit disconnect request word. When decoder 5405-0 determines that the digital word is a circuit setup request word, decoder 5404-0transmits a logic one signal to and AND gate 5407-0. Comparator 5406-0 receives the bits stored in ID register 5900-0 (FIG. 10) and compares them with bits 11 through 13 of the digital word stored in register 5241-0. Recall that ID register 5900-0,being associated with time-slot interchanger 5100-0, contains the bits 000. When bits 11-13 of a given circuit setup request word stored in register 5241-0 are the bits 000 indicating that the requested destination link is one of the four links 3002-0through 3002-3 served by time-slot interchanger 5100-0, comparator 5406-0 transmits a logic one signal to the other input terminal of AND gate 5407-0. In response, AND gate 5407-0 transmits a logic one signal to two AND gates 5411-0 and 5412-0associated with registers 5401-0 and 5402-0 respectively. AND gate 5411-0 receives at its other two input terminals the clock signals S0' and Y1. AND gate 5412-0 receives at its other two input terminals the clock signals S1' and Y1. Accordingly,dependin | | | |
