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Electronic musical instruments |
| RE32838 |
Electronic musical instruments
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| Patent Drawings: | |
| Inventor: |
Suzuki |
| Date Issued: |
January 24, 1989 |
| Application: |
07/012,083 |
| Filed: |
February 6, 1987 |
| Inventors: |
Suzuki; Hideo (Kosai, JP)
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| Assignee: |
Nippon Gakki Seizo Kabushiki Kaisha (Hamamatsu, JP) |
| Primary Examiner: |
Witkowski; Stanley J. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Pfund; Charles E. |
| U.S. Class: |
84/628; 984/309; 984/341; 984/377 |
| Field Of Search: |
84/1.01; 84/1.03; 84/1.24; 84/1.25; 84/1.26 |
| International Class: |
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| U.S Patent Documents: |
3746773; 3886836; 3929053; 3979989; 3979996; 3982460; 4026180 |
| Foreign Patent Documents: |
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| Other References: |
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| Abstract: |
In an electronic musical instrument of digital processing type, key codes are stored in a memory channel by channel for respective tone productions. The stored key codes are utilized for determining pitches of respective tones to be produced. Upon depression of new keys, the formerly stored key codes are automatically added or subtracted channel by channel with the value for a certain note step toward the new key codes at a certain clock rate defining a glissando speed. Thus automatic glissando performances are easily realized. |
| Claim: |
What is claimed is:
1. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, said key code signals having values which onlyidentify depressed keys and which are not proportional to tone frequencies represented by said depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to said key code memory meansfor comparing a first key code received from said key code memory means with a second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to or subtracting from thecontent of said key code memory means a predetermined value defining a semitone step repetitively at a predetermined clock rate to change said first key code in said key code memory means by successive semitone steps one after another to the next keycode until said first key code in said key code memory means becomes equal to said second key code, and tone forming means connected to said key code memory means for forming a musical tone having a pitch determined by said key code in said key codememory means.
2. An electronic musical instrument according to claim 1 which further comprises a variable frequency oscillator for producing a signal that determines said clock rate.
3. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, said key code signals having values which only identify depressed keys and which are not proportional to tone frequenciesrepresented by said depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to said key code memory means for comparing a first key code received from said key code memory means witha second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to or subtracting from the content of said key code memory means a predetermined value defining a semitonestep repetitively at a predetermined clock rate to change said first key code in said key code memory means until said first key code becomes equal to said second key code, tone forming means connected to said key code memory means for forming a musicaltone having a pitch determined by said key code in said key code memory means, wherein said key coder means produces said key code signals on a time division basis, and said key code memory means comprises a plurality of memory stages for storing saidkey code signals on the time division basis.
4. An electronic musical instrument according to claim 3 wherein said key coder means comprises memory means for storing said key code signals at memory stages corresponding to time division channels.
5. An electronic musical instrument according to claim 4 wherein said key coder means further comprises first means for representing a time division channel to be secured, and second means responsive to the output of said first means fordetermining a stage of said memory means utilized to store said key code signal thereby storing key code signals at said stage and not yet secured stages.
6. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, said key code signals having values which only identify depressed keys and which are not proportional to tone frequenciesrepresented by said depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to said key code memory means for comparing a first key code received from said key code memory means witha second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to or subtracting from the content of said key code memory means a predetermined value defining a semitonestep repetitively at a predetermined clock rate to change said first key code in said key code memory means until said first key code becomes equal to said second key code, and tone forming means connected to said key code memory means for forming amusical tone having a pitch determined by said key code in said key code memory means, and wherein said tone forming means includes first means for producing a tone pitch voltage corresponding to the output of said key code memory means, a capacitor forstoring said voltage, and a voltage controlled type variable frequency oscillator for generating an oscillation having a frequency determined by the voltage stored in said capacitor.
7. An electronic musical instrument according to claim 6 which further comprises second means for varying the charging time constant of said capacitor.
8. An electronic musical instrument according to claim 7 which further comprises a variable frequency oscillator for producing a signal that determines the clock rate for said calculation means.
9. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to saidkey code memory means for comparing a first key code received from said key code memory means with a second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to orsubtracting from the content of said key code memory means a predetermined value defining a semitone step repetitively at a predetermined clock rate to change said first key code in said key code memory means until said first key code becomes equal tosaid second key code, tone forming means connected to said key code memory means for forming a musical tone having a pitch determined by said key code in said key code memory means, first means for producing a tone pitch voltage corresponding to theoutput of said key code memory means, a capacitor for storing said voltage, a voltage controlled type variable frequency oscillator for generating an oscillation having a frequency determined by the voltage stored in said capacitor, second means forvarying the charging time constant of said capacitor, a second variable frequency oscillator for producing a signal that determines the clock rate for said calculation means, and third means for controlling the oscillation frequency of said secondvariable frequency oscillator, said second means and said third means being so interrelated that said charging time constant becomes shorter as said oscillation frequency of said second variable frequency oscillator becomes higher, and vice versa.
10. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to saidkey code memory means for comparing a first key code received from said key code memory means with a second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to orsubtracting from the content of said key code memory means a predetermined value defining a semitone step repetitively at a predetermined clock rate to change said first key code in said key code memory means until said first key code becomes equal tosaid second key code, tone forming means connected to said key code memory means for forming a musical tone having a pitch determined by said key code in said key code memory means, first means for producing a tone pitch voltage corresponding to theoutput of said key code memory means, a capacitor for storing said voltage, a voltage controlled type variable frequency oscillator for generating an oscillation having a freqency determined by the voltage stored in said capacitor, means for generating asignal representing a released key state, a first gate means connected between said capacitor and said tone pitch voltage generating means, a second gate means for controlling said first gate means by said signal generated by said signal generatingmeans, and a manual switch for controlling said second gate means.
11. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to saidkey code memory means for comparing a first key code received from said key code memory means with a second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to orsubtracting from the content of said key code memory means a predetermined value defining a semitone step repetitively at a predetermined clock rate to change said first key code in said key code memory means until said first key code becomes equal tosaid second key code, tone forming means connected to said key code memory means and forming a musical tone having a pitch determined by said key code in said key code memory means, a variable frequency oscillator for producing a signal that determinessaid clock rate, a variable voltage source which controls the oscillation frequency of said variable frequency oscillator, a comparitor which compares the voltage of said variable voltage source with a predetermined reference voltage, and meansresponsive to the output of said comparitor for rendering inoperative said calculation means thereby directly applying the newly supplied key code signal to said key code memory means.
12. An electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys, key code memory means for storing said key code signals, comparator means connected to said key coder means and to saidkey code memory means for comparing a first key code received from said key code memory means with a second key code received from said key coder means, calculation means responsive to the result of comparison in said comparator means for adding to orsubtracting from the content of said key code memory means a predetermined value defining a semitone step repetitively at a predetermined clock rate to change said first key code in said key code memory means until said first key code becomes equal tosaid second key code, means connected to said key code memory means and forming a musical tone having a pitch determined by said key code in said key code memory means, said key coder means producing said key code signals on a time division basis andsaid key code memory means further comprising a plurality of memory stages for storing said key code signals on the time division basis, said key coder means further comprising memory means for storing said key code signals at memory stages correspondingto time division channels, means for generating a tone pitch voltage corresponding to the output of said key code memory means, a plurality of capacitors corresponding to a plurality of time division channels and adapted to store said tone pitch voltage,a plurality of variable frequency oscillators for generating oscillation frequencies respectively corresponding to the voltages of said capacitors, and switch means for assigning said tone pitch voltage to said capacitors on the time division basis. |
| Description: |
BACKGROUND OF THE INVENTION
This invention relates to an electronic musical instrument of digital processing type, and more particularly to an electronic musical instrument in which a glissando effect and a portamento effect can readily be provided by conducting automaticcalculations on key codes.
Various types of electronic musical instruments have recently been developed with rapid advance in electronic technique. Electronic organs, typical electronic musical instruments, are widely used because they can produce many types of tonecolors and various tone effects thereby enabling versatile rich expressions of music and because they can readily be performed by even not skilled players. The electronic musical instrument of this type forms musical tones by electronic means differentfrom such natural musical instruments as pianos and pipe organs. When classified according to the method of forming musical tones the electronic musical instruments are classified into a tone signal keying system and a synthesizer system. The tonesignal keying system is applied to the conventional type electronic organ according to which tone source signals having frequencies corresponding to the tone pitches of various keys are provided, and the tone source signals of the tone pitches of theoperated keys are selected by the operation of the keys of a keyboard unit and supplied to a tone coloring circuit so as to produce desired musical sounds. This system is disclosed, for example, in U.S. Pat. No. 3,744,809 issued on July 31, 1973 toNiinomi. According to the synthesizer system, as the keys are depressed, voltage signals hereinafter termed tone pitch signals corresponding to the tone pitches of the operated keys are generated which are used to drive and control voltage controlledtype oscillators for producing tone signals corresponding to the tone pitches of the operated keys and a desired musical tone is produced by utilizing these tone signals. This system is disclosed, for example, in U.S. Pat. No. 3,897,709 issued on Aug. 5, 1975 to Hiyoshi et al.
As above described, the electronic musical instruments are constructed to form musical tones by electronic means so that they can produce by a simple manipulation musical tones resembling those of natural musical instruments as well as tonesspecific to electronical musical instruments and for this reason they have been used extensively. It has been desired strongly to construct electronic musical instruments such that they can also provide the glissando effect and the portamento effectwhich are used in natural musical instruments thereby improving the effect of performance.
However, if the player wishes to produce the glissando effect in which the musical scale varies stepwisely with a prior art electronic musical instrument described above he must sequentially depress the keys of a keyboard in succession at aconstant speed and such performance is especially complicated. Especially when a relatively quick glissando is desired a highly skilled technique is necessary. Where a portamento effect is desired in which the tone pitch is continuously varied from onemusical scale note to the other as in one type of a Hawaiian guitar, in the electronic musical instrument of the tone signal keying system described above, it is impossible to obtain the portamento effect, since the frequencies of the tone signals arefixed. For this reason, a special portamento performance device has been added to such electronic musical instruments for obtaining the portamento effect. Such portamento performance device utilizes a variable frequency type oscillator and theoscillation frequency thereof is continuously varied by continuously adjusting a variable resistor or the like for the purpose of producing the portamento effect. This system is disclosed, for example, in U.S. Pat. No. 3,669,422 issued on Oct. 17,1972 to Yoshihara.
However, the operation of an electronic musical instrument incorporated with a portamento performance device as above described is extremely complicated so that not skilled players can not satisfactorily perform the portamento effect. Moreparticularly, to obtain a portamento effect it is necessary to manually operate the operating element of the portamento performance device while performing a melody as well as an accompaniment on a keyboard unit. Moreover, such operation must satisfy adesired varying speed condition and must stop when the musical tone reaches a destination pitch, and therefore requires excellent skill which will not be attained by not skilled players.
SUMMARY OF THE INVENTION
Accordingly, it is the principal object of this invention to provide an improved electronic musical instrument in which the rate of change in the musical tone pitch from a note corresponding to a firstly depressed key to another notecorresponding to a subsequently depressed key can be varied as desired by the use of digital processing.
Another object of this invention is to provide an improved electronic musical instrument in which by mere sequential (successive) operation of the keys of a keyboard unit the musical tone pitch can be automatically varied at a predetermined speedby a step of a semitone or a desired tone interval over a range of from a musical scale note corresponding to a firstly depressed key to a musical scale note corresponding to a subsequently depressed key thus readily producing a glissando effect.
A further object of this invention is to provide an electronic musical instrument in which by mere sequential (successive) operation of the keys of a keyboard unit the musical tone pitch can be automatically and continuously varied at apredetermined speed over a range of from a musical scale note corresponding to a firstly depressed key to a musical scale note corresponding to a subsequently depressed key thereby readily producing a desired portamento effect.
According to this invention there is provided an electronic musical instrument comprising key coder means for delivering key code signals identifying depressed keys in digital representation, key code memory means for storing the key codesignals, comparator means for comparing key codes delivered from the key code memory means with newly delivered key codes, calculation means responsive to the result of comparison in the comparator means for adding to or subtracting from the content ofthe key code memory means a certain value defining a certain note step toward the newly supplied key code, and means for forming musical tones with successively changing tone pitches in accordance with the sequentially varying key code signals.
BRIEF DESCRIPTION OF THE DRAWINGS
Further objects and advantages of the invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram showing the basic construction of an electronic musical instrument embodying the invention;
FIGS. 2A and 2B, when combined as shown in FIG. 2C, show a block diagram of one embodiment of this invention;
FIGS. 3A through 3F are symbols showing various types of logical elements utilized in this invention;
FIG. 4 is a connection diagram showing one example of the timing signal generator shown in FIG. 2;
FIGS. 5A through 5Q are waveforms showing various timing pulses formed by the timing signal generator shown in FIG. 4;
FIG. 6 is a connection diagram showing the detail of one example of the note detection circuit shown in FIG. 2;
FIG. 7 is a connection diagram showing the detail of a key switch circuit;
FIG. 8 is a connection diagram showing the detail of one example of the block detection circuit shown in FIG. 2;
FIG. 9 is a connection diagram showing the detail of a sampling and holding circuit shown in FIG. 2;
FIG. 10 is a connection diagram showing the detail of a state control circuit shown in FIG. 2;
FIGS. 11A through 11O are waveforms at various portions useful to explain the operations of the note detection circuit, the block detection circuit, the state detection circuit and the sampling and holding circuit shown in FIG. 2;
FIG. 12 is a connection diagram showing the detail of one example of a first key code memory circuit;
FIGS. 13A and 13B, when combined as shown in FIG. 13C, show a connection diagram show the detail of one example of the key ON-OFF detection circuit shown in FIG. 2;
FIGS. 14A and 14B, when combined as shown in FIG. 14C, show a connection diagram of one example of a truncate circuit shown in FIG. 1;
FIG. 15 is a connection diagram showing the detail of one example of a depressed key state memory circuit;
FIGS. 16A and 16B, when combined as shown in FIG. 16C, show examples of a comparator circuit, a calculating circuit and a second key code memory circuit shown in FIG. 2;
FIGS. 17A through 17G are waveforms of various portions useful to explain the operation of a pulse width adjusting circuit shown in FIG. 16;
FIG. 18 is a connection diagram showing the detail of one example of a sampling control circuit shown in FIG. 2;
FIGS. 19A and 19B, when combined as shown in FIG. 19C, show a connection diagram showing the detail of one examples of a sampling circuit and an analogue-digital conversion circuit shown in FIG. 2;
FIGS. 20A through 20R are waveforms of various portions useful to explain the operations of the sampling control circuit, sampling circuit and the analogue-digital conversion circuit;
FIG. 21 is a connection diagram showing the detail of one examples of the tone pitch voltage controllers for respective channels, and the musical tone forming unit; and
FIG. 22 is a connection diagram showing the detail of one examples of a tone pitch voltage controller and the control panel shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A preferred embodiment of this invention will now be described in detail with reference to the accompanying drawings. The electronic musical instrument 10 shown in FIG. 1 comprises a keyboard 12 provided with a plurality of keys. When the keysare depressed, a key coder 14 produces key code signals KC corresponding to the depressed keys and encoded digitally. The key codes are sent to a key code converter unit or key code converter 20 which comprises a memory circuit 22 for storing a key codecorresponding to a firstly depressed key (hereinafter termed first key code signal), a comparator 24 for comparing the output of the memory circuit 22 with a key code corresponding to a subsequently depressed key (hereinafter termed second key codesignal) and a calculation unit (arithmetic unit) 26 which repeatedly add or subtract a predetermined value to and from the first key code signal stored in the memory device 22 until the result of calculation comes to coincide with the second key codesignal. The calculation unit 26 comprises a gate circuit 30 connected to receive the key code from the key coder 14, a full adder 32 responsive to the output of the gate circuit 30 for producing an output S, a detector 34 watching a portion of theoutput (key code) of the memory circuit 22 for judging whether the value to be added to or subtracted from the full adder 32 should be "1" or "2" and a gate circuit 36 which is enabled (opened) when a portamento control signal is not applied via terminal30.sub.a for applying the output of the memory device 22 to an input terminal B of the full adder 32, whereas disabled when the portamento (glissando) control signal is applied via terminal 30.sub.a for preventing the output of the memory device 22 frombeing applied to the input terminal B of the full adder 32. The gate circuit 30 operates to send an output to the full adder 32 indicating that "1" or "2" should be added or subtracted or that any addition or subtraction is not necessary in response tothe result of comparison between the first key code signal stored in the memory circuit 22 and the second key code signal newly supplied from the key coder, which is made by the comparator 24, and to a signal that discriminates whether a value to beadded or subtracted is "1" or "2". The signal for effecting the addition and subtraction described above is formed by an calculation timing pulse supplied to the gate circuit 30 via a terminal 30.sub.b.
The output from the memory circuit 22 is sent to a tone pitch voltage controlling and musical tone forming circuit 20 to act as a note code for forming a desired musical tone.
The operation of the key code converter 20 will now be described.
The operation of a case wherein a portamento (glissando) is not performed will firstly be described. At this time, a potamento (glissando) control signal is not applied to the gate circuits 30 and 36 via the terminal 30.sub.a. As a consequence,the gate circuit 36 is enabled to supply the output of the key coder 14 to the full adder 32 without any modification. Accordingly, the output S from the full adder is the same as the output from the key coder and stored in the memory circuit 22, andthe output thereof is sent to the tone pitch voltage controlling and musical tone forming device 40 to form a predetermined musical tone.
Next, a case in which a portamento (glissando) is performed during the course of performance will be described. At this time, the portamento (glissando) control signal is applied to the gate circuits 30 and 36 via terminal 30.sub.a. Then thegate circuit 36 is enabled to apply the output of the memory circuit 22 to the input terminal B of the full adder 22, whereas the gate circuit 30 prevents the output key code signal of the key coder 14 from being applied directly to the input A of thefull adder 32 so as to perform the following operation in response to the outputs of the comparator 24 and the detector 34.
Suppose now that the first key code signal is being stored in the memory device 22. Under these conditions, when the key coder 14 produces the second key code signal, the comparator 24 compares the second key code signal with the first key codesignal read out from the memory device 22 thereby producing on a line 24.sub.a a signal indicating that which one of the key code signals is larger. When both key code signals coincide with each other the comparator produces a coincidence signal on theline 24.sub.a.
The detector 34 detects a signal from the output of the memory circuit 22 which discriminates that whether a step value to be added or subtracted is "1" or "2". When applied with the above described signals from the comparator 24 and thedetector 34, the gate circuit 30 performs the following logical operations.
Where the first key code signal is smaller than the second key code signal, that is when the key codes are becoming higher, the gate circuit 30 judges that whether the output from the detector 34 is one of note codes C.music-sharp., D, E, F, G,G.music-sharp., A.music-sharp. and B or not, and when it is not such, the gate circuit 30 sends to the full adder 32 an output indicating that "2" should be added to the output of the memory circuit. On the other hand, when it is one of such notecodes, the gate circuit 30 applies to the full adder 32 a signal indicating that "1" should be added to the output of the memory circuit.
Where the first key code signal is larger than the second key code signal, that is when the key codes are descending, the gate circuit 30 judges that whether the output from the detector 34 is one of the note codes D, D.music-sharp., F,F.music-sharp., G.music-sharp., A, B and C or not, and when it is not such, the gate circuit 30 sends to the full adder 32 an output indicating that "2" should be added to the output from the memory circuit 22. On the other hand, when it is one of suchnote codes, the gate circuit 30 sends to the full adder 32 a signal indicating that "1" should be added to the output of the memory circuit.
When a signal showing the coincidence between the first and second code signals is supplied from the comparator 24 during the logical operation described above, the gate circuit 30 terminates such logical operation. At this time, the content ofthe memory circuit 22 is equal to the second key code signal.
The operation of this invention as applied to an actual electronic musical instrument will now be described with reference to FIGS. 2 and following drawings.
The principal elements of the embodiment of this invention shown in FIGS. 2A and 2B comprises a key coder 100 which is constructed to detect key switches operated by depressed keys (one key switch is provided for each key, and where the switch isof the make contact type, the switch is closed when associated key is depressed, whereas in the case of the break contact type, the switch is opened when the key is depressed) for producing coded signals representing the detected key switches, that iskey codes KC; a channel processor 200 for assigning the key codes supplied from the key coder 100 to either one of the channels that can simultaneously produce tones (the number of the channels is much smaller than the number of keys, for example 8,which is the number of keys that can be operated simultaneously, or with a slight time difference, that is the maximum number of the keys that can be operated with both hands and one foot); a key code converter 300 which operates and processes the keycodes supplied from the channel processor thereby converting them into key codes KC' utilized to obtain a glissando effect or a portamento effect; a key code-tone pitch voltage converter 400 for generating voltages KV determining the pitches of the tonescorresponding to the key codes supplied from the key code converter 300; a tone pitch voltage control unit for each channel 500 responsive to the operated and released key switches which are assigned to respective channels by the channel processor 200for controlling the tone pitch voltage KV; a musical tone forming unit 600 which produces a musical tone signal for each channel corresponding to each tone pitch voltage KV supplied from each tone pitch voltage control unit 500 a tone pitch voltagecontrol unit 700 which controls the tone pitch voltage control unit 500 for each channel for exercising the change over between the glissando and the portamento effects and controlling the speed of the glissando and the portamento effects; a timingsignal generator 800 for supplying various timing signals to various units described above, and a loudspeaker and a amplifier for generating the musical sounds corresponding to the output of the musical tone forming unit 600.
The key coder 100 is provided with a key switch circuit 102 including a plurality of key switches 101.sub.a -101.sub.n which are divided into a plurality of blocks (for example, groups for respective octaves). The key switches of each group areassigned to corresponding notes (for example keys for 12 notes of C, C.music-sharp., D . . . B). One terminals a (movable contacts) of respective key switches 101.sub.a -101.sub.n of the respective blocks are commonly connected for the same namednotes, and wiring lines N.sub.1 -N.sub.n are provided for respective notes. The other contacts b (stationary contacts) of the key switches 101.sub.a -101.sub.n of the same group are also commonly connected and wiring lines B.sub.1 -B.sub.l are providedfor respective blocks. Consequently, each one of the key switches 101.sub.a -101.sub.n connected between column and row lines at each cross-point of a matrix circuit constituted by the block wiring lines B.sub.1 -B.sub.l which act as the row lines andthe note wiring lines N.sub.1 -N.sub.m which act as the column lines. For this reason, the total number of the wiring lines derived out from key switch circuit 102, that is the sum of the number of the block wiring lines B.sub.1 -B.sub.l and the numberof the note wiring lines, it much smaller than the number of the entire key switches 101.sub.a -101.sub.n. For example, assuming that the total number of the key switches 101.sub.a -101.sub.n is equal to (1.times.m) the total number of the wiring linesderived out from the key switch circuit is equal to the sum of the number of the notes m and the number of blocks 1, that is (m+1). The key switches 101.sub.a -101.sub.n of the key switch circuit 102 constructed as above described are connected to anote detection circuit 103 via note wiring lines N.sub.1 -N.sub.m and to a block detection circuit 104 via block wiring lines B.sub.1 -B.sub.l.
The detection of all operated ones of the key switches 101.sub.a -101.sub.n is performed by sequentially detecting the operation states (hereinafter merely termed states) of several types.
At the first state ST.sub.1, a signal is applied to the movable contacts a of all key switches 101.sub.a -101.sub.m from the note detection circuit 103 via the note wiring lines N.sub.1 -N.sub.m and the signal is applied to the block wiring wiresB.sub.1 -B.sub.l of the block to which the operated key switches belong via the stationary contacts b of only the operated key switches. The signal thus derived out is supplied to the block detection circuit 104 and stored therein. In this manner, thepresence of one or more of the operated key switches of any block can be detected. During the first state, the timing of storing the signal in the block detection circuit 104 is determined by a first state signal supplied from a state control circuit105 which operates in synchronism with the timing signal generator 500. Upon completion of the storing operation of the block detection circuit 104, the state control circuit 105 detects this condition and then controls the second state.
During the second state ST.sub.2, one block is extracted according to a predetermined order of preference from one or a plurality of blocks that have been stored in the block detection circuit so as to apply a signal to the stationary contacts bof the key switches belonging to said extracted block via block wiring lines B.sub.1 -B.sub.l corresponding to the block extracted from the block detection circuit 104 whereby the signal is derived out from the stationary contacts a of the key switchesof respective notes in said one block via note wiring lines N.sub.1 -N.sub.m. This derived out signal is then stored in the note detection circuit 103. In this manner the signal from the block detection circuit 103 is transmitted to only note wiringlines N.sub.1 -N.sub.m corresponding to the operated ones of the key switches 101.sub.a -101.sub.n and this signal is stored in the note detection circuit 103, thereby detecting the note codes of one or a plurality of the operated key switches belongingto the extracted block. The block signal extracted by the block detection circuit 104 is converted or encoded into a block code signal (hereinafter termed a block code BC) comprising a plurality of bits (for example 3) representing the block, and theblock code is stored in a sampling and holding circuit 106. The timing of extracting one block of the block detection circuit 104 during the second state and the timing of storing of the note detection circuit 103 are determined by the second statesignal supplied by the state control circuit 105 in the same manner as in the first state described above. Upon completion of the storing operation of the note detection circuit 103, the state control circuit 105 detects this condition and then controlsa third state.
The third state ST.sub.3 is an operation state following the second state ST.sub.2. In the third state, one or a plurality of states that have been stored in the note detection circuit 103 during the second state are sequentially extractedaccording to a predetermined order of preference and in synchronism with the clock pulse. The extracted note signal is then connected or encoded into a note code signal (hereinafter termed a note code NC) comprising a plurality of bits (in this example4) which represents the extracted note signal, and the note codes NC are sequentially supplied to the sampling and holding circuit 106. Since the third state ST.sub.3 is executed only for a note stored in the note detection circuit 103 there is not timeloss. For example, where three types of the notes are stored in the note detection circuit 103 a third state regarding a specific block will terminate after three clock pulses. When all note codes stored in the note detection circuit 103 are read outthe state control circuit 105 detects this state to prepared for the control of the next state. In this case, when some of the memories of the block signals still remain in the block detection circuit 104 the control returns to the control of the secondor third state for executing the same in the same manner as above described. Where there is no memory of the block signal remaining in the block detection circuit 104 the control is returned again to the first state.
The sampling and holding circuit 106 stores and holds a block code BC supplied from the block detection circuit 104 during the third state and produces the block code BC in synchronism with a note code NC supplied from a note detection circuit103. Accordingly, the sampling and holding circuit 106 produces a key code KC having 7 bits, for example, corresponding to the combination of the block code BC and the note code NC. The key code KC enables ready discrimination between operated keyswitches. In this manner, before completion of the detection of all operated key switches the control is proceeded stepwisely, namely the first state ST.sub.1 .fwdarw.the second state ST.sub.2 .fwdarw.the third state ST.sub.3 . . . . When a block codeBC regarding all blocks which have been firstly stored in the block detection circuit 104 is transmitted and when the transmission of the note code NC regarding the note of the operated key switches in the last block is completed all memories in theblock detection circuit 104 and the note detection circuit 103 are extracted so that no memory is remaining in the block detection circuit 104 and the note detection circuit 103, whereby the state is advanced to the fourth state ST.sub.0 or the waitstate. When the state control circuit 105 confirms that operations of the key switch circuit 102, the note detection circuit 103 and the block detection circuit 104 have been reset, the first state ST.sub.1 is resumed. Thereafter the fourth stateST.sub.0, that is the wait state, will be reached by repeating the second and third states ST.sub.2 and ST.sub.3 in a manner as above described during which the detection operations of all key switches are repeated once.
The key code KC sent from the sampling and holding circuit 106 of the key coder 100 is applied to the channel processor 200 in which channels for forming the musical tone signals are assigned. At this time, the key code KC sent out from thesampling and holding circuit 106 is held for a definite interval and the holding time corresponds to one operation time in which one assignment is executed in the channel processor 200.
The channel processor 200 comprises a first key code memory circuit 201, a key ON-OFF detection circuit 202, a truncate circuit 203 and a depressed key state memory circuit 204.
The first key code memory circuit 201 comprises a specific number of the memory circuits corresponding to the number of channels that can produce musical tones simultaneously when a plurality of keys are depressed simultaneously. It isadvantageous to construct each memory circuit with a circulating shift register. Suppose now that the number of the channels is equal to A that the number of bits of a key code KC is equal to B, an A stage (one stage=B bits) shift register having Bmemory units is used, and a key code KC already stored or assigned is shifted sequentially and sent out on the time division basis by the clock pulse. The sent out key code is used as a control signal for generating a musical tone waveform and also fedback to the input side of the shift register for circulation.
The key ON-OFF detection circuit 202 compares an input key code KC supplied from the key coder 100 with the all memory key codes sequentially sent out from the first key code memory circuit 201 on the time division basis and when these key codescoincide with each other, the key ON-OFF detection circuit 202 prevents the key code from being stored in the first key code memory circuit 201, in other words, the assignment of the channels is terminated under a judgement that a key code KC which isidentical to the input key code KC has already been assigned to a specific channel. In the case of a non-coincidnece, the input key code KC is stored in all vacant channels of the first key code memory circuit 201 because a new key has been depressed. Furthermore, where the respect of comparison is a non-coincidence and a key code KC has been assigned to all vacant channels, the truncate circuit 203 detects a channel to which has been assigned a tone corresponding to an already released key and hasattenuated to the largest extent thereby controlling such that the key code KC stored in that channel will be forcibly rewritten as an input key code KC. Each time the key code KC is assigned, the key ON-OFF detection circuit 202 supplies the state ofassignment of the inpout key code KC of respective channels to the depressed key state memory circuit 204 to store the state of assignment therein. The output from the memory circuit 204 is used to control the musical tone generation of respectivechannels as will be described later and to detect the released key so as to change the corresponding memory content of the depressed key state memory circuit 204 thereby terminating the musical tone generation while gradually attenuating the musical tonegenerated by a channel according to a predetermined condition. During the subsequent operation, vacant channels are selected in a accordance with the content stored in the depressed key memory circuit 204 for applying an input key code KC to a stage ofa corresponding channel of the first key code memory circuit 201. The portions of the first key code memory circuit 201 and the depressed key state memory circuit 204 corresponding to respective channels are selected in synchronism and on the timedivision basis for storing the signal.
The key code coverter 300 comprises a characterizing element of the embodiment shown in FIG. 1 and corresponds to the key code converter 20. Only when a control signal is applied to the control terminal 301 (corresponding to the terminal30.sub.a shown in FIG. 1) the key code converter 300 functions to operate and process the key codes KC which are sequentially supplied from the channel processor 200 whereby the key codes are sequentially shifted including both addition and subtractionunder a definite condition over a range of from a key code corresponding to an operated key to a key code KC corresponding to a subsequently depressed key thus converting the key codes KC into shifted key codes KC' which are useed to obtain a glissandoeffect or a portamento effect.
The key code convetr 300 comprises a key code shift control terminal 301; a second key code memory circuit 302 (corresponding to the memory circuit 22 shown in FIG. 1) constituted by a circulating shift register having a plurality of memorystages of the number equal to the number of channels and operates to sequentlially store the key codes KC supplied from the channel processor 200; an operation circuit 303 which stores again in the second key code memory circuit 302 an operated key codeKC' which is formed by adding or subtracting a predetermined value to and from the output key code KC' read out from the second key code memory circuit 302 only when a control signal is applied to the key code shift control terminal 301; and a comparator304 (corresponding to the comparator 26 shown in FIG. 1) which compares an input key code KC supplied from the channel processor 200 with an output key code KC' from the second key code memory circuit 302 and terminates the operation and processing ofthe operation circuit 303 which corresponds to the calculation device 26 shown in FIG. 1 when the key codes KC and KC' coincide with each other. The addition and subtraction operations of the operation circuit 303 is controlled by a signal supplied bythe comparator 304 in accordance with the result of comparison. Where the output key code KC' from the second keycode memory circuit 302 is larger than the input key code KC supplied from the channel processor 200 a subtraction operation is performed,whereas when the output key code KC' is smaller than the input key code KC an addition operation is performed. In other words, when a key producing a higher tone pitch than that of a firstly operated key is subsequently operated, an addition processingis performed so that the memory in the second key code memory circuit 302 is sequentially shifted such that the output key code KC' from the second key code memory circuit will become a key code KC which produces a higher tone pitch, whereby the musicaltone forming unit 600 produces a musical tone signal which increases stepwisely for obtaining a glissando effect, or a musical tone signal which increases continuously for obtaining a portamento effect. The operation period of the operation circuit 303is determined by a speed control pulse applied to a speed control terminal which corresponds to terminal 30.sub.b shown in FIG. 1 whereby the speeds of the glissando and portamento effects are controlled variably.
The key code tone pitch voltage converter unit 400 comprises a sampling circuit 401, a sampling control circuit 402 which controls the sampling period and a digital-analogue converter circuit 402. In the key code tone pitch voltage generatorunit 400, the key code KC' supplied from the key code converter 300 is sampled by the sampling circuit 401 and the sampled key code KC" is applied to the digital-analogue converter circuit 403. The sampling period of the sampling circuit 401 isdetermined by the output of the sampling control circuit 402 and the sampling period is equal to a time in which the number of the clock pulses necessary to shift the content of the second key code memory circuit is counted by a number equal to thenumber of channels plus one. Accordingly, each time one cycle of shifting of the second key code memory circuit 302 is substantially completed, the sampling circuit 401 sequentially samples key codes corresponding to different channels and continues tocontinuously produces the sampled key code KC' till the next sampling time thereby performing decreased speed sampling. Because, the key coder 100, the channel processor 200 and the key code converter unit 300 are required to rapidly detect the state(key depressed and key released states) of the key switches 101.sub.a -101.sub.n as well as the assignment to the channels whereas the portions handling the tone pitch voltage are not required to operate at a high speed because in these portions the keycodes are processed parallelly and because when the tone pitch voltage of the analogue signal is processed at a high speed, it is difficult to follow up such high speed processing. More particularly, a small static capacitance of the circuit system andthe wirig lines distort the waveform thus making it difficult to obtain a correct musical tone commensurate with the key code KC'. For the various reasons described above, key code KC' is sampled at a low speed and the sampled key code KC" is thenconverted into an analogue signal which is applied to the voltage controlled type variable frequency oscillators of respective channels to act as the tone pitch voltage KV. The digital-analogue converter circuit 403 connected to the output side of thesampling circuit 401 operates to convert the above described key code KC" into a corresponding tone pitch voltage KC. The digital-analogue converter circuit 403 is connected to receive a key code KC" which is sampled by the sampling circuit 401 at a lowsampling speed and to divide the sampled key code KC" into a block code BC" and a note code NC" which are decoded separately. The decoded block code BC" is applied to a resistance potentiometer for deriving out a voltage signal corresponding to theblock code. The derived out voltage signal is further divided by the decoded note code NC" in proportion to the note thereby producing a tone pitch voltage KV corresponding to the key code KC". By the control signal supplied from the sampling controlcircuit 402 the tone pitch voltage KV is distributed among the channels to which the key codes KC" sampled by the sampling circuit 401 are assigned. Distribution of the tone pitch voltage KV among respective channels is done in synchronism with theoperation of the depressed key state memory circuit 204, and the selected channels are also the same. As above described the tone pitch voltage KV converted into an analogue voltage corresponding to the key code KC" is distributed among respectivechannels. However, when converting the key code KC" into the tone pitch voltage KV the building up portion of the converted tone pitch voltage KV would be smeared due to a small capacitance of the circuit system of the digital-analogue converter.
For this reason, when the tone pitch voltage KV converted in proportion to the key code KC" is applied to the musical tone forming circuit in the later stage starting from the initial portion, that is the building up portion of the converted tonepitch voltage, due to the smear caused by the building up portion, a musical tone quite different from the key code KC" would be formed and the musical tone frequency increases gradually, thereby finally producing a musical tone having a frequencycorresponding to the desired key code KC". The smear at the building up portion of the tone pitch voltage KV persists only a very short time but in an ordinary musical instrument the musical tone at the time of starting the tone is also important. Forthis reason, the digital-analogue converter circuit 403 is constructed to distribute the tone pitch voltage among respective channels only when the digital-analogue conversion has been completed. In other words, after being blocked for a very short time(a fraction of the sampled output) after reception of the key code KC" from the sampling circuit the tone pitch voltage KV is distributed among various channels.
The tone pitch voltage control unit 500 for respective channels comprises a plurality of tone pitch voltage control circuits 501.sub.a -501.sub.h independently provided for respective channels. The tone pitch voltage control circuits 501.sub.athrough 501.sub.h are constructed to independently receive the tone pitch voltage KV supplied from the digital-analogue converter circuit 403 and to enable (open) a gate circuit by a key-ON signal supplied from the depressed key state memory circuit 204thereby storing the tone pitch voltage KV in a capacitor, the terminal voltage thereof being sent to the musical tone forming unit 600 as will be described later. The tone pitch voltage control circuits 501.sub.g -501.sub.h are also constructed tocontrol the charging time constant of the capacitor when the tone pitch voltage KV is applied by a control signal supplied from a tone pitch voltage control unit 700 to be described later so as to vary the building up and building down of the output tonepitch voltage KV' thereby obtaining a glissando effect or a portamento effect.
The musical tone forming unit 600 includes a plurality of musical tone forming circuits 601.sub.a -601.sub.h independently provided for respective channels. Although not shown, each musical tone forming circuit comprises a voltage controlledvariable frequency oscillator (VCO), a voltage controlled type variable filter (VCF), a voltage controlled type variable gain amplifier (VCA), and an envelope generator (EG) for programming the timing and the amount of controlling various componentelements described above (VCO, VCF, VCA). When a tone pitch voltage KV' is applied from the tone pitch voltage control circuits 501.sub.a -501.sub.h voltage controlled type variable frequency oscillator VCO generates an oscillation having a frequencycorresponding to the applied tone pitch voltage KV'.
The oscillation output is sent out via VCF and VCA to act as a musical tone signal and mixed with musical tone signals sent from musical tone forming circuits of the other channels by mixing resistors 900.sub.a -900.sub.h. The mixed signal issupplied to a loudspeaker, not shown, through an output terminal. When VCO, VCF and VCA are controlled by a waveform control signal generated by an envelope generator (EG) the oscillation frequency of the VCO is varied finely in accordance with thewaveform control signal whereas in the VCF, its frequency characteristic is varied to form a musical tone signal resembling the tone of a natural musical instrument. Furthermore, in the VCA, the envelope of the musical tone is controlled in accordancewith the control waveform. The envelope generator EG is controlled by an adjusting lever, not shown, provided for the control panel 950 of the electronic musical instrument and its timing of starting control is determined by a key-ON signal suppliedfrom the depressed key state memory circuit 204.
The tone pitch voltage control unit 700 supplies a control signal to each of the tone pitch voltage control circuits 501.sub.a -501.sub.h of the tone pitch voltage control unit 500 for respective channels so as to vary the charging time constantof the capacitor provided for respective tone pitch voltage control circuits 501.sub.a -501.sub.h thereby controlling the variation of the tone pitch voltage during switching between the glissando and portamento effects and during sustaining.
The switching between the glissando and portamento effects are performed by operating a transfer switch provided for the control panel 950. Furthermore, the tone pitch voltage control unit 700 is connected to apply a portamento (glissando)control signal and an addition control pulse to the terminals 301 and 305 respectively of the key code converter unit 300 described above.
The timing signal generator 800 generates various synchronizing signals by counting a reference clock signal supplied from an oscillator, not shown and supplies the synchronizing signals to various component elements described above therebysynchronizing the operations thereof.
Having described the outline of the fundamental elements and operations thereof of one embodiment of an electronic musical instrument embodying the invention the detail of the construction and operation of various elements will now be describedwith reference to detailed connection diagram and waveforms.
Before describing detailed circuits, symbols utilized therein will firstly be described. Thus FIG. 3A shows an inverter, FIGS. 3B and 3C AND gate circuits, FIGS. 3D and 3C OR gate circuits, and FIG. 3F a delay flip-flop circuit termed as Dflip-flop. Where the number of the inputs is small, standard symbols as shown in FIGS. 3B and 3C are used. However, where there are many inputs modified symbols as shown in FIGS. 3C and 3E are used. More particularly in the cases of FIGS. 3C and 3E, asingle input line is depicted on the input side and a plurality of signal lines are depicted to cross the input line, and the cross points between the used input lines and the single line are bounded by small circles. In the case of FIG. 3C, the logicalequation is: Output=A.multidot.B.multidot.D whereas in the case of FIG. 3E Output=A+B+C.
Timing Pulse Generator 800
FIG. 4 shows the detail of the timing pulse generator 800 shown in FIG. 2 which generates a reference control signal for the electronic musical instrument. For this reason, this timing pulse generator will be described at first. It comprises afour bit counter 801 constituted by four cascade connected flip-flop circuits, and a shift register 802 having a plurality of bits of the number equal to that of the channels. In this embodiment, the number of channels is 8. There is provided areference oscillator, not shown, which produces an output pulse .phi.. The frequency of pulse .phi. is reduced to obtain output pulses .phi..sub.1 and .phi..sub.2. The counter 801 counts the clock pulse .phi..sub.1 shown in FIG. 5A. This clock pulse.phi..sub.1 is an extremely high frequency pulse having a period of 1 .mu.s, for example. In the following, the pulse period is called "a channel time". Assume now that the number of tones of the electronic musical instrument which are generatedsimultaneously is 8, then the number of the channels is 8 so that the time slots sequentially sectionalized by the clock pulse .phi..sub.1 and having a width of 1 .mu.s are sequentially assigned to the first to eighth channels. Because, the channelprocessor 200 is constructed to operate under a dynamic logic by operating various memory circuits and logic circuits on the time division bases in order to form a plurality of musical tones at the same time by depressing a plurality of keys at the sametime or at slightly different times. As shown in FIG. 5B, when respective time slots are sequentially assigned to first to eighth channel times, each channel time will be repeatedly generated at each 8 channel times. More particularly, when a clockpulse .phi..sub.1 is applied to the input terminal of the counter 801 from an oscillator, not shown, the counter sequentially counts the clock pulse and produces the result of count as a binary decimal code outputs comprising parallel four bits. Amongthese outputs, the output of the most significant flip-flop circuit is derived out through an inverter 803.sub.d as output pulses S.sub.1 -S.sub.8 in a range of from the first to the eighth channel times, as shown in FIG. 5C. Also, the most significantflip-flop circuit produces not inverted pulses S.sub.9 -S.sub.16 as shown in FIG. 5D. When the parallel four bit output signals of the counter 801 are simultaneously applied to the inputs of an AND gate circuit 804, this AND gate circuit is enabled todetect the full count condition, thus producing a pulse S.sub.16 as shown in FIG. 5E at the time of the full count. This pulse S.sub.16 is inverted by an inverter 805 to obtain a pulse S.sub.16. Thus, the pulse S.sub.16 is produced at each assignedprocessing time (16 .mu.s) of the channel processor 200. The processing time is equal to a time in which respective channel times circulate twice. This is because that the channel processor 200 compares the input key code KC with the memory code KCwhich has already been assigned in the first 8 channel times and performs a writing operation in the succeeding 8 channel times. Pulses S.sub.1 -S.sub.8, and pulses S.sub.9 -S.sub.10 shown in FIGS. 5C and 5D respectively separate the first half 8channel times and the second half 8 channel times.
When the first to third outputs among the parallel four bit outputs from the counter 801 are simultaneously applied to the inputs of an AND gate circuit 806, this AND gate circuit is enabled to produce output pulses S.sub.8 and S.sub.16 at aninterval of 8 channel times as shown in FIG. 6G. The output pulses S.sub.8 and S.sub.16 produced by the AND gate circuit 806 are applied to an 8 bit shift register 802 and sequentially shifted by the clock pulses .phi..sub.1 and .phi..sub.2 therebyproducing pulses BT.sub.1 -BT.sub.9 from respective bits corresponding to the sequential sampling of the first to eighth channel times as shown in FIGS. 5J through 5Q.
Consequently, the outputs from respective bits of the shift register 802 correspond to timing signals which are derived out in parallel at a spacing of eight channel times. The first to seventh bit output of the shift register 802 is taken outthrough an OR gate circuit 807, and an AND gate circuit 808 is enabled when the output of the OR gate circuit 807 and the output from the most significant bit of the counter 801 are simultaneously applied to its inputs thus producing a clock pulse.phi..sub.A as shown in FIG. 5H. An AND gate circuit 809 is enabled when the output of the OR gate circuit 807 and the output of the inverter 803.sub.d are simultaneously applied to its inputs for producing a clock pulse .phi..sub.B as shown in FIG. 5I.
On the output side of the shift register 802 are connected AND gate circuits 810.sub.a -810.sub.h which are enabled by the output of the shift register 802 and the respective outputs A.sub.0 -A.sub.7 of the depressed key state memory circuit 204as will be described later. The outputs of the AND gate circuit 810.sub.b -810.sub.h are applied to the inputs of a NAND gate circuit 811 for producing an enabling signal ENB which is used in the channel processor 200.
The timing pulse generator 800 further comprises a shift register 815 having channels, the number of the stages of the shift register being (in this example, 8) equal to that of the channels in the same manner as the shift register 802. Theoutputs of respective stages of the shift register 815 are applied to the inputs of a NOR gate circuit 816 together with an initial clear signal IC which is produced when a power switch, not shown, is closed. The output of the NOR gate circuit 816 isapplied to the first stage of the shift register 815. Like shift register 802, the shift register 815 is driven and its content is shifted by two phase clock pulses .phi..sub.1 and .phi..sub.2 and applies its output to one input of a NAND gate circuit817 from its first stage output. To the other input of the NAND gate circuit is applied to BT.sub.8 pulse from shift register 802. For this reason, NAND gate circuit 817 produces on pulse SYNC at each 72 clock pulses.
The initial clear signal IC is produced by differentiating the voltage variation which occurs when the power switch is closed. Since the circuit for producing the initial clear signal is well known in the art, it is not shown herein.
Various circuit elements operate by using the pulse signals and the clock pulses as the timing signals. The operations of various circuit elements will be described sequentially in the following.
Key Coder 100
The key switch circuit 102 is shown in FIG. 6, one example of the note detection circuit 103 is shown in FIG. 7 and one example of the block detection circuit 104 connected to the key switch circuit 102 shown in FIG. 6 is shown in FIG. 8. FIG. 9shows one example of a sampling and holding circuit which samples the note code NC and the block code BC respectively produced by the note detection circuit 103 and the block detection circuit 104 shown in FIGS. 7 and 8 respectively for matching thetiming of the note code and the block code, and FIG. 10 shows one example of the state control circuit 105 which controls the operations of the note detection circuit 103, block detection circuit 104 and the sampling and holding circuit 106 describedabove. As will be described hereinafter in detail, the key coder 100 is constituted by these circuit elements.
A. Key Switch Circuit 102
The key switch circuit is shown in FIG. 6 and provided with a plurality of key switches 101.sub.a -101.sub.n respectively corresponding to the keys of the keyboard of an electronic musical instrument. One of the terminals (stationary contacts)of the key switches 101.sub.a -101.sub.n are commonly connected to respective blocks U.sub.1 -U.sub.5 and then connected to the block input/output terminals 106'.sub.a -106'.sub.e shown in FIG. 8 via block wiring lines B.sub.1 -B.sub.5. The otherterminals (movable contacts) of the key switches 101.sub.a -101.sub.n are connected respectively in series with diodes 107.sub.a -107.sub.n which are used for the purpose of preventing the current from one terminal from flowing to the other terminal. The diodes for the same named note (C.music-sharp., D . . . A.music-sharp., B, C) are commonly connected and then connected to note input/output terminals 108.sub.a -108.sub.l respectively through note wiring lines N.sub.1 -N.sub.12. The number of keysof a two stage keyboard is generally 61. If these keys are divided into five blocks (five octaves) of U.sub.1 -U.sub.5, the key (hereinafter called a CL note) of the lowest octave would becomes surplus. It is uneconomical to increase the number ofblocks for this surplus CL note. For this reason, in the embodiment shown in FIG. 6, the CL note is included in block U.sub.1 so that this block covers 13 key switches. More particularly, one terminal of the key switch 101.sub.n corresponding to the CLnote is connected to block wiring line B.sub.5, while the other terminal is connected to the note input/output terminal 108.sub.n via note wiring line N.sub.13.
Since the keyboard portion (key switch circuit 102) and the electrical circuit portion (note detection circuit 103 and block detection circuit 104) are generally located remotely, the length of the wiring lines N.sub.1 -N.sub.13 interconnectingthe key switch circuit 102 and the note detection circuit 103 and the wiring lines interconnecting the key switch circuit 102 and the block detection circuit 104 is large thereby accompanying line capacitances C.sub.b and C.sub.n. For the sake ofdescription the capacitance of lines B.sub.1 -B.sub.5 is denoted by C.sub.b and that of lines N.sub.1 -N.sub.13 by C.sub.n. Of course, line capacitances C.sub.b and C.sub.n are independent from each other but in this embodiment they are utilizedefficiently.
In the note detection circuit 103 shown in FIG. 7 signal transmission circuits 109.sub.a -109.sub.n, detected note memory circuits 110.sub.a -110 .sub.m and note preference gate circuits 111.sub.a -111.sub.m are provided for each one of the notesC, B . . . C.music-sharp., and CL. Although FIG. 7 shows the detail of only the signal transmission circuits 109.sub.a, 109.sub.e and 109.sub.m, the detected note memory circuits 110.sub.a, 110.sub.e and 110.sub.m and the note preference gate circuits111.sub.a, 111.sub.e and 111.sub.m for notes C, C.music-sharp. and CL, and the circuits for the other notes are constructed in the same manner. Signal transmission circuits 109.sub.a -109.sub.m apply voltage V.sub.DD to note input/output terminals108.sub.a -108.sub.m by the switching action of transistors 112 provided for each note to charge the line capacitance of the note wiring lines N.sub.1 -N.sub.13. The signals from the note input/output terminals 108.sub.a -108.sub.m are supplied to thedetected note memory circuits 110.sub.a -110.sub.m each constituted by an inverter 113, AND gate circuits 114 and 115, an OR gate circuits 116 and a delay flip-flop circuit 117 and independently stores a pulse ST.sub.2 ' (described to be later) suppliedfrom the state control circuit 105. When a detected note signal is applied to either one of the detected note memory circuits 110.sub.a -110.sub.m, the OR gate circuit 118 sends out a note presence signal AN. The memories read out from the detectedmemory circuits 110.sub.a -110.sub.m are supplied to the note preference gate circuits 111.sub.a -111.sub.m each comprising an OR gate circuit 119, an inverter 120 and an AND gate circuit 121 whereby the memory contents of the detected note memorycircuits 110.sub.a -110.sub.m are read out in accordance with a predetermined order of preference and each read out memory is supplied to a note code transmission circuit 122 thus sending out through one of OR gate circuits 123'.sub.a -123'.sub.d 4 bitnote code corresponding to each note code. The note preference gate circuits 111.sub.a -111.sub.m are constructed such that the memory contents of the detected note memory circuits 110.sub.a -110.sub.m are sequentially read out from the note preferencegate circuit 111.sub.a on the upper side toward the note preference gate circuit 111.sub.m on the lower side whereby the read out memory contents are converted into note codes NC. Where either one of the detected note memory circuits 110.sub.a-110.sub.m is detected a memory note signal MN is sent out via OR gate circuit 119 of one note preference gate circuit.
B. Block Detection Circuit 104
As shown in FIG. 8, the block detection circuit 104 comprises detected block memory circuits 123.sub.a -123.sub.e, block preference gate circuits 124.sub.a -124.sub.e, signal transmission circuits 125.sub.a -125.sub.e and a block codetransmission circuit 126 which are provided independently for each one of the blocks U.sub.1 -U.sub.5. Each one of the detected block memory circuits 123.sub.a -123.sub.e is constituted by an inverter 126', AND gate circuits 127 and 128, an OR gatecircuit 129 and a delay flip-flop circuit 130. When a block detection signal is supplied is either one of the detected block memory circuits 123.sub.a -123.sub.e, a block presence signal AB representing that there is a block in which the operated keyswitch has been detected is sent out to the state control circuit 105. When supplied with a first stage signal ST.sub.1 from the state control circuit 105, each one of the detected block memory circuits 123.sub.a -123.sub.e stores the block detectionsignal. Each one of the block preference gate circuits 124.sub.a -124.sub. e is constituted by an OR gate circuit 132, inverters 133 and 134 and AND gate circuits 135-137, and whenever a block detection signal is being stored in anyone of the detectedblock memory circuits 123.sub.a -123.sub.e the OR gate circuit 132 of the block preference circuit 124.sub.e sends to the state control circuit 105 a memory block signal MB which represents that a block detection signal is now being stored. Furthermore,each time a second state signal ST.sub.2 is applied, the memory contents of the detected block memory circuits 132.sub.a -132.sub.c are sequentially read out in accordance with a predetermined order of preference (in this embodiment, from 124.sub.a to124.sub.e) and the read out block detection signal are supplied to a block code transmission circuit 126 at which these signals are encoded. Then the encoded signals are sent out via OR gate circuits 138.sub.a -138.sub.c as three bit block codes BC. Each one of the signal transmission lines 125.sub.a -125.sub.e is constituted by a transistor 139 which is turned ON by the fourth state signal ST.sub.0 for discharging the line capacitance C.sub.b of the block wiring lines B.sub.1 -B.sub.5 and twocomplementary transistors 140 and 141 which are connected to ground the block wiring lines B.sub.1 -B.sub.5 only when the block detection signals are sent out from the detected block preference circuits 124.sub.a -124.sub.e but to connect the blockwiring lines B.sub.1 -B.sub.5 to a source V.sub.DD where the block detection signals are not sent out.
C. State Control Circuit 105
As shown in FIG. 10, the state control circuit 105 is constituted by two delay flip-flop circuits 142 and 143, inverters 144 and 145, AND gate circuits 146-153, and OR gate circuits 154 and 155, and constructed to produce control signals ST.sub.1-ST.sub.0 for detecting first to fourth states as shown in Table 1 thereby completing the detection of the operated key switches. The output signals Q.sub.1 and Q.sub.2 of the delay flip-flop circuits 142 and 143 show the operation states underexecution.
TABLE 1 ______________________________________ State Q.sub.1, Q.sub.2 Q.sub.1 Q.sub.2 ______________________________________ First State (ST.sub.1) 1 0 Second State (ST.sub.2) 0 1 Third State (ST.sub.3) 1 1 Fourth State (ST.sub.0) 0 0 ______________________________________
Thus, various state signals ST.sub.1 -ST.sub.0 are generated in accordance with the outputs Q.sub.1 and Q.sub.2 of the delay flip-flop circuits 142 and 143. These flip-flop circuits are written with input signals by the clock pulse .phi..sub.Bshown in FIG. 5I and their contents are read out by the clock pulse .phi..sub.A shown in FIG. 5H so that the minimum interval of generating state signals ST.sub.1 -ST.sub.0 is equal to the period of the clock pulse .phi..sub.A. In other words, alloperations of the key coder 100 are synchronized by the clock pulse .phi..sub.A.
D. Sampling and Holding Circuit 106
As shown in FIG. 9, the sampling and holding circuit 106 is constructed such that the block codes BC sent from the block code transmission circuit 126 of the block detection circuit 104 shown in FIG. 8 are respectively stored in block codetemporary memory circuits 156-158 at the timings of the first and third state signals ST.sub.1 and ST.sub.3 supplied from the operation state control circuit 105. Each of the block code temporary memory circuits 156-158 comprises an AND gate circuit159, an OR gate circuit 160 and a delay flip-flop circuit 161 and stores block code BC each time the first and third state signals ST.sub.1 and ST.sub.3 are applied. The outputs of the block code temporary memory circuits 156-158 are applied to oneinputs of AND gate circuits 162-164 with the other inputs connected to receive the memory note signal MN supplied from the note detection circuit 103, so that the stored block codes BC are read out from the delay flip-flop circuits 165-167 in synchronismwith the note code NC each time the memory note signal MN is applied. Reading out operations of the block codes BC from the delay flip-flop circuits 165-167 are synchronized by the clock pulse .phi..sub.B. The sampling and holding circuit 106 issupplied with note code NC from the note detection circuit 103. The note code NC is written in delay flip-flop circuits 168-171 and the read out therefrom at the timing of the clock pulse .phi..sub.B. Thus, after being synchronized with the block codeBC, the note code is derive out as the note code. In the same manner, the fourth state signal ST.sub.0 generated by the state control circuit 105 is also stored in a delay flip-flop circuit 172 and then read out at the timing of the clock pulse.phi..sub.B. The purpose of an inverter 173 is to form a key code KC specific to the note signal CL in which the block code is forcibly changed to "0" "0" "0" at the time of sending out the note code CL.
E. Operation of Key Coder 100
The operation of the key coder 100 shown in FIGS. 6-10 will now be described in detail with reference to the waveforms shown in FIGS. 11A-11O. In describing the operation, it is assumed that keys corresponding to the notes B and A of blockU.sub.5 and the note B of block U.sub.3 are operated so that their key switches are closed.
As shown in FIGS. 11A and 11B when the clock pulses .phi..sub.A and .phi..sub.B shown in FIGS. 5H and 5I are applied to the delay flip-flop circuits 142 and 143 of the state control circuit 105 (FIG. 10) from the timing signal generator 800 shownin FIG. 3, these delay flip-flop circuits store the output signals from OR gate circuits 154 and 155, respectively, at the timing of the clock pulse .phi..sub.B and send out their outputs Q.sub.1 and Q.sub.2 at the timing of the clock pulse .phi..sub.A. For example, it is assumed not that when the state control circuit 105 is in the fourth state ST.sub.0, that is the waiting state at a time t.sub.1 shown in FIG. 11A, then the outputs Q.sub.1 and Q.sub.2 from the delay flip-flop circuits 142 and 143 willbe "0" and "0" respectively as shown in Table 1 so that the outputs of the inverters 144 and 145 will be "1" and " 1". Accordingly, AND gate circuit 151 is enabled to produce a signal "1" which is applied to the input of the delay flip-flop circuit 142via OR gate circuit 154. At the same time, as shown in FIG. 11.sub.c, the fourth state signal ST.sub.0 (waiting state) is sent out through AND gate circuit 151. This fourth state signal ST.sub.0 is applied to respective signal transmission circuits125.sub.a -125.sub.e of the block detection circuit 104 (FIG. 8) thereby turning ON transistors 139 of the signal transmission circuits 125.sub.a -125.sub.e with the result that the wiring line capacitances C.sub.b of respective block wiring linesB.sub.1 -B.sub.5 are discharged.
When clock pulse .phi..sub.B is generated during times t.sub.1 and t.sub.2 as shown in FIG. 11A, the outputs of the OR gate circuits 154 and 155 are stored respectively in the delay flip-flop circuits 142 and 143 of the state control circuit 105shown in FIG. 10. At this time, since the output of only OR gate circuit 154 is "1", the delay flip-flop circuits 142 and 143 store "1" and "0" respectively. When the clock pulse .phi..sub.A is generated at time t.sub.2 shown in FIG. 11A, the memoriesstored in the delay flip-flop circuits 142 and 143 are read out. As a consequence, their outputs Q.sub.1 and Q.sub.2 become "1" and "0" with the result that AND gate circuit 152 produces the first state signal ST.sub.1 shown in FIG. 11D which is appliedto respective signal transmission lines 109.sub.a -109.sub.m of the note detection circuit 103 shown in FIG. 7 thus turning ON transistors 102 of these signal transmission lines. When transistors 112 are turned ON, voltage V.sub.DD is applied to keyswitch circuit 102 via note input/output terminals 108.sub.a -108.sub.m thus charging all capacitances C.sub.n of the note wiring lines N.sub.1 -N.sub.13.
When these capacitance C.sub.n are charged, a signal is produced on the block wiring line B of block U to which an operated key switch among all key switches 101.sub.a -101.sub.n belongs to charge the capacitance C.sub.b of the block wiring lineB. Thus, a block containing the operated key is detected depending upon whether the charged capacitance belongs to which block, whereby a detection signal is applied to the block input/output terminal 106' corresponding to the detected block U. Thisdetection signal is also applied to the corresponding detected block memory circuit 123 of the block detection circuit 104 shown in FIG. 6. When a block detection signal is applied to any one of the detected block memory circuits 123.sub.a -123.sub.e, ablock presence signal AB shown in FIG. 11G is sent to the state control circuit 105 via OR gate circuit 131. The block presence signal AB represents that there is a block in which an operated key switch has been detected and its value increases as thewiring line capacitance C.sub.n of the note wiring line N.sub.1 -N.sub.13 increases when the first state signal ST.sub.1 is sent out. One inputs of the AND gate circuits 128 of the detected block memory circuits 123.sub.a -123.sub.e are connected to theblock input/output terminals 106'.sub.a -106'.sub.e, respectively, to receive the block detection signals while the other inputs are connected to receive the first state signal ST.sub.1. Consequently, in the first state, only in the detected blockmemory circuit 123 corresponding to block U in which an operated key switch has been detected, signal "1" is stored in the delay flip-flop circuit 130 via AND gate circuit 128 and OR gate circuit 129. For example when the operated key switches aredetected in blocks U.sub.5 and U.sub.3 a block detection signal "1" is stored in the delay flip-flop circuits 130 of the detected block memory circuits 123.sub.a and 123.sub.c. The above described operation is executed while the clock pulse .phi..sub.Ais being produced as the first state operation.
When a block presence signal AB which represents that there is an operated key switch is produced, this block presence signal AB is applied to one input of the AND gate circuit 150 of the state control circuit 105 shown in FIG. 10. When appliedwith the block presence signal AB, the state control circuit 105 judges that there is a block in which the presence of an operated key switch has been detected thus proceeding to the control of the second state. More particularly, when a block presencesignal AB is applied, since inverters 144 and 145 producing signal "1", the AND gate circuit 150 is enabled to produce signal "1" which is applied to the delay flip-flop circuit 143 via OR gate circuit 155. As a consequence, signals "0" and "1" arestored in the delay flip-flop circuits 142 and 143 respectively at a time t.sub.3 shown in FIG. 11A and signals "0" and "1" are read out at time t.sub.4 by the clock pulse .phi..sub.A. The "0" and "1" outputs of the delay flip-flop circuits 142 and 143are in the second state as shown in Table 1. Then the AND gate circuit 153 of the state control circuit 105 generates the second state signal ST.sub.2 as shown in FIG. 11E. At this time, the delay flip-flop circuits 130 of the delay detection circuits123.sub.a and 123.sub.c are storing block detection signals "1" as above described so that these delay flip-flop circuits 130 apply signal "1" to one inputs of the OR gate circuits of corresponding block preference gate circuits 124.sub.a and 124.sub.c. The outputs of the OR gate circuits of respective block preference gate circuits 124.sub.a -124.sub.e are connected to the inputs of the OR gate circuits of the block preference gate circuits 124.sub.b -124.sub.e sequentially at lower orders, so that solong as at least one of the detected block memory circuit 123.sub.a -123.sub.e is storing a block detection signal, the OR gate circuit 132 of the block preference gate circuit 124.sub.e of block U.sub.1 at the lowest order of preference sends out asignal "1" shown in FIG. 11H which acts as a memory block signal MB showing that there is a memory block. This memory block signal MB is applied to one inputs of AND gate circuits 146, 148 and 149 of the state control circuit 105. Consequently,substantially concurrently with the generation of the second state signal ST.sub.2 ' the AND gate circuit 146 is enabled whereby another second state signal ST.sub.2 ' will be generated. In this manner, when signals "0" and "1" of the delay flip-flopcircuits 142 and 143 are read out by the clock pulse .phi..sub.A at time t.sub.4 shown in FIG. 11A, second state signals ST.sub.2 and ST.sub.2 ' are generated thus controlling the second state.
In the second state, a single memory block among a plurality of memory blocks is extracted in accordance of an order of preference predetermined by the block preference gate circuits 124.sub.a -124.sub.c. In FIG. 4, the order of preference isset in the order of blocks U.sub.5, U.sub.4 . . . , U.sub.1. In the block preference gate circuit 124.sub.a of block U.sub.5 at the highest order, the output of the inverter 133 is normally "1", so that as soon as the block detection signal "1" isapplied from the delay flip-flop circuit 130 of the detected block memory circuit 123.sub.a, AND gate circuit 135 is enabled. The outputs from the delay flip-flop circuits of the detected block memory circuits 123.sub.a -123.sub.e of the blocks U.sub.5-U.sub.1 at higher orders are sequentially applied to the block preference gate circuits 124.sub.b -124.sub.e regarding the blocks U.sub.4 -U.sub.1 at lower orders via OR gate circuits 132 of the block preference gate circuits 124.sub.a -124.sub.eregarding blocks U.sub.5 -U.sub.1. Accordingly, when the detected block memory circuits 123.sub.a -123.sub.d of the blocks U.sub.5 -U.sub.2 at upper orders store block detection signals, a signal "0" is applied to one inputs of AND gate circuits 135 viainverters 133 of the block preference gate circuits 124.sub.b -124.sub.e regarding blocks U.sub.4 -U.sub.1 at lower orders whereby the AND gate circuits 135 are disabled to establish a preference connection. Consequently only one AND gate circuit 135 ofthe block preference gate circuits 124.sub.a -124.sub.e produces signal "1". Where detection of the operated key switches is memorized in blocks U.sub.5 and U.sub.3, signal "1" is produced from only the AND gate circuit 135 of the block preference gatecircuit 124 regarding the block U.sub.5 during the interval of the second state ST.sub.2 shown by time t.sub.4 in FIG. 11A. Since the AND gate circuit 135 of the other block preference gate circuits 124.sub.b -124.sub.e is supplied with "1" output(which is inverted by inverter 133) of the OR gate circuit 132 of the block preference gate circuit 124.sub.a regarding block U.sub.5, due to the preferential operation on described above, the outputs of the AND gate circuits 135 of the other blockpreference gate circuits 124.sub.b -124.sub.e regarding the other blocks U.sub.4 -U.sub.1 are all "0". The AND gate circuit 137 is enabled when the outputs of the AND gate circuits 135 of the block preference gate circuits 124.sub.a -124.sub.e and thesecond state signal ST.sub.2 are applied to the inputs, and the output of the AND gate circuit 137 is applied to the transistors 140 of the signal transmission circuits 125.sub.a -125.sub.3 and the block code transmission circuit 126. The inputs ofrespective AND gate circuits 136 are connected to receive the second stage signal ST.sub.2 and the outputs of the AND gate circuits 135 which are inverted by inverters 134.
At time t.sub.4 shown by FIG. 11A, the second state signal ST.sub.2 (FIG. 11E) produced by the state control circuit 105 is applied to the inputs of the AND gate circuits 136 and 137 of respective preference gate circuits 136 and 137 while theother second stage signal ST.sub.2 ' is applied to the detected note memory circuits 110.sub.a -110.sub.m of the note detection circuit 103.
Consequently, during an interval t.sub.4 -t.sub.6, that is the interval in which the second state signal ST.sub.2 is generated, the output of only AND gate circuit 137 of the block preference gate circuit 124.sub.a becomes "1" and the outputs ofthe AND gate circuits 137 of the other block preference gate circuit 124.sub.b -124.sub.e are all "0". In this manner, the memory of only block U.sub.5 is read out and the read out signal is applied to the block code transmission circuit 126 and to thetransistors 140 of the signal transmission circuits 125.sub.a. The output of the AND gate circuit 137 of the block preference gate circuit 124.sub.a is inverted by the inverter 126' of the detected block memory circuit 123 and the inverted outputdisables the AND gate circuit 127. Accordingly, the memory of the delay flip-flop circuit 130 of the detected block memory circuit 123.sub.a is erased. However, since the outputs of the AND gate circuits 137 of the other block preference gate circuits124.sub.b - 124.sub.e are "0" signals "1" are applied to the inputs of the AND gate circuits 127 of the detected block memory circuits 123.sub.b -123.sub.e through inverters 126 so that the output of the delay flip-flop circuit 130 is maintainedunchanged. Thus, the memory contents of the blocks U.sub.4 -U.sub.1 are held continuously.
The output of the AND gate circuit 135 of the block preference gate circuit 124.sub.a regarding block U.sub.5 is "1" and this "1" signal is applied to one input of AND gate circuit 136 via inverter 134. Accordingly, the AND gate circuit 136 willnot be enabled by the "0" output of inverter 134 even when the second state signal ST.sub.2 is applied to the other input. On the other hand, the AND gate circuits 136 of the other blocks U.sub.4 -U.sub.1 are enabled by the "1" signals obtained byinverting the "0" outputs of the AND gate circuits 135 and the second state signal ST.sub.2, thereby producing an outputs "1" which are used to turn ON transistors 141 of the signal transmission circuits 125.sub.b -125.sub.e.
As above described, in the signal transmission circuit 125.sub.a of block U.sub.5, transistor 140 is turned ON while transistor 141 is turned OFF thus applying ground potential to the block input/output terminal 106'.sub.a. In the signaltransmission circuits 125.sub.b -125.sub.e of the blocks U.sub.4 -U.sub.1, transistors 140 are turned OFF while transistors 141 are turned ON. Accordingly, voltage V.sub.DD is applied to block input/output terminals 106'.sub.b -106'.sub.e regardingblocks U.sub.4 -U.sub.1 via transistor 141 thus charging the capacitance C.sub.b of the block wiring lines B.sub.2 -B.sub.5 of the key switch circuit 102 shown in FIG. 6. Then the diodes 107 connected to the key switches 101 included in blocks U.sub.4-U.sub.1 are reversely biased so that the key switches 101 included in the blocks U.sub.4 -U.sub.1 will be electrically isolated from the note wiring lines N.sub.1 -N.sub.13. However, since the potential of the block input/output terminal 106'.sub.a ofthe block U.sub. 5 is reduced to the ground potential the capacitance C.sub.b of the block wiring wires B.sub.1 will be discharged, thus rendering conductive the diode 107 connected to the operated key switch 101 of block U.sub.5. At this time, keyswitches 101 of block U.sub.5 correspond to tone notes C, B, . . . C.music-sharp. respectively and since the capacitances C.sub.n of respective note wiring lines N.sub.1 -N.sub.12 have already been charged in the first state, the charges of thecapacitances of the note wiring lines N.sub.1 -N.sub.12 corresponding to the operated key switches will discharge through a circuit of diode 107 key switch 101 block input/output terminal 106'.sub.a and transistor 140 of the block preference gate circuit125.sub.a. In block U.sub.5, for example, when it is now assumed that the key switches of notes B and A are closed, then the charges of the capacitances of the wiring lines N.sub.2 and N.sub.4 of notes B and A are discharged whereas the capacitancesC.sub.n of the other wiring lines N.sub.1, N.sub.3, N.sub.5 -N.sub.13 maintain their charges. Consequently, signals "0" are applied to the inputs of inverters 113 of the detected note memory circuits 110.sub.b and 110.sub.d from the note input/outputterminals 108.sub.b and 108.sub.d whereas signal "1" are applied to the inputs of inverters 113 from the other note input/output terminals 108.sub.a, 108.sub.c, 108.sub.e -108.sub.m. In this manner, signal "0" is applied from the block input/outputterminal 106'.sub.a of the extracted block U.sub.5 to either one of the note input/output terminals 108.sub.a -108.sub.e corresponding to the operated key switch of the extracted block U.sub.5, thus judging that the operated key switch corresponds to aspecific note.
In the detected note memory circuits 110.sub.a -110.sub.m the signals applied through note input/output terminals 108.sub.a -108.sub.m are inverted by inverters 113 and then applied to one inputs of respective AND gate circuits 115. Since theother inputs of the AND gate circuits 115 and applied with the second state signal ST.sub.2 ' which is generated by the state control circuit 105 shown in FIG. 10, signal "1" is stored in the delay flip-flop circuits 117 via AND gate circuits 115 and ORgate circuits 116 in the detected note memory circuits 110.sub.b and 110.sub.d corresponding to the notes B and A which are detected when the other second state signal ST.sub.2 ' is executed by the operations described above.
The reason that the other second state signal ST.sub.2 ' is used for storing the note signal in the detected note memory circuit 110.sub.a -110.sub.m instead of the second state signal ST.sub.2 is to positively store the detected note in theblock detection circuit 104 only when a memory block is available (when the memory block signal MB is "1") and to inhibit to store a new memory in the third state as will be described later.
The second state described above completes within the period of one clock pulse (.phi..sub.A), and at the next time t.sub.6 (FIG. 11A) the delay flip-flop circuits 117 of the detected note memory circuits 110.sub.b and 110.sub.d parallellyproduce signals "1" which are applied to the note preference circuits 111.sub.b and 111.sub.d. At this time t.sub.6, the third state ST.sub.3 ' is executed.
In the third state, signal note is derived out from the stored note signals according to a predetermined order of preference of the note preference gate circuits 111.sub.a -111.sub.m. In the note preference gate circuits 111.sub.a -111.sub.mshown in FIG. 7, the order of preference is set in the order of notes C, B, . . . C.music-sharp. and CL. Like the block preference gate circuits 124.sub.a -124.sub.e described above, in the note preference gate circuits 111.sub.a -111.sub.m, a signal"0" is normally applied to the inverter 120 of the note preference gate circuit 111.sub.a of the most significant note C so that the output of the inverter 120 is normally "1". When this signal "1" is applied to the flip-flop circuit 117 of the defectednote memory circuit 110.sub.a the AND gate circuit 121 will be enabled at once. The outputs of the delay flip-flop circuits of the note preference gate circuits 111.sub.a -111.sub.1 regarding the notes C - C.music-sharp. at the upper orders are appliedto one inputs of the AND gate circuits at lower orders via OR gate circuits 119 whereas the outputs of the delay flip-flop circuits 117 of the note preference gate circuits 111.sub.b -111.sub.m regarding the notes B-CL at lower orders are applied to theother inputs of the AND gate circuits 121 thereby disabling the same. The outputs of the delay flip-flop circuits 117 of the detected note memory circuits 110.sub.a -110.sub.m are supplied to one inputs of the AND gate circuits 114 thereof whereas theoutputs of the delay flip-flop circuits 117 of the detected note memory circuits 110.sub.a -110.sub.l regarding the notes C,C.music-sharp. at the higher orders of preference are sequentially applied via OR gate circuits 119 to the other inputs of theAND gate circuits 114 of the detected note memory circuits 110.sub.b -110.sub.m at lower orders. The AND gate circuit 114 of the detected note memory circuit 109.sub.a at the highest order is normally supplied with signal "0" so as to self-hold thememory of the delay flip-flop circuit 117 of the detected note memory circuit 110.sub.a. The circuit is constructed such that the memories of the delay flip-flop circuits 110.sub.b -110.sub.m at lower orders are self-held by the signals "1" sent fromthe delay flip-flop circuits 110.sub.a of the detected note memory circuits at higher orders.
Consequently, at time t.sub.6 shown in FIG. 11A, that is at a time when the third state signal ST.sub.3 is generated, the note preference gate circuit 111.sub.b of note B produces an output signal "1" which is applied to the note codetransmission circuit 122. At this time, the outputs of the other note preference gate circuits 111.sub.a, 111.sub.c -111.sub.m are all "0". When time t.sub.8 (see FIG. 11A) is reached the memory of the detected note memory circuit 110.sub.b is erasedand the output of the delay flip-flop circuit 117 thereof becomes "0" with the result that the detected note memory circuit 110.sub.d of note A applies signal "1" to the note code transmission circuit 122 via the note preference gate circuit 111.sub.d. When the next clock pulse is generated at time t.sub.10 the memory of the detected note memory circuit 110.sub.d will be erased.
As above described when the read out operations of all detected note signals are completed, the memory note signal MN produced by the OR gate circuit 111.sub.m regarding the note at the lowest order changes to "0" at time t.sub.12 as shown inFIG. 11H. This change of from "1" to "0" of the memory note signal MN means completion of the contents of the detected note memory circuits 110.sub.a -110.sub.m.
As above described, in the third state, the memories of the notes B and A are continuously read out during an internal of clock pulses (two clock periods) corresponding to the number of notes (in this example A and B) stored in the detected notememory circuits 110.sub.a through 110.sub.m.
Transistors 112 provided for the signal transmission circuits 109.sub.a -109.sub.m are connected to be turned ON when applied with either one of the first state signal ST.sub.1 and the third state signal ST.sub.3 so that in this embodiments thesum of the first and third state signals (ST.sub.1 +ST.sub.3) is used to drive transistor 112 without preparing a specific third state signal.
Considering now the conditions contributing to the third state, it is essential that the state preceding one clock pulse is at the second state or at the third state. In the state control circuit 105 shown in FIG. 10, output signal Q.sub.2 ofthe delay flip-flop circuit 143 is applied to one inputs of AND gate circuits 147-149. The fact that this signal Q.sub.2 is "1" means that the present state is the second state or the third state as can be noted from Table 1. Under these conditions,the block detection circuit 104 applies to one input of AND gate circuit 149 a memory block signal MB which shows the presence of an available memory block, and the note detection circuit 103 applies to the other input of the AND gate circuit 149 a notepresence signal AN which shows that there is a note signal required to be stored, whereby the AND gate circuit 149 is enabled to apply signal "1" to the delay flip-flop circuit 142. Whenever AND gate circuit 149 is enabled the AND gate circuit 148 isalso enabled so that signal "1" is applied to the delay flip-flop circuit 142. As a result, the inputs to the delay flip-flop circuits 142 and 143 becomes "1" so that after one clock pulse both outputs Q.sub.1 and Q.sub.2 becomes "1" thus establishingthe third state shown in Table 1. For this reason, a case wherein both outputs Q.sub.1 and Q.sub.2 are "1" shows that the third state is now being executed. Where the note presence signal AN is still generated after the state has changed to the thirdstate, the output of the AND gate circuit 147 becomes "1" which is applied to the delay flip-flop circuits 142 and 143 thus changing their outputs Q.sub.1 and Q.sub.2 to "1" to continue reading out of the stored notes by maintaining the third state. Where the output Q.sub.1 of the delay flip-flop circuit 142 is "1", the state is either the first or third state so that this signal is applied to transistor 112 of the note detection circuit 103 (FIG. 7) to act as the sum of the first and third statesignals (ST.sub.1 +ST.sub.3). When the AND gate circuit 148 of the state control circuit 148 of the state control circuit 105 shown in FIG. 10 is enabled whereas AND gate circuit 149 is not enabled, in other words, where the note presence signal AN fromthe note detection circuit 103 disappears at a time when the memory block signal MB is being supplied from the block detection circuit 104, it is judged that the extraction of the memory note of the extracted block has been completely thereby proceedingto the extraction of the next block and the note thereof. More particularly, when the output "1" of the AND gate circuit 148 is applied to the delay flip-flop circuit 143 via OR gate circuit 155 the outputs Q.sub.1 and Q.sub.2 of the delay flip-flopcircuits 142 and 143 are changed to "0" and "1" respectively for generating the second state signal thereby proceeding to the second state.
When such control is effected, during a interval between t.sub.6 to t.sub.10 (FIG. 11A) the third state is repeatedly processed and when all memory notes of the detected note memory circuits 110.sub.a -110.sub.m have been extracted the notepresence signal AN produced by the OR gate circuit 118 shown in FIG. 5 becomes "0". This means that the third state with reference to one block has terminated. Consequently, if any memory block is still remaining in the block detection circuit 104,(the memory block signal MB produced by the OR gate circuit 132 of the block detection circuit 104 shown in FIG. 8 is "1" the state control circuit 105 must repeat the control of the second state for extracting the next memory block thereby extracting anote corresponding to an operated key switch corresponding thereto. Accordingly, where only the AND gate circuit 148 of the state control circuit shown in FIG. 10 is enabled, the state control circuit 105 is returned to the second state by applying theoutput signal "1" of the AND gate circuit 148 to the delay flip-flop circuit 143 via OR gate circuit 155 whereby the second state signals ST.sub.2 and ST'.sub.2 are generated for controlling the second state in the same manner as above described. Sincein this case the note B of block U.sub.3 is not yet extracted (still remaining) the state is returned to the second state from the third state at time t.sub.10 as shown in FIGS. 11E and 11F. As shown in FIG. 11K, the memory block U.sub.3 is extracted bythe second state signal ST.sub.2 at times t.sub.10 and t.sub.12 shown in FIG. 11E. As shown in FIG. 11K, the memory block U.sub.3 is extracted by the second state signal ST.sub.2 at times t.sub.10 and t.sub.12, FIG. 11E. At the next clock pulse thestate is again proceeded to the third state as shown by times t.sub.12 and t.sub.14 shown in FIG. 11F, thus extracting the note of the operated key switch of block U.sub.3. Accordingly, note B during an interval of t.sub.12 -t.sub.14 (FIG. 11L) isextracted. By repeating the operation described above all of the memory blocks stored in the block detection circuit 104 and the memory note stored in the note detection circuits 103 are extracted. Then, all of the clock presence signal AB, memoryblock signal MB, note presence signal AN, and memory note signal MN become "0". Consequently, AND gate circuits 147-151 of the state control circuit 105 shown in FIG. 10 are all disabled with the result that the signals supplied to the delay flip-flopcircuits 142 and 143 become "0". Then, during the next clock cycle the outputs Q.sub.1 and Q.sub.2 become "0" thereby proceeding to the fourth state shown in Table 1, that is the waiting state. Consequently the fourth state signal ST.sub.0 turns ONtransistor 139 of the block detection circuit 104 whereby the block wiring lines B.sub.1 -B.sub.5 are grounded to reset the key switch circuit system.
In the above described operation, when the state is switched to the second state during an interval t.sub.4 -t.sub.6 shown in FIG. 11A, the block preference gate circuit 124.sub.a of the block detection circuit 104 produces signal "1" which isapplied to the block code transmission circuit 126 to be converted into a block code BC which represents the block code U.sub.5. More particularly, when the output signal from the block preference gate circuit 124.sub.a is applied to the block codetransmission circuit 126, OR gate circuits 138.sub.a -138.sub.c produce signals "1", "0" and "1" respectively between t.sub.4 and t.sub.6 as shown in FIG. 11K which constitute the block code BC representing the block U.sub.5. In this case, the circuitis constructed such that when the block preference gate circuits 124.sub.a -124.sub.e regarding blocks U.sub.5 -U.sub.1 produce outputs the block code transmission circuit 126 produces block codes as shown in the following Table 2.
TABLE 2 ______________________________________ block block code (BC) ______________________________________ U.sub.5 101 U.sub.4 100 U.sub.3 011 U.sub.2 010 U.sub.1 001 ______________________________________
In the foregoing description, notes B and A included in the block U.sub.5 were sequentially extracted between t.sub.6 and t.sub.10 as shown in FIG. 11F. The extraction signal of note B at a higher order of preference is firstly applied to thenote code transmission circuit 122 from the note preference gate circuit 111.sub.b of the note code detection circuit 103, shown in FIG. 7 as signal "1". In response to this signal, OR gate circuits 123.sub.a -123.sub.d produce signals "1", "1", "0" and"1" respectively between t.sub.6 and t.sub.8 as shown in FIG. 11L which constitute the note code NC representing note B. When the note preference gate circuit 111.sub.d applies its output signal to the note code transmission circuit 122 at the next clockpulse, OR gate circuits 123.sub.a -123.sub.d produce outputs "1", "0", "1" and "0" respectively between t.sub.8 and t.sub.10 as shown in FIG. 11L which constitute a note code NC representing note A.
Similar to the block code transmission circuit 126 of the block detection circuit 104 described above when the note preference gate circuits 111.sub.a -111.sub.m of the note detection circuit 103 produce outputs, the note code transmissioncircuit 122 will produce note codes NC as shown in the following Table 3.
TABLE 3 ______________________________________ note note code (NC) ______________________________________ C 1110 B 1101 A# 1100 A 1010 G# 1001 G 1000 F# 0110 F 0101 E 0100 D# 0010 D 0001 C# 0000 CL 1110 ______________________________________
As shown in FIGS. 11K and 11L, the block detection circuit 104 and the note detection circuit 103 extract an encoded memory block at the highest order of preference (in this example block U.sub.5) at the second state thereby proceeding to thethird state at the next clock pulse .phi..sub.A. At the third state, the stored notes (that is notes B and A) included in the previously extracted block U.sub.5 are sequentially encoded and extracted. When the extraction of the stored notes completes,the state proceeds to the fourth state (waiting state) or returns to the second state. The fourth and second states are selected in accordance with the presence or absence of the memory block. Where the memory block U.sub.3 is still remaining as abovedescribed, the state is returned to the second state thus extracting block U.sub.3 as shown in FIG. 11K. When block U.sub.3 is extracted the state is again proceeded to the third state by the next clock pulse .phi..sub.A, thus extracting the memory noteB as shown in FIG. 11L. These operations are repeated until all of the memory blocks and the memory notes are extracted, and when such extraction is completed the state is advanced to the fourth state (waiting state). By repeating these operations(first to fourth states) blocks and notes containing operated key switches are sequentially encoded and extracted.
However, the block code BC and the note codes NC produced by the block detection circuit 104 and the note detection circuit 103 are generated at different times as shown in FIGS. 11K and 11L, so that if they are applied to the circuits on thelater stages without any modification difficulties would be resulted. For this reason, the block codes BC and the note codes NC are supplied to the sampling and holding circuit 106 shown in FIG. 9 so as to match their generating timings for combiningthem into a key code which is supplied to the circuits on the later stages. The sampling and holding circuit 106 also functions to form a special block code BC for the note CL.
The detail of the sampling and holding circuit 106 will be described hereunder with reference to FIG. 9.
When the block code transmission circuit 126 shown in FIG. 6 produces a block code BC consisting of three bits KB.sub.1, KB.sub.2 and KB.sub.3 and representing the block U.sub.5 at time t.sub.4 as shown in FIG. 11K, respective bits KB.sub.1-KB.sub.3 of the block code BC are applied to the block code temporary memory circuits 156, 157 and 158 of the sampling and holding circuit 106. Respective block code temporary memory circuits 156-158 store respective bits KB.sub.1 -KB.sub.3 in thedelay flip-flop circuits 161 via OR gate circuits 160 at the timing of the clock pulse .phi..sub.B. When the next clock pulse .phi..sub.A is supplied, the memory contents of the delay flip-flop circuits 161 are read out and supplied to one inputs of ANDgate circuits 162-164. The output signals of respective delay flip-flop circuits 161 are applied to the inputs thereof via AND gate circuits 159 and OR gate circuits 160.
During an interval in which the AND gate circuits 159 are enabled, that is under the first and third states, the outputs of the delay flip-flop circuits 161 are applied to the inputs thereof. Writing by clock pulse .phi..sub.A and reading out ofthe stored signals by clock pulse .phi..sub.B, one clock later than .phi..sub.B, are continued to self-hold the memories. In this manner, the bits KB.sub.1, KB.sub.2 and KB.sub.3 of the block code BC are stored in block code temporary memory circuits156, 157 and 158, respectively. Accordingly, the block code BC which represents block U.sub.5 is held during the third state. Each output signal of the block code temporary memory circuits 156, 157, 158 is applied to each of inputs of AND gate circuits162-164, so that when the memory note signal MN is applied to the other inputs from the note detection circuit 103, AND gate circuits 162-164 are enabled. In other words, when the memory note signal MN that represents that the note detection circuit 103contains a memory note is applied, the AND gate circuits 162-164 acting as the block code output gate circuits produce the memory output signals of the block code temporary memory circuits 156-158 and these output signals are applied to the delayflip-flop circuits 165-167. As a consequence, AND gate circuits 162-164 acting as the block code output gate circuits continue to produce the block code BC of the block U.sub.5 as shown in FIG. 11M only during the interval in which the memory notescontained in block U.sub.5 are extracted. Consequently, block codes BC are obtained during the interval of generating the note codes NC shown in FIG. 11L and the codes NC and BC are generated synchronously. When extraction of the memory notes B and Acontained in block U.sub.5 is completed, the memory note signal MN becomes "0" so that AND gate circuits 162-164 are disabled thus interrupting the sending out of the block code BC representing the block U.sub.5 which is stored in the block codetemporary memory circuits 156-158. When the memory note signal MN becomes "0" when the memory block signal MB is "1" or under a condition in which a memory block presents the state control circuit 105 shown in FIG. 10 returns to the second state. As aconsequence, AND gate circuits 159 are disabled to clear the contents of the block code temporary memory circuits 156-158. The block codes BC sent out from AND gate circuits 162 through 164 are applied to the delay flip-flop circuits 165-167respectively and send out therefrom as block codes BC at the timing of clock pulse .phi..sub.B as shown in FIG. 11N. The note codes NC produced by the note code transmission circuit 122 are applied to respective delay flip-flop circuits 168-171 fromwhich they are sent out as note code outputs NC at the timing of the clock pulse .phi..sub.B as shown in FIG. 11D. Consequently, the block code outputs BC produced by the sampling and holding circuit 106 and representing block U.sub.5, and the note codeoutputs NC representing the notes B and A contained in this block are produced at the same timing or synchronously. Each three bit block code BC and four bit note code NC are combined to form a key code KC of the parallel seven bits construction. Forthis reason, each seven bit key code KC represents one of the operated key switches. Where keys corresponding to note B of block U.sub.5 are operated, as can be noted from Tables 2 and 3, block code BC is expressed by "101" whereas the note code NC by"1101" and the seven bit key code KC obtained by combining them is expressed by a code "101 1101". The sampling and holding circuit 106 sequentially performs contained in this block is extracted and supplied to respective delay flip-flop circuits of thesampling and holding circuits 168-171 and then sent out therefrom at the timing of clock pulse .phi..sub.B. The block codes BC stored in the block code temporary memory circuit 156-158 are supplied to respective delay flip-flop circuits 165-167 by thememory note signal MN and then produced therefrom at the timing of clock pulse .phi..sub.B thus synchronized with the note code NC. Accordingly, the sampling and holding circuit 106 produces a seven bit key code "011 1101" representing the note B ofblock U.sub.3. When the operations described above are completed the signals of all operated key switches (in this examples three key switches) are converted into corresponding key codes KC which are detectable digitally.
In addition to the operation of forming the seven bit key codes KC in synchronism with the generation of the block codes BC and the note codes NC, the sampling and holding circuit 106 also forms a special block code BC for note CL.
Inherently the note CL is contained in a block different from block U.sub.1, but for the convenience of grouping the key switch circuit 101, the note CL is included in block U.sub.1. For this reason, it is necessary to make block code BC of noteCL to be different from the block code BC of block U.sub.1. For the reason described above, where a signal is obtained from note CL, a special block code BC is purposely generated for forming a key code KC representing note CL. This special block codeBC is generated in the following manner. More particularly, when a key switch corresponding to the note CL is depressed, since it is included in block U.sub.1, the block code transmission circuit 126 produces a block code "001" that represents blockU.sub.1 which is stored in the block code temporary memory circuit 158 of the sampling and holding circuit 106. On the other hand, in the note detection circuit 103, AND gate circuit 121 of the note preference gate circuit 111.sub.m produces an outputsignal at the third state. This output signal is converted into a note code "1110" representing note CL in the note code transmission circuit 122. The signal CL produced at this time by the AND gate circuit 121 of the note preference gate circuit111.sub.m is inverted by inverter 173 of the sampling and holding circuit 106 and the output of the inverter disables the AND gate circuit 162. As a consequence the "1" signal of above described block code "001" representing block U.sub.1 is inhibitedby AND gate circuit 162 so that the block code "001" is forcibly converted into "000". In this example, since a code "000" is not assigned to blocks U.sub.1 -U.sub.5 this code "000" becomes the sixth block code BC, which is sent out only when key switch101.sub.m corresponding to note CL is operated so that this block code BC serves to discriminate the note C from note CL which are assigned in duplicate to note C. The flip-flop circuit 172 provided for the sampling and holding circuit 106 is used toproduce a start signal X, one clock pulse delayed, by producing signal ST.sub.O by the state control circuit 105 at the timing of clock pulse .phi..sub.B, and to supply the start signal X to a key ON-OFF detection circuit 202 to be described later.
Above description regards the detail of the operation of key coder 100 which detects operated keys and generates key codes KC corresponding thereto.
Channel Processor 200
The detail of the construction and operation of the channel processor 200 will now be described with reference to FIGS. 12-15 which are connection diagrams showing one examples of first key code memory circuit 201, key ON-OFF detection circuit202, truncate circuit 203 and depressed key state memory circuit 204 which constitute the channel processor 200.
A. Key Code Memory Circuit 201
The first key code memory circuit 201 shown in FIG. 12 comprises a plurality of shift registers 205.sub.a -205.sub.g for respective bits KN.sub.1 -KB.sub.3 of a key code KC, the number of the stages (memory positions) of each shift register beingequal to the number of the musical tones that can be produced at the same time, that is the number of channels (in this embodiment, 8 channels). These shift registers 205.sub.a -205.sub.g are driven by a two phase clock pulse comprising a clock pulse.phi..sub.1 shown in FIG. 5A and a clock pulse .phi..sub.2 having an opposite phase with respect to the clock pulse .phi..sub.1 so as to sequentially shift their contents. The outputs produced by the last stages of the shift registers are fed back totheir inputs through AND gate circuits 206.sub.a -206.sub.g and OR gate circuits 207.sub.a -207.sub.g respectively. For this reason, these shift registers cooperate to constitute a 8 stage 7 bit circulating shift register having a number of stagescapable of storing key codes of the same number as the channels, and comprising parallel bits. To the inputs of respective shift registers are applied key codes KC each consisting of bits .[.KN.sub.1 -NB.sub.3 .]. .Iadd.KN.sub.1 -K[N]B.sub.3 .Iaddend. via AND gate circuits 208.sub.a -208.sub.g and OR gate circuits 207.sub.a -207.sub.g. Consequently, each time a set signal which is produced corresponding to channels not yet assigned with key codes is impressed upon line 209 from key ON-OFF detectioncircuit 202, the AND gate circuits 208.sub.a -208.sub.g are enabled to apply respective bit signals KN.sub.1 -KB.sub.3 of the key codes KC in the shift registers 205.sub.a -205.sub.g and the same key code KC is written and held in the stages ofrespective shift registers corresponding to the channels not yet assigned with the key codes. The fact that which key code KC(KN.sub.1 -KB.sub.3) is assigned to which channel can be judged by the output timings of the shift registers driven by clockpulses .phi..sub.1 and .phi..sub.2 because clock pulses .phi..sub.1 and .phi..sub.2, and channels which are assigned with the key codes on the time division basis are synchronous. Accordingly, the stored key codes KC assigned to respective channels arederived out sequentially on the time division basis at each channel time shown in FIG. 5B, and the derived out key codes are sequentially applied to a key code converter 300 (to be described later) via output terminals 210.sub.a -210.sub.g and are alsofed back to the inputs of respective shift registers to be feld therein. An initial clear signal IC is supplied to one input of the OR gate circuit 207.sub.g to write signal "1" in the shift registers at the timing of the initial clear signal IC. Tothe other inputs of the AND gate circuits 206.sub.a -206.sub.g are applied the output of a NAND gate circuit 209'. The inputs of this NAND gate circuit 209' are connected to receive a set signal supplied from the key ON-OFF detection circuit 202 to bedescribed later via line 209 and the initial clear signal IC.
B. Key ON-OFF Detection Circuit 202
The key ON-OFF detection circuit 202 shown in FIGS. 13A and 13B comprises a key code comparator circuit 211 which compares the stored key codes KC derived out from shift registers 205.sub.a -205.sub.g of the first key code memory circuit 211 withkey codes KC newly applied to the shift registers. The stored key codes corresponding to respective | | | |
