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Row grabbing system |
| RE32326 |
Row grabbing system
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| Patent Drawings: | |
| Inventor: |
Nagel, et al. |
| Date Issued: |
January 6, 1987 |
| Application: |
06/496,273 |
| Filed: |
May 19, 1983 |
| Inventors: |
Nagel; Robert H. (New York, NY)
Saylor; Richard (Monsey, NY)
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| Assignee: |
IRD, Inc. (Farmingdale, NY) |
| Primary Examiner: |
Masinick; Michael A. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Stiefel, Gross, Kurland & Pavane |
| U.S. Class: |
348/463; 348/464; 348/466; 348/478 |
| Field Of Search: |
358/83; 358/141; 358/903 |
| International Class: |
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| U.S Patent Documents: |
3369073; 3488435; 3602891; 3609227; 3647949; 3649749 |
| Foreign Patent Documents: |
2058681 |
| Other References: |
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| Abstract: |
A real time frame grabbing system for substantially instantaneously providing a continuous video display or a selectable predetermined video frame of information on a video display means from continuously transmittable video information which is transmitted as a plurality of pseudo video scan lines wherein the selected frame being grabbed is updatable on a displayable row by displayable row basis. Each of the pseudo video scan lines has a television scan line format and comprises a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, the pseudo video scan line having an associated transmission time equivalent to that of a television video scan line. The packet of digital information comprises at least address information for a displayable row and data information for the displayable characters in the row. Each of these psuedo video scan lines further comprises a horizontal sync signal at the beginning thereof which provides a record separator between adjacent pseudo video scan lines and resets the input receiver logic for the transmitted pseudo video scan lines upon the detection of each horizontal sync signal to provide noise immunity enhancement. The pseudo video scan lines are transmitted and received through a conventional television distribution system. Each pseudo video scan line contains means for error checking the contents of the received pseudo video scan line for inhibiting display of the associated displayable row when the error check is not satisfied. Programmable means, such as a general purpose digital computer, is conventionally programmed to interleave the pseudo video scan line signal transmission to provide pseudo video scan line information corresponding to a common assigned row for a plurality of frames before providing such information corresponding to a subsequent different common assigned row for the plurality of frames. |
| Claim: |
What is claimed is:
1. A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a videodisplay means from continuously transmittable video information comprising means for transmitting said video information as a plurality of pseudo video scan lines, each of said pseudo video scan lines having a television video scan line format andcapable of comprising a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, said pseudo video scan line having an associated transmission time equivalent to said television videoscan line, said packet of digital information comprising at least address information for said displayable row and data information for said displayable characters in said displayable row, each of said pseudo video scan lines further comprising ahorizontal sync signal at the beginning thereof, said horizontal sync signal providing a record separator between adjacent pseudo video scan lines, said transmitting means further comprising means for providing a vertical sync signal after apredetermined plurality of pseudo video scan lines have been transmitted, said pseudo video scan line being a composite video signal, said system further comprising television signal distribution means for distributing said transmitted composite pseudovideo scan line signals to said video display means for providing said continuous video display.[...]..Iadd., and receiver means operatively connected between said television signal distribution means and said video display means for processing saiddistributed composite pseudo video scan line signals and capable of providing a displayable video row signal to said video display means from a pseudo video scan line signal pertaining to said selected frame for providing said continuous video display,said receiver means comprising means for updating said continuously video displayable selectable frame on a displayable video row-by-row basis as said data portion of any of said displayable received distributed pseudo video scan line signals pertainingto said selected frame is updated. .Iaddend.
2. A real time frame grabbing system in accordance with .[.claim.]. .Iadd.claims 1 or 28 .Iaddend.wherein said composite pseudo video scan line signal provided by said transmitting means comprises a three level signal having first, second andthird signal levels with said digital data information varying between said second and third signal levels and said horizontal sync signal information being provided between said first and second signal levels.
3. A real time frame grabbing system in accordance with .[.claim.]. .Iadd.claims 1 or 28 .Iaddend..[.further comprising receiver means operatively connected between said television signal distribution means and said video display means forprocessing said distributed composite pseudo video scan line signals and.]. .Iadd.wherein said processing means comprises means .Iaddend.capable of providing a displayable video row signal to said video display means from each of said pseudo video scanline signals pertaining to said selected frame for providing said continuous video display, a predetermined plurality of displayable video rows comprising a displayable video frame of information.
4. A real time frame grabbing system in accordance with claim 3 wherein said composite video scan line signal further comprises clock signal reference frequency information, said receiver signal processing means comprising means for providing amaster clock signal output in accordance with said reference frequency information and a predetermined data bit rate, and decoder means operatively connected to said master clock signal output for providing timing control signals for said receiver signalprocessing means indicative of predetermined character positions within said pseudo video scan line signal and predetermined bit positions within a character for processing said distributed pseudo video scan line to provide said displayable video rowsignal therefrom.
5. A real time frame grabbing system in accordance with claim 3 wherein said receiver signal processing means comprises means responsive to the occurrence of said horizontal sync signal for each distributed pseudo video scan line for resettingsaid processing means in response to each detection of said horizontal sync signal, whereby noise immunity for said system is enhanced.
6. A real time frame grabbing system in accordance with claim .[.3.]. .Iadd.1 .Iaddend.wherein said .[.receiver.]. .Iadd.updating .Iaddend.means comprises means for updating said continuously video displayable selectable frame on a displayablevideo row-by-row basis dependent on the real time data information content of said received pseudo video scan .[.lines.]. .Iadd.line. .Iaddend.
7. A real time frame grabbing system in accordance with claim .[.6.]. .Iadd.1 .Iaddend.wherein said updating means comprises memory means for retrievably storing said continuously distributed pseudo video scan line data portion for providingsaid displayable video row therefrom, said memory means retrievably stored data portion being continuously updateable as said data portion of said pseudo video scan line signal associated therewith is updated.
8. A real time frame grabbing system in accordance with claim .[.3.]. .Iadd.1 or 28 .Iaddend.wherein each of said packets of digital information further comprises an error check information content based on at least the address and datainformation content of an associated pseudo video scan line, said receiver signal processing means comprising error check means for obtaining an error check indication from said distributed associated pseudo video scan line and comparing said error checkindication with said error check information content of said associated pseudo video scan line in accordance with a predetermined error check condition for providing a predetermined output condition signal when said error check condition is satisfied,said receiver signal processing means further comprising condition responsive means operatively connected to said error check means to receive said predetermined output condition signal therefrom when provided, said condition responsive means inhibitingthe provision of said displayable video row from said associated pseudo video scan line signal when said predetermined output condition signal is not provided thereto. .[.9. A real time frame grabbing system in accordance with claim 8 wherein saidreceiver means comprises means for testing said address information portion of said distributed pseudo video scan line signal for satisfaction of at least one predetermined signal reception condition, said address information testing means providing apredetermined output condition when said reception condition is satisfied, memory means for retrievably storing said pseudo video scan line data portion for providing said displayable video row therefrom and delay means for delaying the storing of saiddistributed pseudo video scan line signal data portion for a sufficient interval to enable testing for said error check condition and testing of said address information prior to storing of said pseudo video scan line data portion, said conditionresponsive means being further operatively connected to said address information testing means for inhibiting the storage of said data portion in said memory means when said predetermined output condition signals from said testing means are not providedthereto, whereby the provision of said displayable video row from
said associated pseudo video scan line signal is inhibited..]. 10. A real time frame grabbing system in accordance with claim .[.9.]. .Iadd.1 .Iaddend.wherein said receiver means further comprises keyboard means for selecting saidpredetermined video frame to be continuously displayed, said address information comprising information corresponding to the frame associated with said distributed pseudo video scan line, said address information testing means comprising means fortesting said frame information, said reception condition being correspondence between said frame information and said selected frame. .[.11. A real time frame grabbing system in accordance with claim 9 wherein a predetermined pseudo video scan linesignal contains permission information representative of predetermined frames which a video display means is authorized to receive for video display thereof, said receiver means comprising means for storing said authorized frames, said addressinformation comprising information corresponding to the frame associated with said distributed pseudo video scan line, said address information testing means comprising means for testing said frame information, said reception condition beingcorrespondence between said frame information and stored authorized
frame..]. 12. A real time frame grabbing system in accordance with claim .[.1.]. .Iadd.28 .Iaddend.wherein said system further comprises programmable means for receiving said continuously transmittable video information, retrievably storingsaid information, reformatting said stored information into a desired pseudo video scan line format and continuously providing this reformatted information to said transmitting means a word at a time, said word comprising a pair of displayablecharacters. .[.13. A real time frame grabbing system in accordance with claim 12 wherein said programmable means includes means for interleaving said reformatted pseudo video scan line information to provide pseudo video scan line informationcorresponding to a common assigned row for a plurality of frames to said transmitting means before providing pseudo video scan line information corresponding to a subsequent different common assigned row for said plurality of frames to said transmittingmeans..].
. A real time frame grabbing system in accordance with claim 12 wherein said transmitting means comprises a first-in-first-out serial word memory means having a storage capacity of a predetermined plurality of words operatively connected to saidprogrammable means for receiving said reformatted information word transmission therefrom, and means for controlling the strobing of data out of said first-in-first-out memory means operatively connected to said first-in-first-out memory means, saidprogrammable means controlling the strobing of data into said
first-in-first-out memory means. 15. A real time frame grabbing system in accordance with claim 14 wherein said transmitter means comprises a master clock signal generation means for controlling the bit rate of transmission of said pseudovideo scan line signals, bit counting means operatively connected to said master clock signal generation means for counting said clock signal and providing an output pulse each time said bit count corresponds to a predetermined common quantity of bits ina displayable character, said output pulse representing the start of said character, means for generating a composite sync signal and vertical drive signal, said master clock signal generation means synchronizing said bit rate with said composite syncsignal, means operatively connected to said sync signal generation means for providing a frame enable signal at a predetermined vertical scan position after said vertical drive signal, said means for controlling the strobing of data out of saidfirst-in-first-out memory means capable of receiving a ready to transmit data signal from said first-in-first-out memory means and comprising condition responsive means operatively connected to said sync signal generating means for receiving saidcomposite sync signal therefrom, said bit counting means for receiving said output pulse therefrom, said frame enable signal providing means for receiving said frame enable signal therefrom and said first-in-first-out memory means for receiving saidready to transmit data signal therefrom for controlling said strobing of data out from said first-in-first-out memory means in response to said received signals for providing said data information portion for one of
said pseudo video scan line signals. 16. A real time frame grabbing system in accordance with claim 15 wherein said transmitter means further comprises sync combining means operatively connected to said first-in-first-out memory means forreceiving said one pseudo video scan line signal data information portion and to said sync signal generating means for receiving said composite sync signal therefrom for providing said composite pseudo video scan line signal to said distribution means.
. A real time frame grabbing system in accordance with claim 16 wherein said transmitter means further comprises a shift register means operatively connected between said first-in-first-out memory means output and said sync combining meansinput, said shift register means further being operatively connected to said bit counting means output and said master clock signal generating means output for loading said one pseudo video scan line signal data portion from said first-in-first-outmemory means into said shift register means in response to said bit counting means output pulse, said shift register means shifting out said loaded one pseudo video scan line signal data portion for providing said data portion to said sync combiningmeans at a shift rate established by said master
clock signal. 18. A real time frame grabbing system in accordance with claim 17 wherein said transmitter means further comprises flip-flop means and character counting means having its input connected to said bit counting means output forclocking said character counting means in response to said bit counting means output pulse for providing an output pulse when a quantity of bit counting means output pulses corresponding to a predetermined total number of characters comprising one pseudovideo scan line signal has been counted for establishing a time period corresponding to said total number of characters, said character counting means output being connected to said flip-flop means for receiving said character counting means output pulseand providing a sync burst gate signal output in response thereto, said flip-flop means being further operatively connected to said sync signal generating means for receiving said composite sync signal, said flip-flop means being set by said charactercounting means output pulse and reset by said composite sync signal, said transmitter means further comprising a selectable multiplexer means having a first input operatively connected to said shift register means output and a second input operativelyconnected to said master clock signal generating means output for providing a clock synchronizing burst signal thereto and further being connected to said flip-flop means output for switching between said first and second inputs in response thereto, saidmultiplexer means output being connected to said sync combining means input for selectively providing said first and second inputs thereto, said clock synchronizing burst signal being selected during the interval of said sync burst gate signal, saidshift register means output being selected when said sync burst gate signal output is not provided and said shift register means output is provided, said composite pseudo video scan line signal further comprising said clock synchronizing burst signal for
an interval corresponding to said sync burst gate interval. 19. A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a videodisplay means from a plurality of pseudo video scan lines, each of said pseudo video scan lines having a television video scan line format and capable of comprising a complete self-contained packet of digital information sufficient to provide an entiredisplayable row of video data characters, said pseudo video scan line having an associated transmission time equivalent to said television scan line, said packet of digital information comprising at least address information for said displayable row anddata information for said displayable characters in said displayable row, each of said pseudo video scan lines further comprising a horizontal sync signal at the beginning thereof, said horizontal sync signal providing a record separator between adjacentpseudo video scan lines, said pseudo video scan line being a composite video signal, said system comprising means for selecting said predetermined video frame to be continuously displayed and means operatively connected to said video display means andsaid frame selection means for processing said composite pseudo video scan line signals and capable of providing a displayable video row signal to said video display means from each of said pseudo video scan line signals pertaining to said selected framefor providing said continuous video display, a predetermined plurality of displayable video rows comprising a displayable video frame of information.[...]..Iadd., said processing means comprising means for updating said continuously video displayableselectable frame on a displayable video row-by-row basis as said data portion of any of said displayable received distributed pseudo video scan line signals pertaining
to said selected frame is updated. .Iaddend. 20. A real time frame grabbing system in accordance with claim 19 .Iadd.or 29 .Iaddend.wherein said processing means comprises means responsive to the occurrence of said horizontal sync signal foreach pseudo video scan line for resetting said processing means in response to each detection of said horizontal sync
signal, whereby noise immunity for said system is enhanced. 21. A real time frame grabbing system in accordance with claim 19 .Iadd.or 29 .Iaddend.wherein said composite pseudo video scan line signal further comprises clock signal referencefrequency information, said processing means comprising means for providing master clock signal output in accordance with said reference frequency information and a predetermined data bit rate, and decoder means operatively connected to said master clocksignal output for providing timing control signals for said processing means indicative of predetermined character positions within said pseudo video scan line signal and predetermined bit positions within a character for processing said distributedpseudo video scan line to
provide said displayable video row signal therefrom. 22. A real time frame grabbing system in accordance with claim 19 wherein said .[.processing.]. .Iadd.updating .Iaddend.means comprises means for updating said continuously videodisplayable selectable frame on a displayable video row-by-row basis dependent on the real time data information content of
said received pseudo video scan lines. 23. A real time frame grabbing system in accordance with claim .[.22.]. .Iadd.19 .Iaddend.wherein said updating means comprises memory means for retrievably storing said pseudo video scan line dataportion for providing said displayable video row therefrom, said memory means retrievably stored data portion being continuously updateable as said data portion of said pseudo video scan
line signal associated therewith is updated. 24. A real time frame grabbing system in accordance with claim 19 .Iadd.or 20 .Iaddend.wherein each of said packets of digital information further comprises an error check information content basedon at least the address and data information content of an associated pseudo video scan line, said processing means comprising error check means for obtaining an error check indication from said distributed associated pseudo video scan line and comparingsaid error check indication with said error check information content of said associated pseudo video scan line in accordance with a predetermined error check condition for providing a predetermined output condition signal when said error check conditionis satisfied, said processing means further comprising condition responsive means operatively connected to said error check means to receive said predetermined output condition signal therefrom when provided, said condition responsive means inhibitingthe provision of said displayable video row from said associated pseudo video scan line signal when said predetermined output condition signal is not provided thereto. .[.25. A real time frame grabbing system in accordance with claim 24 wherein saidprocessing means comprises means for testing said address information portion of said distributed pseudo video scan line signal for satisfaction of at least one predetermined signal reception condition, said address information testing means providing apredetermined output condition when said reception condition is satisfied, memory means for retrievably storing said pseudo video scan line data portion for providing said displayable video row therefrom and delay means for delaying the storing of saiddistributed pseudo video scan line signal data portion for a sufficient interval to enable testing for said error check condition and testing of said address information prior to storing of said pseudo video scan line data portion, said conditionresponsive means being further operatively connected to said address information testing means for inhibiting the storage of said data portion in said memory means when said predetermined output condition signal from said testing means are not providedthereto, whereby the provision of said displayable video row from said associated pseudo video
scan line signal is inhibited..]. 26. A real time frame grabbing system in accordance with claim .[.24.]. .Iadd.29 .Iaddend.wherein said selection means comprises keyboard means, said address information comprising information correspondingto the frame associated with said pseudo video scan line, said address information testing means comprising means for testing said frame information, said reception condition being correspondence between said frame information and said selected frame. .[.27. A real time frame grabbing system in accordance with claim 25 wherein a predetermined pseudo video scan line signal contains permission information representative of predetermined frames which a video display means is authorized to receive forvideo display thereof, said processing means comprising means for storing said authorized frames, said address information comprising information corresponding to the frame associated with said pseudo video scan line, said address information testingmeans comprising means for testing said frame information, said reception condition being correspondence between said frame information and stored
authorized frame..]. .Iadd.28. A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a video display means from continuouslytransmittable video information comprising means for transmitting said video information as a plurality of pseudo video scan lines, each of said pseudo video scan lines having a television video scan line format and capable of comprising a completeself-contained packet of digital information sufficient to provide an entire displayable row of video data characters, said pseudo video scan line having an associated transmission time equivalent to said television video scan line, said packet ofdigital information comprising at least address information for said displayable row and data information for said displayable characters in said displayable row, each of said pseudo video scan lines further comprising a horizontal sync signal at thebeginning thereof, said horizontal sync signal providing a record separator between adjacent pseudo video scan lines, said transmitting means further comprising means for providing a vertical sync signal after a predetermined plurality of psuedo videoscan lines have been transmitted, said pseudo video scan line being a composite video signal, said system further comprising television signal distribution means for distributing said transmitted composite pseudo video scan line signals to said videodisplay means for providing said continuous video display and programmable means for receiving said continuously transmitted video information, retrievably storing said information, reformatting said stored information into a desired pseudo video scanline format and continuously providing this reformatted information to said transmitting means, said programmable means including means for interleaving said reformatted pseudo video scan line information corresponding to a common assigned row for aplurality of frames to said transmitting means before providing pseudo video scan line information corresponding to a subsequent different common assigned row for said plurality of frames to said transmitting means. .Iaddend. .Iadd.29. A real timeframe grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a video display means from a plurality of pseudo video scan lines, each of said pseudo video scanlines having a television video scan line format and capable of comprising a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, said pseudo video scan line having an associatedtransmission time equivalent to said television scan line, said packet of digital information comprising at least address information for said displayable row and data information for said displayable characters in said displayable row, each of saidpseudo video scan lines further comprising a horizontal sync signal at the beginning thereof, said horizontal sync signal providing a record separator between adjacent pseudo video scan lines, said pseudo video scan line being a composite video signal,said system comprising means for selecting said predetermined video frame to be continuously displayed and means operatively connected to said video display means and said frame selection means for processing said composite pseudo video scan line signalsand capable of providing a displayable video row signal to said video display means from each of said pseudo video scan line signals pertaining to said selected frame for providing said continuous video display, a predetermined plurality of displayablevideo rows comprising a displayable video frame of information, said processing means comprising means for updating said continuously video displayable selectable frame on a displayable video row-by-row basis as said data portion of any of saiddisplayable received distributed pseudo video scan line signals pertaining to said selected frame is updated, a predetermined pseudo video scan line signal containing permission information representative of predetermined frames which a video displaymeans is authorized to receive for video display thereof, said processing means comprising means for storing said authorized frames and for testing said address information portion of said distributed pseudo video scan line signal for satisfaction of atleast one predetermined signal reception condition, said address information testing means providing a predetermined output condition signal when said reception condition is satisfied, said processing means further comprising condition responsive meansoperatively connected to said address information testing means for inhibiting the storage of said distributed pseudo video scan line signal data portion in said authorized frame storing means when said predetermined output condition signal is notprovided thereto from said testing means, said address information comprising information corresponding to the frame associated with said distributed pseudo video scan line, said address information testing means comprising means for testing said frameinformation, said reception condition being correspondence between said frame information and stored authorized frame, whereby the provision of said displayable video row from said associated pseudo video scan line is inhibited in the absence ofauthorization for display thereof. .Iaddend. .Iadd.30. A real time frame grabbing system in accordance with claim 8 wherein said receiver means further comprises memory means for retrievably storing said pseudo video scan line data portion forproviding said displayable video row therefrom and delay means for delaying the storing of said distributed pseudo video scan line signal data portion for a sufficient interval to enable testing for said error check condition and testing of said addressinformation prior to storing of said pseudo video scan line data portion. .Iaddend.
.Iadd.31. A real time frame grabbing system in accordance with claim 24 wherein said processing means further comprises memory means for retrievably storing said pseudo video scan line data portion for providing said displayable video rowtherefrom and delay means for delaying the storing of said distributed pseudo video scan line signal data portion for a sufficient interval to enable testing for said error check condition and testing of said address information prior to storing of saidpseudo video scan line data portion. .Iaddend. |
| Description: |
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to video communication systems in which individual frames may be grabbed for video display thereof.
2. Description of the Prior Art
Video communication systems in which individual frames may be grabbed for video display are well known, such as the system disclosed in U.S. Pat. No. 3,740,465, or a system employing the Hitachi frame grabbing disc. These prior art systemssuch as the one disclosed in U.S. Pat. No. 3,746,780 are normally two-way request response systems requiring the user to request information by the dialing of a specific digital code which is uniquely assigned to each frame. However, such systemsnormally grab a group of frames for storage and then subsequently select the individual frame for display out of the group of grabbed frames as opposed to instantaneously selecting a single frame in real time. Furthermore, such prior art systems do notprovide for real time updating of the grabbed video frame. Furthermore, some such prior art frame grabbing systems, such as the type disclosed in U.S. Pat. No. 3,397,283 are normally capable of only grabbing the next immediate signal in response tothe provision of a starter signal or, as disclosed in U.S. Pat. No. 3,051,777, utilize a counter for frame location which must be reset to the beginning of a tape for video tape supplied information in order to locate a selected frame to be grabbed. These systems are not applicable in a real time frame grabbing environment. Similarly, other typical prior art frame grabbing systems, such as disclosed in U.S. Pat. Nos. 3,695,565; 2,955,197; 3,509,274; 3,511,929 and 3,582,651 can not be utilized ina real time frame grabbing environment, such as one in which the video information associated with the grabbed frame is capable of being continuously updated. Accordingly, presently available prior art frame grabbing systems familiar to the Inventorsare not capable of easily locating a frame to be grabbed in real time nor of being able to continuously update such a grabbed frame in real time.
Video communication systems in which the signal being transmitted is digitized are also well known. For example, U.S. Pat. No. 3,743,767 discloses a video communication system for the transmission of digital data over standard televisionchannels wherein the digital data is transmitted in a conventional television scan line format through conventional television distribution equipment. However, such prior art communication system merely digitizes one television scan line at a time fordistribution to a video display terminal on a bit-by-bit basis in a line, 84 bits of information being provided per television scan line. Furthermore, such a prior art system is not transmission selectable by every display terminal nor is the data for adisplayable video row packed into a self-contained pseudo video scan line information packet. Thus, there is no significant increase in the data transmission rate resulting from such a prior art video communication system. Similarly, U.S. Pat. Nos. 3,061,672 and 3,569,617 are examples of other prior art video communication systems in which television signals are digitized without any significant resultant compression in data transmission time. Furthermore, these other prior art systems requirespecial distribution circuitry. In addition, prior art video communication system in which a digital television signal is transmitted do not sufficiently isolate the individual rows comprising a frame so as to provide satisfactory noise immunity betweenthese rows, noise immunity at best being provided between frames, nor is there satisfactory data compression in the transmission time of the video information in such prior art systems.
These disadvantages of the prior art are overcome by the present invention.
SUMMARY OF THE INVENTION
A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a video display means from continuously transmittable video information, whereinsuch information is transmitted as a plurality of pseudo video scan lines is provided. Each of the pseudo video scan lines has a television video scan line format and comprises a complete self-contained packet of digital information sufficient toprovide an entire displayable row of video data characters, the pseudo video scan line having an associated transmission time equivalent to that of a television video scan line. The packet of digital information comprises at least address information,such as page, group, permission, user and direct address for a displayable row and data information for the displayable characters, such as 32 characters, in a displayable row. Each of the pseudo video scan lines further comprises a horizontal syncsignal at the beginning thereof, each horizontal sync signal providing a record separator between adjacent pseudo video scan lines as well as providing noise immunity on a row by row basis for resetting all the input logic in the receiver which processesthe transmitted signal every horizontal sync pulse. The transmitter for the pseudo video can line includes means for providing a vertical sync signal after a predetermined plurality of pseudo video scan lines have been transmitted, the pseudo video scanline being a composite video signal. These transmitted pseudo video scan line composite vieo signals are distributed through a conventional television distribution system, such as a cable distribution system, to various video display means for providinga continuous video display thereof. The receiver which is operatively connected between the distribution network and an associated video display means, processes the distributed composite pseudo video scan line signals and provides a displayable videorow to the associated video display means from each of the pseudo video scan line signals pertaining to the frame selected in order to provide the continuous video display, a predetermined plurality of displayable video rows comprising a displayablevideo frame of information. The receiver also preferably includes means for updating the continuously video displayable selectable frame on a displayable video row-by-row basis dependent on the real time data information content of the received pseudovideo scan line.
Each of the packets of digital information contained within the pseudo video scan line, also preferably includes an error check information content based upon at least the address and data information content of the associated pseudo video scanline, the receiver including error check means for obtaining an error check indication of the distributed associated pseudo video scan line and comparing the error check indication with the error check information content of the associated pseudo videoscan line in accordance with a predetermined error check condition for providing a predetermined output condition when the error check condition is satisfied. The receiver also includes condition responsive means operatively connected to the error checkmeans for preventing the provision of the displayable video row from the associated pseudo video scan line when the predetermined output condition is not met.
The system also preferably includes programmable means, such as a general purpose computer, for receiving the continuously transmittable video information, retrievably storing the information, reformatting it into a desired pseudo video scan lineformat and continuously providing this reformatted information to the transmitter on a word-by-word basis, a word comprising a pair of displayable characters. Furthermore, the programmable means preferably includes means for interleaving the reformattedpseudo video scan line information to provide pseudo video scan line information corresponding to a common assigned row for a plurality of frames to the transmitter before providing pseudo video scan line information corresponding to a subsequentdifferent common assigned row for the plurality of frames to the transmitter. Thus, the provision of the pseudo video scan line enables the use of conventional television transmission techniques and equipment for transmission and reception as well asconventional television circuitry for processing the received and transmitted signals. Furthermore, by utilizing the horizontal sync as a record separator, one can insure that any loss of synchronization or noise pulse will not disrupt more informationthan one pseudo video scan line. In addition, significant data compression in transmission time is obtained by transmitting the pseudo video scan lines as opposed to conventional television scan lines, with each pseudo video scan line being a selfcontained packet of information sufficient for display of an entire displayable video row containing a plurality of conventional television scan lines, such as 13, as opposed to display of one television scan line.
In the present invention, frame grabbing is accomplished by preferably feeding the pseudo video scan line into a buffer storage for comparison with an information request from the .[.keyboarad.]. .Iadd.keyboard .Iaddend.which, if matched,updates the appropriate memory for display or selection control so that updating is, in reality, accomplished on a row-by-row basis as opposed to a page or frame-by-frame basis as new information is provided in real time, the selected frame beingautomatically updated in real time as new information is provided for a given row of the displayed selected frame.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a diagrammatic illustration of a typical pseudo video scan line format in accordance with the present invention;
FIG. 2 is a graphical illustration of conventional vertical drive and composite sync signals illustrating the origin of the vertical sync signal in accordance with the present invention;
FIG. 3 is a .[.blcok.]. .Iadd.block .Iaddend.diagram of the timing and keyboard control, memory input control and a part of the output processing portions of the preferred receiver of the present invention;
FIG. 4 is a block diagram of the phase locked loop portion of the arrangement illustrated in FIG. 3;
FIG. 5 is a block diagram of another portion of the memory input control portion of the preferred receiver of the present invention;
FIG. 6 is a block diagram of the memory and output processing portion of the preferred receiver of the present invention;
FIG. 6a is a graphical illustration of the timing associated with various signals in the arrangement of FIG. 6;
FIG. 7 is a block diagram of another portion of the memory and output processing portion of the preferred receiver of the present invention;
FIG. 8 is a logic diagram, partially in schematic, of a portion of the timing and keyboard control portion of the preferred receiver of the present invention illustrated in FIG. 3;
FIG. 9 is a logic diagram, partially in schematic, of the keyboard portion of the timing and keyboard control portion of the receiver illustrated in FIG. 3;
FIG. 10 is a logic diagram, partially in schematic, of the portion of the memory input control portion of the receiver illustrated in FIG. 5;
FIG. 11 is a logic diagram, partially in schematic, of the portion of the memory input control portion of the receiver illustrated in FIG. 6;
FIG. 12 is a logic diagram, partially in schematic, of the memory and output processing portion of the receiver illustrated in FIG. 3;
FIG. 13 is a logic diagram, partially in schematic, of another portion of the memory and output processing portion of the receiver illustrated in FIG. 7;
FIG. 14 is a block diagram of the preferred transmitter portion of the present invention;
FIG. 15 is a logic diagram of the first in-first out memory portion of the transmitter portion illustrated in FIG. 14;
FIGS. 16 and 17 are logic diagrams, partially in schematic of the transmitter portion illustrated in FIG. 14 except for the first in-first out memory portion illustrated in FIG. 15; and
FIG. 18 is a functional block diagram of the preferred embodiment of the row grabbing system of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
System General Description
Referring now to the drawings in detail and initially to FIG. 18 thereof, the preferred embodiment of the row grabbing system, generally referred to by the reference numeral 10, of the present invention is shown. As will be described in greaterdetail hereinafter, the row grabbing system 10 of the present invention is preferably a one-way frame grabbing system in which continuously transmitted information or messages are transmitted via pseudo video scan lines 12 (FIG. 1 and 2) on a row by rowbasis, with the pseudo video scan line 12 preferably being identical in format to a conventional video scan line, that is it is consistent with FCC and EIA standards for a video scan line signal format; however, this pseudo video scan line 12 actuallycontains a row of information, such as approximately between 11 and 13 actual television video scan lines of information, with the transmission time of the pseudo video scan line 12 preferably being equal to the transmission time of a conventional TVvideo scan line, which is approximately 63 microseconds. The various portions of the pseudo video scan line 12 will be described in greater detail hereinafter with reference to FIGS. 1 and 2. In the row grabbing system 10 of the present invention, theinformation is updated on a row by row basis by transmission of a pseudo video scan line containing new information so that the frame being grabbed will effectively have this row containing new information updated when this row of information is updatedin memory. In the preferred system 10 of the present invention, continuously transmitted information or messages may be instantaneously "grabbed" in real time so as to repetitively provide a video display of a selected video frame of such informationwhich may be updated on a row by row basis in real time.
Video information may be of any conventional type, such as news information, money rate information, stock market information, local advertising, television program listings, weather information, consumer information, etc., which isconventionally supplied from conventional external information sources for these types of information such as sources 2,002 and 2004 shown by way of example. These conventional external information sources 2,002 and 2,004 preferably conventionallysupply this information in a digital format, such as from a ticker for news information or stock information, by way of example, through a conventional communication line 2,006 or 2,008 or a conventional local video terminal, preferably, to aconventional mini computer 2000, such as a model number PDP-8e manufactured by Digital Equipment Corp. Mini-computer 2000 preferably has an associated conventional mass memory 2010 for conventional storage of data. Computer 2000 stores this informationin mass memory 2010, reformats it, such as by adding header information, and continuously provides this information as a 12 bit parallel output 2011 to a transmitter 20, to be described in greater detail hereinafter, which provides the pseudo video scanline 12 for transmission to the TV distribution network. It should be noted that at any time, the twelve bit parallel output of computer 2000 preferably represents two characters or one word. If desired, a 14 bit parallel bit output from the computer2000 could be utilized to provide two seven bit characters. Computer 2000 shall be described in greater detail hereinafter with reference to FIG. 14. The mass memory 2010 is preferably updated by the computer 2000 in conventional fashion at the optimumtransfer time for data which is, conventionally, not necessarily in the order of reception of the external information from sources 2002 and 2004, this data being preferably continuously suppliable in real time to the computer 2000. In conventionalfashion, the information in computer 2000 is supplied to transmitter 20 which, in turn, supplies this information to a CATV cable system 22 through a conventional RF modulator 24, composite video being supplied to modulator 24 from transmitter 20. Onesuch modulator 24 is preferably provided for each television channel on which information is to be transmitted, only one such channel being illustrated in FIG. 18 by way of example. Preferably, the mass memory 2010 which is read in conventional fashionby computer 2000 to provide the requisite information via transmitter 20 to the CATV cable system 22, has sufficient storage capacity to store the entire page capacity of the system.
As used hereinafter throughout the specification and claims the term page means one video frame of information, the term group means a predetermined number of pages, the term row is a displayable video row and means a portion of a page containinga plurality of conventional television video scan lines, and the term pseudo video scan line means a signal which is identical in form to that of a conventional video scan line but which actually contains a row of information, such as approximatelybetween 11 and 13 actual television video scan lines of information with the transmission time of the pseudo video scan line being equal to the transmission time of a conventional TV video scan line and with the pseudo video scan line being an entirepacket of information necessary for video display of that row. The term conventional or television video scan line is used in its conventional manner.
The mass memory 2010 may be any conventional mass memory storage device sufficient to store the requisite page capacity of the system, such as an RK-08 memory device manufactured by Digital Equipment Corp. The output of the computer 2,000 ispreferably conventionally transmitted from computer 2,000 to the transmitter 20 via a conventional data break of the computer 2,000. All pages of information are preferably continuously being transmitted from the computer 2000 through transmitter 20 ona pseudo video scan line by pseudo video scan line basis, that is respectively on a row by row basis, through the appropriate RF Modulator 24 for the video channel being utilized and, therefrom, through the CATV cable system 22 to conventional videodisplay terminals or devices 2013 and 2015, such as commercially available video monitors, two such devices being shown by way of example. It should be noted that the number of video display devices 2013 and 2015 preferably has no requisite correlationwith the number of .[.eternal.]. .Iadd.external .Iaddend.information sources 2002 and 2004 and more sources 2002 and 2004 could be utilized than video display devices 2013 and 2015 or vice versa, if desired. In normal contemplated use, the number ofvideo display devices 2013 and 2015 will normally exceed the number of external information sources 2002 and 2004, however, this need not be the case. The computer 2000 conventionally recirculates the data provided thereto in continuous fashion and, aspreviously mentioned, eventually updates the mass memory 2010 at the optimum transfer time for the data, which time is not necessarily in the order of reception of the external information from sources 2002 and 2004. The information from externalsources 2002 and 2004, which is preferably being provided substantially continuously to the computer 2000 (as long as it is being generated from the external sources 2002 and 2004) is provided to the mass memory 2010 and instantaneously to thetransmitter 20 which operates in a manner to be described in greater detail hereinafter to provide the pseudo video scan line 12 transmission of the information. As will also be described in greater detail hereinafter, each video display device 2013 and2015 preferably has an associated display control unit 25 and 26, respectively, which, as will be described in greater detail hereinafter, preferably functions to enable the real time frame grabbing or selection of a single page of continuouslytransmitted information for the instantaneous repetitive continuous video display, or frame grabbing, thereof, this information being updatable on a row by row basis in real time. Preferably, each of the display control units 25 and 26 by way ofexample, one such display control unit preferably being associated with each video display terminal or device, are identical in structure and operation. If desired, however, any display control unit 25-26 may be modified in a manner to be described ingreater detail hereinafter so as to prevent the reception of certain categories of information while enabling the reception of other categories of information. For purposes of clarity, only one such typical display control unit 25 will be described byway of example, the structure and operation, as previously mentioned, being identical with that of display control unit 26. Identical reference numerals, followed by the letter a will be utilized in FIG. 18 for elements of display control unit 26 whichare identical in structure and operation with those of display control unit 25. In the overall system block diagram of FIG. 18, the display control unit 25 only preferably contains a conventional RF demodulator 27, one such demodulator 27 being providedfor each channel and a receiver 28, to be described in greater detail hereinafter, which receiver receives the composite video demodulated by demodulator 27 and determines whether the user is correct, the user has permission to receive the pseudo videoscan line of information being transmitted at that time, whether the signal is error free, whether the page address of the pseudo video scan line is correct, and whether a direct address condition, to be described in greater detail hereinafter, exists,and, preferably assuming the pseudo video scan line signal passes all these tests, then the receiver processes this signal and provides a video signal corresponding to a displayable row of information on the video display device 2013. The keyboard whichaccomplishes the selection of the desired page or video frame of information and the appropriate group thereof to be grabbed or repetitively displayed on the video display terminal 2013 is included as part of the receiver portion 28 and will be describedin greater detail hereinafter as part of the receiver portion 28 of the system 10.
TRANSMITTER
General Description
Referring now to FIG. 14, initially, the transmitter portion 20 of the row grabbing system 10 of the present invention shall generally be described in greater detail. Thereafter, with reference to FIGS. 15, 16 and 17, the preferred transmitterportion 20 of the present invention shall be described in greater detail.
Computer 2000 which provides the 12 bit parallel output 2011 of data also provides a strobe command, as will be described in greater detail hereinafter, via path 2014, the strobe command on path 2014 and the 12 parallel lines of data 2011 beingpreferably loaded into a conventional FIFO word series memory, shown in greater detail in FIG. 15, which acts like a parallel shift register. FIFO memory 2016 preferably accepts information under command of the strobe line 2014 from computer 2000 andcan preferably store up to 64 words which is 128 characters of information, two characters of information comprising one word. Computer 2000 can .[.slo.]. .Iadd.also .Iaddend.preferably completely erase FIFO memory 2016 by the provision of a resetcommand via path 2018, as will be described in greater detail hereinafter. FIFO memory 2016 supplies a ready signal to computer 2000 via path 2020 which denotes that the input location of memory 2016 is empty. Computer 2000 only preferably strobes datainto FIFO memory 2016 if the ready line 2020 is asserted. It should be noted that preferably the inputting and outputting of memory 2016 are completely independent of each other.
The transmitter 20 preferably includes a conventional television sync generator 2022 which provides composite sync via path 2023 in accordance with EIA standards as well as vertical drive via path 2025. The timing of sync generator 2022 ispreferably controlled by conventional crystal controlled oscillator 2026, such as a 14.31818 megahertz crystal controlled oscillator, in conventional fashion. The transmitter 20 preferably requires a master clock to control the bit rate of transmission. This bit rate, which is preferably selected at 5.113657 megahertz, must preferably be synchronized with the composite sync. The data bit rate selected must be consistent with the broadcast television channel .[.band width.]. .Iadd.bandwidth.Iaddend.and must be an integral multiple of the horizontal frequency, which is necessary to keep the data bits phase locked with the horizontal sync signal. The 5.113657 megahertz clock, which shall be referred to as clock A, is preferably obtained bya conventional crystal controlled phase locked loop 2024 which is locked at 5/14 of the 14.31818 megahertz oscillator 2026 frequency through a divide-by-14/5 frequency divider 2028. The clock A output of phase locked loop 2024 is preferably divided by aconventional divide-by-seven bit counter 2030 in order to generate a pulse on line 2032 which represents the start of each character. This pulse is provided in parallel to a character counter 2034 which uses this signal as a clock input and preferablycounts up to 40, counter 2034 being a divide-by-40 counter, to establish the period corresponding to the 40 characters preferably contained within a single pseudo video scan line 12. The output of character counter 2034 is preferably a pulse on line orpath 2036 which occurs during the period of the 40th character. The trailing edge of the pulse present on path 2036 preferably sets a flip-flop 2038 which is reset by the composite sync provided via path 2023 from sync generator 2022. Thus, the outputof flip-flop 2038 is a gate which starts at the end of the 40th character and ends at the beginning of the horizontal sync pulse. During this gating time, it is preferably desired to transmit a burst of sync pulses which are identical to a stream ofalternate "0" and "1" data bits, this burst of sync pulses being located in region F (FIG. 1) of the pseudo video scan line 12, as will be described in greater detail hereinafter. This signal which is provided on line 2040 is termed the sync burst gateand is provided to a multiplexer 2042 as one input thereto, this input being the control or select input for multiplexer 2042.
One selectable input to multiplexer 2042 is provided from the output of a divide-by-2 flip-flop 2044 whose input is the clock A output of phase locked loop 2024. When the gating signal on path 2040 is high, multiplexer 2042 preferably selectsthis input signal from flip-flop 2044, which provides a square wave output at one-half the frequency of clock A, and applies this signal to the output data line 2046 of multiplexer 2042. The other selectable input to multiplexer 2042 preferably is theserial data output of a conventional parallel-to-serial shift register 2050 which receives the 12 parallel lines of data output from FIFO memory 2016. When the gate signal on path 2040 is low, multiplexer 2042 preferably selects the serial data line2048 output from shift register 2050 and applies this signal to the output data line 2046 of multiplexer 2042. Shift register 2050 is preferably a 14 line input parallel-to-serial shift register with two lines being grounded in the arrangemet to bedescribed by way of example. If 14 input data lines were utilized then these two grounded terminals will, of course, be respectively connected to the other two of the 14 data input lines. Shift register 2050 receives the 12 lines of data from FIFOmemory 2016 via path 2051, this data being loaded into shift register 2050 when a load command is received from bit counter 2030 on path 2032. Data is outputed from shift register 2050 as the serial data line 2048, the shift rate being preferablyestablished by clock A. Preferably, 14 clock pulses occur to shift out 14 bits of data from shift register 2050 for each word loaded into shift register 2050. The data output of multiplexer 2042 is preferably supplied to a conventional sync combiner2052 which also receives the composite sync signal via path 2023 from sync generator 2022.
The output of sync combiner 2052 is a conventional composite video signal format, which is a three level signal, the data varying between levels 2 and 3 corresponding to digital values of 0 and 1 and the sync being indicated by level 1, asillustrated in FIGS. 1 and 2, with FIG. 1 illustrating a typical pseudo video scan line signal 12 format. This composite video signal represents a single pseudo video scan line at a time as described and shown in FIGS. 1 and 2, computer 2000 beingconventionally programmed to control various locations or assignments in regions B through E of the pseudo video scan line, these regions to be described in greater detail hereinafter in the description of the receiver portion 28 of the row grabbingsystem 10. As was previously mentioned, region F of the pseudo video scan line 12 is provided on line 2040 as a sync burst gate provided to multiplexer 2042 and regions A and G are provided from the composite sync on path 2023.
The transmitter 20 also preferably includes a strobe control portion 2054 which contains all the logic for determining when the data should be strobed out of the FIFO memory 2016. It is most preferable that when data is shifted out of memory2016 and transmitted, that complete lines of 40 characters each are shifted, in the example given. If all conditions necessary for the transmission of 40 characters in a pseudo video scan line 12 are not met preferably an empty line, which is a pseudovideo scan line having only regions A,F and G occupied, is transmitted. It is further preferred that data be transmitted only during a selected portion of the television vertical frame so as to insure that only empty lines are transmitted during thevertical drive period. Strobe control portion 2054 preferably monitors the various conditions necessary and starts to issue a series of strobe out pulses on line 2056 only if the output of FIFO memory 2016 is ready as indicated on ready line 2058provided from memory 2016 to strobe control portion 2054, if the vertical scan position is correct as indicated by a signal present on line 2060 termed frame enable, to be described in greater detail hereinafter, and if a composite sync pulse has beenreceived from sync generator 2022 via path 2023. When all these conditions are met, the output of bit counter 2030 on line 2032 is allowed to control the strobing of FIFO memory 2016. The master reset pulse when issued or provided on line 2018 fromcomputer 2000 preferably prevents any new pseudo video scan line of data from being transmitted until all the above mentioned conditions are again met. The correct vertical scan position or frame enable signal provided via path 2060 is preferablyobtained from a decoder 2062 which decodes the output of a line counter 2064. Line counter 2064 counts the number of pseudo video scan lines after the vertical drive, the inputs to line counter 2064 being the vertical drive signal from sync generator2022 provided via path 2025 and the composite sync signal from sync generator 2022 provided via path 2023. This decoder 2062 preferably selects the group of lines which are used for transmission.
DETAILED DESCRIPTION OF TRANSMITTER
Referring now to FIGS. 15, 16 and 17, the transmitter portion 20 of the row grabbing system 10 of the present invention shall be described in greater detail, FIGS. 15 through 17 being logic schematics of appropriate portions of the transmitterportion 20, the balance of the transmitter portion 20 not illustrated in greater detail than in FIG. 14 being conventional. Accordingly, a more detailed description than previously provided will not be provided for those conventional portions notillustrated in greater detail in FIGS. 15 through 17 as they would readily be understood by one of ordinary skill in the art.
Referring initially to FIG. 15, the conventional FIFO memory 2016 is shown in greater detail. FIFO memory 2016 preferably comprises three conventional four bit-by-64 word FIFO serial memories 2070, 2072 and 2074, such as an MOS FIFO serialmemory of the type manufactured by Fairchild under designation 33414, each memory stage 2070, 2072 and 2074 receiving four of the 12 parallel bit data line outputs from computer 2000. The input ready and output ready lines are preferably combined byNAND gates 2076 for the input ready line to provide the input ready signal via path 2020 to computer 2000, and by NAND gate 2078 for the output ready line to provide the output ready signal via path 2058 to strobe control portion 2054.
Referring now to FIGS. 16 and 17, the balance of the transmitter portion 20 shall be described in greater detail, where appropriate, for purposes of clarity. Referring initially to FIG. 16, the television sync generator 2022, as previouslymentioned, is preferably a conventional MOS television sync generator such as the type manufactured by Fairchild under the designation 3261 and will not be described in any greater detail herinafter. Oscillator 2026, which supplies the clock signal tothe television sync generator 2022 for controlling the timing thereof and the reference frequency signal to the phase locked .[.group.]. .Iadd.loop .Iaddend.2024 .[.preferably.]., as previously mentioned, preferably comprises a conventional integratedcircuit oscillator 3000, such as the type manufactured by Motorola under the designation 4024, utilized with inverters 3002 to 3004 to provide the clock to sync generator 2022 at opposite phases as is conventionally required by a sync generator 2022 ofthe type previously described. In addition, oscillator 3000 is preferably crystal controlled by a conventional crystal 3006 at the oscillator frequency, such as the 14.31818 megahertz frequency chosen by way of example. The clock signal output ofoscillator 3000 is preferably applied via path 3010 to a conventional four bit binary counter 3008, such as the type manufactured by Texas Instruments under the designation SN 74161N, preferably connected as a divide-by-14 counter, counter 3008 forming aportion of the divide-by-14/5 divider network 2028. The output of counter 3008 is preferably connected as the clock input to a conventional divide-by-2 flip-flop 3012 also forming part of the divide-by-14/5 divider 2028. The output of the divide-by-2flip-flop 3012 is preferably connected to one input of phase locked loop 2024 which is preferably a conventional MOS phase locked loop, such as the type manufactured by Signetics under the designation NE562B. Thus, the total division ratio fromoscillator 2026 through phase locked loop 2024 is preferably 28-to-1. The output of phase locked loop 2024 provided via path 3014 is fed back to the input of a conventional four bit binary counter 3016, such as the type utilized for counter 3008,however counter 3016 preferably being connected as a divide-by-5 counter. The output of counter 3016 is preferably, in turn, connected to a conventional divide-by-2 flip-flop 3018, such as the type manufactured by Texas Instruments under designation SN7474N, whose output is in turn preferably connected to a second input of phase locked loop 2024. Accordingly, the total feed back path division ratio is preferably 10 and the phase locked loop 2024, accordingly, varies its output frequency provided viapath 3014 as necessary to keep its two inputs from flip-flop 3012 and flip-flop 3018 at exactly equal frequencies but with a phase difference of 90.degree.. As a result of the frequency division ratio utilized on each input path to phase locked loop2024, the phase locked loop output frequency is exactly preferably 5/14 of the frequency of oscillator 2026 which, by way of example, provides a clock A output frequency for phase locked loop 2024 of 5.1136357 megahertz as the output frequency of phaselocked loop 2024.
Bit counter 2030 which, as previously mentioned with reference to FIG. 14, preferably receives this clock A output frequency, is preferably a conventional divide-by-7 bit binary counter 3020, such as the type manufactured by Texas Instrumentsunder the designation SN74160N, counter 3020 which forms part of the bit counter network 2030 preferably being the actual bit counter. Two of the output lines of bit counter 3020 are preferably decoded by a conventional two input NAND gate 3022 toprovide a pulse at the third count of counter 3020, this pulse being provided as one input to a two input negative NAND gate 3082. The carry output from bit counter 3020 is preferably connected to the D input of a conventional D type flip-flop 3024whose clock input is preferably connected to the clock A output of phase locked loop 2024 provided via path 3014. This provides at the output of flip-flop 3024 a pulse at the completion of the divide-by-seven cycle of counter 3020 which pulse isutilized as the load input of the parallel-to-serial register 2050 provided via path 2032.
As was previously mentioned with reference to FIG. 14, the output of bit counter 2030 provided via path 2032 is also preferably provided to .[.charcter.]. .Iadd.character .Iaddend.counter 2034. As shown and preferred in FIG. 16, charactercounter 2034, which is preferably a divide-by-40 counter, comprises two counter stages 3026 and 3028 which are both conventional four bit decade or divide-by-10 counters, such as the type manufactured by Texas Instruments under the designation SN74160N. Each counter 3026 and 3028 is preferably clocked from the master clock A via path 3014 and is enabled by the carry output of bit counter 3020 via path 2032. Thus the counter stages 3026 and 3028 preferably increment only once per character. Thecharacter counter 2034 also preferably comprises a decoder which includes negative NAND gates 3030 and 3032, connected, respectively, to the outputs of counter stages 3026 and 3028, and a NAND gate 3034 whose inputs are the outputs of gates 3030 and3032. The decoder formed by gates 3030, 3032 and 3034 preferably generates a negative pulse on the 40th count from counter stages 3026 and 3028 of counter 2034. As shown and preferred, counter stages 3026 and 3028 are cleared by the composite syncsignal provided from sync generator 2022. The composite sync output of sync generator 2022, as shown and preferred in FIG. 16, is provided to a conventional D flip-flop 3036, with the composite sync output of sync generator 2022 being provided to the Dinput thereof, flip-flop 3036 preferably being clocked by the master clock A provided via path 3014. As a result, the output of flip-flop 3036 is preferably exactly the same as the input composite sync from generator 2022 except that it is slightlydelayed by a small fraction of the clock period, such as on the order of 50 nanoseconds, as necessary for transitions of the output to be exactly synchronized to the master clock frequency.
As was previously mentioned with respect to FIG. 14, multiplexer 2042 preferably receives as one selectable input, the output of a divide-by-2 flip-flop 2044 whose input is the master clock A output of phase locked loop 2024. As shown andpreferred in FIG. 16, flip-flop 2044 is preferably a conventional flip-flop which has the inverted clock A signal supplied to the clock input thereof through inverter 2045 and which generates an output frequency of one-half the clock A frequency via path2047 to multiplexer 2042. The other selectable input to multiplexer 2042, as was previously mentioned with respect to FIG. 14, is the serial data output of parallel-to-serial register 2050 provided via path 2048. As shown and preferred in FIG. 16,parallel-to-serial register 2050 preferably comprises two shift register stages 3038 and 3040, such as the type manufactured by Texas Instruments under designation SN74166N, which are preferably loaded in parallel and are shifted out alternately, firstseven bits being provided from one stage and then seven bits being provided from the other stage. The outputs of shift register stages 3038 and 3040 are preferably alternately selected by NAND gates 3042 and 3044. Preferably, the least significant bitof decade counter 3026 of character counter 2034 is supplied to one input of NAND gate 3042 and is applied inverted through inverter 3043 to one input of NAND gate 3044. This signal preferably alternates at the character rate and selects which NAND gate3042 or 3044 is on. The outputs of NAND gate 3042 and 3044 are connected as the two inputs to a negative NOR gate 3046 and, accordingly, alternate groups of seven data bits appear at these two inputs and a continuous stream of data bits is, therefore,present at the output of gate 3046 via path 2048 to multiplexer 2042.
As was previously mentioned with reference to FIG. 14, the switching of multiplexer 2042 is preferably accomplished by flip-flop 2038, which is preferably a conventional RS flip-flop which is set by the composite sync on one input via path 3050and is reset by the output of NAND gate 3034 of character counter 2034 which is the character 40 pulse. As shown and preferred in FIG. 16, multiplexer 2042 comprises NAND gates 3052 and 3054 whose outputs are connected to negative NOR gate 3056. Theselected data exists on output line 2046, gate 3052 and 3054 being supplied from opposite outputs of flip-flop 2038 so that one of these two gates is on when the other is off and vice-versa.
Now referring to the strobe control logic 2054, this logic preferably includes a conventional flip-flop 3060 which is cleared by the master reset signal provided via path 2018 from computer 2000 or by an output pulse from a conventional counter3062, to be described in greater detail hereinafter, contained within the strobe control logic 2054, provided via path 3063. Flip-flop 3060 is preferably set by the horizontal sync. The output of flip-flop 3060 is preferably connected to one input of athree input NAND gate 3064 whose two other inputs are provided from the frame enabling circuit or decoder 2062, to be described in greater detail hereinafter with reference to FIG. 17. The output of NAND gate 3064 will preferably be low during frameenable if flip-flop 3060 is set. This output is preferably combined with the FIFO ready signal in a negative NAND gate 3066 whose output will be high only if FIFO memory 2016 is ready as indicated by the FIFO ready signal provided via path 2058, bothframe enable signals are asserted and a horizontal sync pulse has been received since the last or previous transmission, as indicated by an output being provided from NAND gate 3064 to negative NAND gate 3066. If all these conditions are met, gate 3066will provide an output signal to the D input of another conventional flip-flop 3068 which will be set at the start of the next horizontal sync pulse present at its clock input. When flip-flop 3068 is set, this signifies that the system is ready to starttransmitting a pseudo video scan line. The output of flip-flop 3068 is preferably connected to the clock input of another flip-flop 3070 which is, accordingly, set at the time that flip-flop 3068 is set. When flip-flop 3070 is set, its output goes highenabling counter 3062 which then starts to count under control of the master clock A, provided via path 3014, which is supplied at its clock input. Counter 3062 is preferably a conventional four bit divide-by-16 counter, such as the type manufactured byTexas Instruments under the designation SN74163N. When counter 3062 counts to 8, its most significant bit goes high which supplies a high level signal via path 3071 to one input of a conventional two input NOR gate 3072. Gate 3072 then provides anoutput signal to a two input negative NAND gate 3074 which, in turn, provides an output signal to a two input NAND gate 3076 whose output is, in turn, inverted through an inverter 3078 to provide the FIFO .[.out.]. strobe .Iadd.out .Iaddend.signal viapath 2056 to FIFO memory 2016. When counter 3062 counts to 15, its carry output preferably goes high and is fed back to flip-flop 3070 via path 3079 to clear it which in turn clears counter 3062 ending its count cycle. Thus, counter 3062 preferablysupplies a single FIFO strobe out pulse to FIFO memory 2016 via path 2056 in the manner previously described at the beginning of a pseudo video scan line. The purpose of this is to preferably preload FIFO memory 2016 with the first valid word beforetransmission starts. Subsequent FIFO strobe out pulses are obtained from a negative NAND gate 3082 which generates a strobe out pulse when a negative pulse is present to gate 3082 from decoder 3022, which was previously described with reference to bitcounter 2030, as long as a horizontal sync pulse is not present at its other input, the output of gate 3082 being the other input to NOR gate 3072. The second input to negative NAND gate 3074 is preferably supplied from the negative output of flip-flop3068 which preferably inhibits a strobe pulse after 40 characters have been transmitted. The other input to NAND gate 3076, which is supplied from the counter stage 3026 through inverter 3043 to NAND gate 3076, preferably inhibits alternate pulses,pulses at the other input of NAND gate 3076 provided from the output of negative NAND gate 3074 occurring once per character whereas a FIFO strobe out pulse is needed only once per two characters, which is once per word.
Referring now to FIG. 17, the sync combiner 2052, frame enable decoder 2062 and line counter circuit 2064 shall be described in greater detail hereinafter. The line counter 2064 preferably comprises two four bit binary counter stages 3090 and3092, such as the type manufactured by Texas Instrument under the designation SN74193L. Counter stages 3090 and 3092 are preferably initially cleared by the vertical drive signal from sync generator 2022 provided via path 2025 and are clocked by thecomposite sync signal from sync generator 2022 provided via path 2023 via a conventional two input NAND gate 3094, the other input to NAND gate 3094 being the frame enable A signal output of decoder 2062 provided via path 3095. Clocking of counterstages 3090 and 3092 preferably continues until count 224 at which time decoder 2062, which is preferably a three input NAND gate, generates a low output via path 3095 turning off NAND gate 3094, NAND gate 2062 being the decoder which provides the frameenable signals via path 3095 and 3093, the frame enable signal provided via path 3093 being provided in parallel from one input to NAND gate 2062 from counter stage 3092 of line counter 2064.
Sync combiner 2052 which ultimately combines the composite video output pseudo video scan line signal 12, is preferably a conventional sync combiner as shown and preferred in FIG. 17, and has a data input via path 2046 and a composite sync inputvia path 2023, each of these inputs supplying current drive to a conventional transistor 3096 such that the collector output via path 3097 of transistor stage 3096 has a current determined by the combination of input logic levels and has three outputlevels corresponding to three signal levels, data varying between levels 2 and 3 corresponding to digital values of 0 and 1 and sync being indicated by level 1, this composite video signal output of path 3097 representing one pseudo video scan line at atime as described and shown with reference to FIGS. 1 and 2. This is the video signal transmitted from transmitter 20 to RF modulator 24 and therefrom through the cable distribution network 22 from which it is ultimately demodulated and provided toreceivers 28 for processing and ultimate provision to the video display devices 2013 and 2015 for display of the selected or grabbed frame as well as row-by-row update of the selected frame.
RECEIVER
General Description
Referring now to FIGS. 3 through 7, initially, and once again to FIGS. 1 and 2, the preferred receiver portion 28 of the row grabbing system 10 of the present invention shall generally be described in greater detail. Thereafter, with referenceto FIGS. 8 through 14, the preferred receiver portion 28 of the present invention shall be described in greater detail. As was previously described with reference to the preferred transmitter portion 20 of the row grabbing system 10 of the presentinvention, the transmitter 20 preferably provides what is generally termed a pseudo video scan line such as the type 12 illustrated in FIG. 1. This pseudo video scan line 12, as was previously described, is identical in format to a conventional videoscan line; that is, it is consistent with FCC and EIA standards for a video scan line signal format; however, this pseudo video scan line 12 actually contains a row of information, such as approximately between 11 and 13 actual television video scanlines of information with the transmission time of the pseudo video scan line 12 being equal to the transmission time of a conventional TV video scan line, which is approximately 63 microseconds. With respect to the pseudo video scan line 12, thehorizontal sync and vertical sync portions are identical to a conventional video signal as is the format for the horizontal sync and the vertical sync as well as the horizontal sync amplitude. The time and amplitude envelope of the video region of thepseudo video scan line 12, which region is defined as areas B,C,D,E and F in FIG. 1 is identical with the format for a conventional video scan line as is the three dimensional frequency envelope. Thus, all of the above mentioned standard conditions fora conventional video scan line signal are met by the pseudo video scan line 12 provided by the transmitter portion 20 of the row grabbing system 10 of the present invention and received by the receiver portion 28. Accordingly, any .[.euipment.]. .Iadd.equipment .Iaddend.that can handle conventional video can handle the pseudo video scan line 12 of the present invention which can thus be transmitted and received through a conventional television distribution system with conventional televisionequipment.
Referring once again to the pseudo video scan line 12 illustrated in FIG. 1, the signal received by the receiver portion 28 and transmitted by transmitter 20 is in reality a digital signal which looks like a conventional video scan line to thereceiver 28. The distribution of information in regions A through G of the pseudo video scan line, or row of information, illustrated in FIG. 1 is as follows. Region A represents the horizontal sync signal which starts the timing for the receiver 28and indicates the beginning of the pseudo video scan line from the beginning of the horizontal sweep for a conventional television scan line. Region B represents the pseudo video scan line 12 address which contains all the following information bitlocations. It should be noted, that preferably a 1 is indicated by the presence of a pulse and a 0 is indicated by the absence of a pulse, such as illustrated in FIG. 1 in region F where 1-0-1 is illustrated. When data is transmitted, as was previouslymentioned, all of the following information bits are present; group, which is the section or chapter including a predetermined number, such as 1,000, of pages and is the most significant bit of the page address, page which represents one frame in agroup; and row which occupies one character space which is preferably seven bits, and defines a portion of a page preferably containing approximately 11 to 13 scan lines which comprise one displayable character height. Region B also preferably containsdirect address information, which is the first transmitted bit preferably and is a 0 unless the direct address condition exists which is a control condition for a selected terminal informing the terminal to supersede the requested page. This region alsopreferably contains permission information which is a one bit position which is preferably a 1 when the user is being given authority to receive one or more selected groups of information. It should be noted that preferably there is also an emergencyoverride condition which provides control information to all terminals to override all requests including a permission request and occurs when the page and group information bit locations are 0, this condition preferably being utilized to displayemergency information such as a civil defence warning Region C is preferably a special character information region of 7 bits which is preferably utilized for optional functions to be performed by the individual receiver 28 or terminal. Region Dpreferably contains 32 characters of displayable information in digital form. Region E preferably contains 7 bits of error check information and, preferably may represent the complement of the binary equivalent of the sum of all of the 1 bits present inregions B, C, and D. Region F preferably contains the clock synchronizing burst or pulse train at the bit rate (the frequency preferably being equal to one-half the bit-rate) and comprises a pulse train of ones and zeros of two character spaces or 14bits. Region G is preferably the same as region A and represents the horizontal sync signal. As was previously mentioned, the vertical sync is provided by generating a special sequence of horizontal sync pulses during the normal television blankingperiod, which is after approximately 246 horizontal sync pulses, which in the present invention is after approximately 20 pages have been transmitted. Therefore, a 20 pages are transmitted before each vertical sync. The sync signal looks like aconventional composite sync signal with the vertical sync interval comprising approximately nine normal horizontal sync pulse times as illustrated in FIG. 2 which is an illustration of conventional composite sync and vertical drive signals.
Now referring to FIGS. 3 and 4, the preferred synchronization and timing portion of the receiver portion 28 of the row grabbing system 10 of the present invention shall generally be described. The synchronization and timing portion preferablycontains a conventional sync separator 400 which is provided in conventional fashion, through a conventional distribution system 22, with the composite video input via path 402 from the transmitter 20. As was previously mentioned, the composite videoinput provided via path 402 preferably includes data and horizontal sync information as well as vertical sync information at the appropriate given time. The conventional sync separator 400 separates the composite video input signal into a vertical syncsignal via path 404, a horizontal sync signal via path 406 and a data signal via path 408, the data signal via path 408 preferably including regions B through F for a given pseudo scan line of information which is received via path 402 by the syncseparator 400. The data portion of the pseudo of the pseudo video scan line 12 is provided in parallel as one input to a conventional two input NAND gate 410. The other input to NAND gate 410 preferably comprises the character 39 and the character 40pulse output signals of a counter and decoder circuit 412 to be described in greater detail hereinafter with reference to FIG. 8. Suffice it to say at this time that an output is present to NAND gate 410 from the counter and decoder circuit 412 duringthe time interval corresponding to characters 39 and 40, as will be described in greater detail hereinafter. The output of NAND gate 410 is provided to a conventional phase locked loop 414, to be described in greater detail hereinafter with reference toFIGS. 4 and 8. Suffice it to say that phase locked loop 414 is preferably a correctable voltage controlled oscillator which operates without any additional input, as illustrated in FIG. 4, at the data bit rate, which is preferably, by way of example,approximately 5.11 megahertz, and is preferably crystal controlled. As illustrated in FIG. 4, the phase locked loop 414 preferably comprises a conventional phase .[.dectector.]. .Iadd.detector .Iaddend.416, a conventional filter 418 connected to theoutput of the phase detector 416 and a conventional voltage controlled oscillator 420 which is conventionally crystal controlled by crystal 422 which is connected to the output of filter 418. In addition, a feedback path is conventionally providedbetween the output of voltage controlled oscillator 420 and the phase detector 416 through a conventional divide-by-two flip-flop 424. Thus, a reference frequency, which is half the data bit rate is provided to the phase detector 416 and the output ofthe voltage controlled oscillator 420 is the master clock frequency, termed clock A at the data bit rate. By way of example, the reference frequency is approximately 2.55 megahertz and the clock A frequency is approximately 5.11 megahertz. Thus, theclock A output is provided via path 426 from the conventional phase locked loop 414.
Referring once again to FIG. 3, the clock A output provided via path 426 is provided to a conventional selectable divide-by-8 or divide-by-1 frequency divider 428 (FIG. 6) whose output is either the clock A signal or the clock B signal which isthe clock A signal divided by eight. Thus, for example, clock B is approximately 0.64 megahertz and is provided via path 430 (FIG. 6). This clock B signal provided via path 430 from selectable frequency divider 428 is preferably provided as an input tothe counter and decoder circuit 412 which preferably decodes the character positions and the bits within the character by counting clock pulses starting with the end of the horizontal sync pulse, as will be described in greater detail hereinafter, sevencounts preferably being provided per character. The horizontal sync input is also preferably provided to the counter decoder circuit 412 to start and/or reset the counters contained therein. The output of the counter and decoder circuit 412 ispreferably the control information corresponding to character positions 1 through 41 and bits 1 through 7, by way of example. As was previously mentioned, the character position control information for character positions 39 and 40 is preferablyprovided as one input to the two input NAND gate 410. It should be noted that preferably character positions 39 and 40 are the 14 bits which comprise region F of the pseudo video scan line 12. Accordingly, NAND gate 410 only preferably provides anoutput to phase locked loop 414 when the data portion of the pseudo video scan line 12 is at region F so that only information contained in region F is provided to phase locked loop 414. As was previously mentioned, region F is the reference frequencywhich is one-half the data bit rate or one-half the master clock frequency which is supplied to the phase detector 416 which conventionally functions together with the feed back signal from the voltage controlled oscillator 420 as modified by theflip-flop 424 to provide a feedback frequency equal to the reference frequency which corrects the voltage controlled oscillator 420 if there is any difference, whether this difference be in frequency or phase. In addition, circuit 418 conventionallyfunctions to stabilize the phase locked loop 414, the output of the phase locked loop 414 being a continuous clock signal which is twice the reference frequency and identical in phase. Preferably, the data bit rate is equivalent to twice the maximumfrequency of transmission, with the highest frequency of transmission possible being two bits per cycle for a digital signal.
The data information portion of the pseudo video scan line 12 is also preferably provided in parallel to an error check circuit 432 which preferably receives control or timing information from the counter and decoder circuit 412 via path 434corresponding to character position 38 as well as receiving data via path 408 from the sync separator 400. As was previously mentioned, character position 38 preferably corresponds to the error check information portion of the pseudo video scan line 12. Error check circuit 432, will be described in greater detail hereinafter with reference to FIG. 8 with respect to the presently preferred arrangement for accomplishing an error check. With respect to the arrangement illustrated in detail in FIG. 8,error check circuit 432 preferably counts the number of "one" bits in characters 1 through 7 which comprise regions B, C, and D, preferably, and compares that sum with the binary number located in character position 38, which corresponds to region E, andrequires non-coincidence in every bit of that comparison since character position 38 or region E preferably contains the complement of that sum. Error check circuit 432 provides an output signal, such as a 1 , indicating the error check is OK when thepreferred error check condition exists, this signal being termed "error check OK signal" provided via path 436. This error check OK signal on path 436 will preferably remain until the next error check of the next subsequent pseudo video scan line whichoccurs one conventional television video scan line transmission time after the previous pseudo video scan line. The complement of this sum is preferably selected from an .[.erro.]. .Iadd.error .Iaddend.check sum to allow a check for empty lines, whichare lines that only contain information in regions F and G which, in such an instance, would sum to 0. If the complement was not utilized for the error check sum in region E, such a signal would pass the error check since the sum would be 0 andcharacter position 38 would contain a 0 so the sum would match. Therefore, by utilizing the complement, empty line signals would be rejected, which is preferred in the present invention.
The output of the counter and decoder circuit 412 also preferably comprises a character clock signal for the main memory write mode, as will be described in greater detail hereinafter with reference to FIG. 8, which is provided to a conventionaltwo bit multiplexer 440 which also receives as inputs a character clock signal in the main memory read mode from a column counter 442 (FIG. 7) to be described in greater detail hereinafter, via path 444, and a select input via path 446 which signalselects between the character clock input in the write mode and the character clock input in the read mode in response to the provision of a memory read/write signal from memory write logic 450 (FIG. 6), to be described in greater detail hereinafter, viapath 446. Preferably, in response to a memory write command which is provided from the memory write logic 450 via path 446, the character clock input selected by multiplexer 440 is the signal provided from the counter and decoder circuit 412, whereas inresponse to a memory read command provided from the memory write logic 450, the character clock input selected by multiplexer 440 is the character clock provided from column counter 442. The character clock input selectively provided from multiplexer440 is used to clock a character counter 454, to be described in greater detail hereinafter with reference to FIG. 12, which also receives the horizontal sync input to start and/or reset the counter 454. The output of the character counter 454 is thecharacter address. The data portion of the pseudo video scan line 12 provided via path 408 is also provided in parallel to a conventional serial memory 456 which is a one line buffer which preferably delays the signal by one conventional televisionvideo scan line transmission time (preferably for character positions 4 through 37, by way of example) before the provision of the data to a main memory portion 458 to be described in greater detail hereinafter. This delayed data is also provided inparallel via path 460 to a permission memory 462 (FIG. 6), to be described in greater detail hereinafter. This one conventional television video scan line transmission time delay enables the testing, to be described in greater detail hereinafter, of thepseudo video scan line 12 for purposes of deciding whether or not to write this infomation into a main memory 464 of the main memory portion 458 prior to the actual writing of the data into this main memory 464. The actual generation of the read/writecommand to the main memory 464 will be described in greater detail with reference to FIGS. 5 and 6.
With reference to the main memory portion 458 of FIG. 3, the serial memory 456 preferably has a 256 bit capacity and serially loads these bits one character or seven bits at a time into a conventional shift register 466, which is a one wordserial-to-parallel converter which comprises a conventional seven bit shift register which parallel unloads seven bits into a character latch 468, to be described in greater detail with reference to FIG. 12 or into a row latch 470 to be described ingreater detail hereinafter with reference to FIG. 12, depending on the particular character position. As was previously mentioned, preferably characters 4 through 37 which represent, preferably, regions B, C, and D of the pseudo video scan line 12 areloaded into the serial memory 456. Preferably, character latch 468 and row latch 470 are enabled by enable signals provided from counter and decoder circuit 412 at the appropriate times. Preferably, row latch 470 receives character position 4information, which preferably comprises the row information and character latch 468 preferably receives character positions 6 through 37, which comprises region D, which preferably is the character or displayable data information. Preferably, as waspreferably mentioned, the special character is located at character position 5 and is not unloaded to character latch 468. In addition, shift register 456 receives the clock B input signal as a clock signal therefor. The output of character latch 468preferably provides a displayable data input in parallel to memory 464 one character at a time or seven bit parallel. In the memory write mode, row latch 470 will preferably provide the row address in parallel to memory 464 for a given pseudo video scanline 12, which row address is preferably set once per pseudo video scan line 12. In the memory write mode, the row latch 470 output is provided to a conventional multiplexer 474 which switches the address input of memory 464 to the output of row latch470. In the memory read mode, multiplexer 472 siwtches the row address input of memory 464 to the output of row counter 474 (FIG. 7), to be described in greater detail hereinafter. Preferably, five bits of row address are utilized which is adequate forproviding address information for 32 video displayable rows. As was previously mentioned, the main memory 464 address input identifies the character address or character position which is provided from the output of character counter 454, which ispreferably a five bit counter capable of supplying 32 character addresses utilizing the character clock input (one clock per character) and the horizontal sync to provide the character addres. Accordingly, memory 464 is preferably, by way of example, arow-by-32 character array or page, of which 16 or 32 rows may be utilized. Memory 464 receives a read or write command via path 446 from memory write logic 450 (FIG. 6), as will be described in greater detail hereinafter. It should be noted thatpreferably four bits are utilized to assign 16 rows and one bit is utilized to assign a left control condition and a right control condition if 64 characters are to be displayed instead of 32 characters, assuming a page has normally been defined as 32characters wide by 16 rows high, 64 characters representing two pages. It should also be noted that row latch 470 also provides a permission bit output via path 480 to the permission write logic 482 (FIG. 6), to be described in greater detailhereinafter.
Preferably, as was previously mentioned, the group and/or page to be displayed or grabbed in real time is selected by means of a conventional keyboard 484, to be described in greater detail hereinafter. Suffice it to say at this time thatkeyboard 484 is preferably a conventional ten digit keyboard which provides a serial digital output. For example, if decimal 326 is the number depressed on the keys of the keyboard 484, then keyboard 484 will conventionally put out a pulse train of 326pulses. The outputs from keyboard 484 are preferably the control signal "group call" provided via path 486, the "number" selected provided via path 488, the control condition "up" or more provided via path 490 which represents incrementing the selectednumber by one preferably; the control condition "down" or back provided via path 492 which preferably represents decrementing the selected number by 1; and the control condition "page call" provided via path 494, the control conditions up and downincrementing or decrementing the group or page selection depending on which condition, group or page, was most recently selected. This keyboard 484 output via paths 486 through 494, inclusive, is preferably provided to a .[.key board.]. .Iadd.keyboard.Iaddend.counter 500 (FIG. 5), to be described in greater detail hereinafter, where this information is interpreted to control the selection of the appropriate frame to be grabbed in real time.
Referring now to FIGS. 5 and 6 the generation of the memory read/write command provided via path 446 and a memory write clock provided via path 995 from memory write logic 450 shall generally be described. As was previously mentioned, the outputof keyboard 484 is provided to keyboard counter 500, to be described in greater detail hereinafter, which counts the pulse train corresponding to the number selected and provides a parallel binary output, such as preferably 10 bits, for both the groupselected via parallel paths 502 and for the page selected via parallel paths 504, and increments or decrements the appropriate counter in response to the receipt of the up or down control signal from the keyboard 484. The selected page output 504 fromkeyboard counter 500 is preferably provided in parallel to a conventional multiplexer 506 which sequentially switches each parallel output 504 to a single output line 508 to provide a serial selected page address on path 508. Multiplexer 506 isaddressed to switch by a page address counter 510 to be described in greater detail hereinafter with reference to FIG. 10, which is in turn operated by the page address clock provided via path 512 from counter and decoder circuit 412 (FIG. 3), this pageaddress clock preferably being 10 bits or pulses which correspond to the page address bits. The output of the page address counter 510 is preferably a binary number representing the bit number within the page address sequence and controls the switchingof multiplexer 506. Multiplexer 506 and page address counter 510 are preferably equivalent to a 10 bit parallel load/serial out shift register. The page address counter 510 and multiplexer 506, as will be described in greater detail hereinafter, permitthe page address to be checked. In order to accomplish this, the serial page address output on path 508 is provided as one input to a conventional exclusive or gate 514 whose other input is the page address bit present on the data line 408, the serialpage address bits on path 508 being provided in coincidence with the page address bits on data line 408. When the pseudo vidso scan line page address on data line 408 is the same as the serial page address on path 508, the output of exclusive or gate514 will be low, which in the logic chosen by way of example represents a 0. When these inputs differ, in other words when there is a lack of coincidence, the output of exclusive or gate 514 will be high (a 1 in the logic chosen) for at least one clockperiod of the page address sequence. The output of exclusive or gate 514 is provided to a conventional flip-flop 516 which, when the output of 514 is high, will be clocked by the page clock provided via path 512. Flip-flop 516 is preferably aconventional JK flip-flop. If at any time during the page address sequence, the output of 514 goes high, the output of flip-flop 516 will preferably go low and provide no output and remain low until reset by the horizontal sync at the end of the pseudovideo scan line 12. The normal condition of the output of flip-flop 516 provided via path 518 is a high or 1 indicating that the page address is OK or checks, this signal being termed the "page address OK signal" which is provided to anotherconventional flip-flop 520 (FIG. 6) which supplies this information to the memory write logic 450.
Now considering the provision of a user address check to insure that the correct user is receiving the pseudo video scan line. The page address counter 510 output is also provided in parallel to multiplexer 522 whose other input is a hard-wireduser address 524. The user address perferably occupies the same space in the pseudo video scan line as the page address and, accordingly, the receiver 28 must preferably be able to distinguish between the two. The page address counter 510 outputsequentially switches multiplexer 522 to provide a serial bit user address on path 526 to EXCLUSIVE OR GATE 528 whose other input is the data path 408. The serial user address provided via path 526 is in coincidence with the user address bits providedvia path 408 to gate 528. When the pseudo video scan line user address provided via path 408 is the same as or coincident with the user address provided via path 526, the output of gate 528 will be low for the logic chosen by way of example. When thereis a lack of coincidence between these two inputs to gate 528, the output of gate 528 will be high for at least one clock period of the user address sequence. The output of gate 528 is preferably provided to a conventional JK flip-flop 530 which ispreferably clocked by the page address clock provided via path 512. If at any time during the user address sequence, which is preferably identical with the page address sequence, the output of gate 528 goes high, the output of flip-flop 530 willpreferably go low (a no output condition) and remain low until reset by the horizontal sync, provided via path 406, at the end of the pseudo video scan line. The normal condition of the output of flip-flop 530 is preferably high on path 532 indicatingthat the user address checks or is OK, indicated by the term "user address OK signal" which is provided as one input to the permission write logic 482 (FIG. 6). The user address O.K. signal is also provided to memory write logic 450 through a flip-flop960, via path 961, which preferably introduces a one scan line delay.
Now considering the direct address condition we refer once again to FIG. 5. As was previously mentioned, the first bit of the address in region B of the pseudo video scan line 12 is preferably the direct address bit. A bit one gate signal isprovided as an output from a decoder 940,942 (FIG. 10) via path 534 and is termed the "bit one gate" output. This output is provided to a conventional flip-flop 536 which senses whether this signal is a 1 or 0. Flip-flop 536 provides an output signal"direct address OK" on path 538 when the first bit is a 1. The data line input from sync separator 400 provided via path 408 is provided to flip-flop 536 which is clocked by the bit one gate output on path 534 from decoder 412. The output of flip-flop536 provided via path 538, which output is termed the direct-address-OK-signal when a direct address condition is present, is preferably provided to another conventional flip-flop 540 (FIG. 6) whose output is connected as one input to the memory writelogic 450 to be described in greater detail hereinafter.
Referring now to FIG. 6, the generation of the read/write main memory command via path 446, the main memory write clock via path 995 and the generation of the permission memory read/write command from the permission write logic 482 shall bedescribed in greater detail hereinafter. As was previously mentioned, the permission bit of the row address position is provided via path 480 from the row latch 470 to the permission write logic 482, as is the user address OK signal on path 532 fromflip-flop 530. Permission write logic 482 preferably stores the user address OK signal and delays it for one conventional television video scan line transmission time as illustrated in FIG. 6a. If the delayed user address OK signal is present at thesame time the permission bit signal is present on path 480, permission write logic 482 preferably provides a permission write command signal via path 550 to the permission memory 462 and, in parallel, to a conventional multiplexer 552 as a select signalthereto. Permission memory 462 preferably receives data input via path 460 from the output of serial memory 456 (FIG. 3). In the write mode for the permission memory 462 via path 550, multiplexer 552 selects the address input for permission memory 462from the parallel output of a bit counter 554 which provides one input to multiplexer 552, the other selectable input to multiplexer 552 being the selected group parallel bit output 502 of keyboard counter 500. The input to the bit counter 554 is theclock B output of the divide-by-8 or divide-by-1 frequency divider 428, with the divide-by-8 or divide-by-1 mode selected by the condition of line 550. In the permission write mode, frequency divider 428 is preferably set as a divide-by-8 counter sothat the output in this mode is the clock B output comprising the clock A input divided by 8 or, in the example given, approximately 0.64 megahertz. This clock-A-divided-by-8 output of frequency divider 428 in this permission write mode is preferablyalso utilized as the clock input for the serial memory 456. As a result, the permission memory 462 address is preferably changed coincident with the shifting of the input data, both occurring at the reduced clock B rate. It should be noted that thepermission bit only identifies one pseudo video scan line of data as a permission line but is not the actual permission indication, all data of that pseudo video scan line having the permission bit comprising the permission data or indication. It isthis permission data which is provided to the permission memory 462 via path 460. The permission data provided via path 460 to permission memory 462 preferably contains information as to which group the user has permission to receive. Each bit ofpermission data pertains to a different group, preferably, and is stored in permission memory 462 addressable by bit. For example, if one starts counting with the beginning of the fifth character position, if the 24th bit in the pseudo video scan lineobtaining permission information after the start of the count was a 1, that bit would be present at the input of permission memory 462 at the time that the address input to permission memory 462 was the binary number 24. Therefore, when in thepermission read mode, if the address is 24, that would be output on line 556 as a permission OK signal. The above, is thus an example of giving permission for group 24. Preferably, the permission memory 462 is non-destructible and, is preferablyconstructed to operate at the reduced address rate, the clock-A-divided-by-8 rate being the preferred standard inexpensive MOS memory (for example a Signetics 2602B) operating rate. However, because of utilizing the reduced operating rate ofclock-A-divided-by-8, it takes 8 pseudo video scan lines of time to perform this permission writing operation. This can, however, be conventionally scheduled by conventional programming of a computer to avoid any noticeable lag (due to interleaving)since any given terminal or receiver 28 does not normally receive all successive pseudo video scan lines as each successive scan line preferably pertains to a different page. For example, as previously mentioned, the sequence of transmission ispreferably page 1, line 1, page 2, line 1, etc. until all the pages have line 1 thereof transmitted and then page 1, line 2, page 2, line 2, etc., until all the pages have line 2 transmitted and so forth until each line of each page has been transmitted. Thus, the pseudo video scan lines of one page are preferably interleaved with the pseudo .[.vido.]. .Iadd.video .Iaddend.scan lines of another page so that a direct full-page-by-full-page transmission does not occur; rather the transmission ispreferably one row per page at a time.
Now describing the permission read mode and referring once again to FIG. 6, the permission read condition on line 550 is the opposite condition from the permission write condition occurring on line 550. In the permission read mode, the selectedgroup information 502 provided from keyboard counter 500 to multiplexer 552 is the address input which is provided to permission memory 462, this input 502 having been selected by multiplexer 552 which has been switched by the permission read signalappearing on line 550. If this address input 502 to permission memory 462 is a permitted group, then a permission OK signal, such as a 1, will be present on line 556. For example, if, as in the previous example, group 24 was selected, then a permissionOK signal would be present on line 556. Accordingly, the operation of permission memory 462 is a conventional look-up table operation.
The page address OK signal present on path 518 is provided to flip-flop 520 to introduce a delay equivalent to the transmission time for one conventional television video scan line. Similarly, the direct address OK signal which would be presenton line 538 is introduced to flip-flop 540 to introduce a delay equivalent to the transmission time for one conventional television video scan line. As shown and preferred in FIGS. 6 and 6a, all single television video scan line delay outputtransmissions provided by the permission write logic 482, flip-flop 520 and flip-flop 540 occur at the time of the occurrence of the character 41 timing signal from decoder 412. As is also shown and preferred in FIG. 6, the delayed page address OKsignal flip-flop 520 output is provided via path 560 to the memory write logic 450, the delayed direct address OK signal output from flip-flop 540, when such a signal is present, is provided via path 562 to the memory write logic 450 and the delayed (onescan line) error check OK signal is provided via path 436 to the memory write logic 450. In addition, the permission OK signal is provided via path 556 to the memory write logic 450. As will be described in greater detail hereinafter, the main memorywrite command signal is provided to multiplexer 440 via path 446 when the error check OK signal is present on path 436 and either the direct address OK signal is present on path 562 or both the page address OK signal is present on path 560 and thepermission OK signal is present on path 556. When these conditions are met, the memory write command signal is provided via path 446 to multiplexer 440.
Referring once again to FIG. 3, the provision of data 564 from main memory 464 as well as the loading of the main memory 464 shall be discussed. The main memory write clock signal provided via path 995 to main memory 464 preferably causes memory464 to input data from the serial memory buffer 456 in the following write cycle. As was previously mentioned, the input data to memory 464 is one pseudo video scan line 12 of data. Serial memory 456 provides the data one character or seven bits at atime serial to shift register 466. Shift register 466 in turn provides this data to character latch 468 seven bits parallel. While the next seven bits of the next character are being shifted into shift register 456 from serial memory 456, the firstseven bits previously loaded into the character latch 468 are loaded into the memory 464. This cycle continues preferably 32 times to load all characters of one row, which is a psuedo video scan line, into memory 464. At that time, the write cycle iscomplete. The write cycle begins anew when another main memory write clock signal is received by memory 464 and all other previously mentioned conditions are met.
In the read mode, a main memory read command signal is provided to multiplexer 440 via path 446. This memory read command signal condition is present on path 446 when the memory write command signal condition is not present as it represents theopposite conditions for line 446. The character address is provided from character counter 454 to main memory 464 in the same manner as previously discussed with respect to the write mode. Main memory 464 provides the parallel bit data output 564 tocharacter generator 570 (FIG. 7), to be described in greater detail hereinafter, as addressed by row and character. This parallel bit data output 564 is preferably a seven bit parallel representation of alphanumeric characters, such as an ASCII code ofboth upper and lower case letters, or just upper case letters and special symbols for graphics or other purposes such as chemical symbols, stock market fraction symbols, etc.
Now referring to FIG. 7, the display of decoded data such as characters and symbols shall generally be described. It should be noted that, preferably, the operation of the circuitry illustrated in FIG. 7 is preferably that of a conventionaltelevision digital display terminal. For purposes of discussion, it shall be assumed that a row of pseudo video scan line 12 contains 13 conventional television video scan lines of data, although, if desired, such a system could utilize 11 conventi | | | |
