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Reactive computer system adaptive to a plurality of program inputs |
| RE31736 |
Reactive computer system adaptive to a plurality of program inputs
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| Patent Drawings: | |
| Inventor: |
Mueller, et al. |
| Date Issued: |
November 13, 1984 |
| Application: |
06/398,719 |
| Filed: |
July 15, 1982 |
| Inventors: |
Moravec; John V. (Willow Springs, IL)
Mueller; David J. (Naperville, IL)
Prysby; Daniel G. (Elk Grove, IL)
Watson; George A. (Fullerton, CA)
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| Assignee: |
Rockwell International Corporation (El Segundo, CA) |
| Primary Examiner: |
Zache; Raulfe B. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Hamann; H. FredrickMcGlynn; Daniel R. |
| U.S. Class: |
345/549; 345/551; 715/539 |
| Field Of Search: |
364/2MSFile; 364/9MSFile; 364/521; 358/81; 358/82; 358/903; 340/701; 340/703; 340/725; 340/731; 340/745; 340/756; 340/799; 273/DIG.28 |
| International Class: |
G06T 17/00 |
| U.S Patent Documents: |
3376465; 3623069; 3624634; 3639910; 3736564; 3742289; 3750133; 3767901; 3829095; 3877009; 3886588; 3918039; 3944999; 3973244; 3995312; 3996584; 4026555; 4070710; 4071843; 4139838; 4142180; 4155095; 4180805; 4301503 |
| Foreign Patent Documents: |
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| Other References: |
Peter B. Denes, Computer Graphics In Color, Bell Laboratories Record, May 1974, pp. 139-148..
Russell Peterman, Brightening Up A Digital-TV Display, Digital Design, Jul. 1976, pp. 46-51.. |
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| Abstract: |
There is disclosed a computer system including a storage means such as a random access memory (RAM) for receiving data to be displayed upon a display means, e.g. a color cathode ray tube, a microprocessor for control of the computer system operations, and viewer input devices such as a control stick or keyboard, whereby the viewer may respond selectively to the data displayed upon the display means. A limited capacity storage unit, illustratively in the form of a tape cassette, stores data in the form of a program for permitting the viewer to store useful material in the form of a repository, such as a Christmas list; the program to be displayed by the display means can assume any of a limitless number of programs and may be adapted to an exceptionally wide range of uses for the home, office or school. The computer system permits the viewer to respond as through the input devices, to the material being displayed, whereby subsequent material may be effected. To effect a variety of operations, the computer system includes a record/read device for receiving the storage unit, whereby the stored data thereon may be read out and stored in the RAM for subsequent use by the computer system. In this regard, graphic material to be displayed upon the display means is stored in select locations in the RAM to be selectively read out, dependent upon the image to be displayed. Further, there is included a second storage means in the form of a read-only memory (ROM) for storing utility sub-routines, whereby various operations of the computer system may be controlled. |
| Claim: |
What is claimed is:
1. A data processing and display system for transferring data between said system and a data storage unit, the data storage unit storing a set of characters from which aplurality of composite images may be formed, image data identifying the arrangement of the characters to form a desired image, and color information identifying a palette of colors from which the characters may be colored, said system comprising:
(a) color display means for displaying images of a selected arrangement of characters chosen from the set and characters colored with selected colors from the palette;
(b) means for reading data from the data storage unit;
(c) addressable storage means coupled to said reading means for receiving therefrom and for storing data derived from the storage unit indicative of the set of characters and the palette of colors; and
(d) display control means for first addressing the image data in a first portion of said addressable storage means to obtain a first readout, and secondly for using the first readout data and being coupled to said color display means to receivedata identifying the currently displayed image by said color display means for addressing a second portion of said storage means to obtain signals indicative of the character color then to be applied to and displayed by said color display means.
2. The system as claimed in claim 1, wherein there is included an input/output data bus for bidirectionally conveying data between said addressable storage means and each of said color display means, said data reading means and said displaycontrol means.
3. The system as claimed in claim 2, wherein said display control means comprises timing means for providing address signals and there is further included an address bus means interconnecting said timing means and said addressable storage meansby which the address signals are applied to said addressable storage means.
4. The system as claimed in claim 3, wherein said color display means displays the colored images in a raster format comprised of a series of horizontal lines and said timing means provides a first train of horizontal timing signalscorresponding to the end of each horizontal line and a second train of vertical timing signals corresponding to the end of each raster.
5. The system as claimed in claim 4, wherein said color display means displays the images in the form of the selected arrangement of characters, each character comprised of a first number of horizontal lines, each line having a second number ofincremental dot portions disposed upon a horizontal line, each such character disposed in a text line of a third number of characters, so that a fourth number of the text lines forms the selected image composed of the selected arrangement of characters,said timing means providing first timing signals in the form of a character count indicative of which character in the horizontal line is to be displayed, and second timing signals indicative of the text line of the character to be displayed.
6. The system as claimed in claim 3, wherein said timing means provides first address signals to effect the first readout of data within said addressable storage means, and second address signals to effect the second readout of data from saidaddressable storage means.
7. The data processing system as claimed in claim 3, wherein said system comprises a microprocessor for developing command signals to be applied to said addressable storage means whereby the reading and writing of data thereto and therefrom iscontrolled, and coordination means responsive to the output of said timing means to coordinate the application of the microprocessor command signals.
8. The system as claimed in claim 4, wherein said timing means comprises a character counter for providing an output signal corresponding to the number of characters scanned within a line of the display, and a text counter for providing a countsignal indicative of the text line being displayed.
9. The system as claimed in claim 8, wherein said display control means comprises a first bus driver responsive to the outputs of said character counter and said text counter, for applying a first memory address signal to said addressablestorage means to obtain the first readout.
10. The system as claimed in claim 9, wherein said timing means comprises a raster counter for indicating the number of rasters displayed upon said color display means for providing a signal indicative thereof.
11. The system as claimed in claim 10, wherein said display control means further comprises a second bus driver coupled to said address bus and responsive to the first readout and to the raster count signals for providing a second memory addressto said addressable storage means to read out the image data corresponding to that of a character to be applied to said color display means.
12. The system as claimed in claim 7, wherein said coordination means comprises a gate for selectively passing the microprocessor command signals in response to timing signals developed by said timing system.
13. The system as claimed in claim 1, wherein said display control means includes a color memory for storing that portion of the palette of colors corresponding to those colors by which the characters of the image currently being displayed maybe colored.
14. The system as claimed in claim 13, wherein said display control means further comprises latch means for receiving during the first and second readouts image data including color pointers for identifying those colors of the palette by whichthe characters of the image currently being displayed are to be colored.
15. The system as claimed in claim 14, wherein said display control means comprises address means responsive to the pointers for addressing and reading out from said color memory a selected one of the palette of colors.
16. The system as claimed in claim 13, wherein said display control means comprises color latch means for receiving color pointers indicative of the background, a foreground and edge portions of the image to be reproduced by said color displaymeans, and a color controller for selectively applying the aforementioned color pointers to address said color memory.
17. The system as claimed in claim 16, wherein there is further included second latch means for receiving the color pointers and said color controller is responsive to control data conveyed with the color pointers to effect a selectedinterchange of the color pointers associated with the background, foreground and edge portions of the color image displayed by said display means.
18. The system as claimed in claim 2, wherein there is included a plurality of generator means, each for receiving image date corresponding to a symbol to be displayed by said color display means, and means for controlling the placement of eachof the symbols of said generator means within the display of said color display means.
19. The system as claimed in claim 18, wherein said control means comprises means for storing an indication of the coordinates of each of the symbols of said generator means and means for reading from each of said generator means the symbolimage data to be displayed by said color display means.
20. The system as claimed in claim 19, wherein said color display means displays an image in a raster format comprised of a series of horizontal lines, each of said generator means comprising a register for receiving its symbol image data fromsaid addressable storage means.
21. The system as claimed in claim 20, wherein said color display means comprises a timing system for providing a first count signal indicative of the number of scanned horizontal lines of the display and for providing a second count signalindicative of the number of characters that have been scanned across a horizontal line.
22. The system as claimed in claim 21, wherein said storing means comprises a first, vertical position memory for receiving and storing an indication in terms of the horizontal line at which a symbol is commenced to be generated, and acomparator responsive to the output of said vertical position memory and the vertical count signals to provide an initiate signal to enable the display of the symbol image data from one of said generator means.
23. The system as claimed in claim 22, wherein there is included a plurality of counters for receiving a first count initiated signal indicating the horizontal position across each horizontal line of the image display upon which itscorresponding register is to initiate the readout of its symbol image data, said timing system providing a dot clock signal indicative of each elemental dot area of a horizontal line to be applied to each of said counters, and upon counting to the countas set by its count signal, each counter generates and applies an initiate signal to its corresponding register.
24. The system as claimed in claim 22, wherein there is included a gate responsive to the output of said character counter to selectively transmit symbol image data from said addressable storage means via said input/output data bus to each ofsaid registers, and decoding means responsive to the second count signal to enable a selected one of said registers to receive the symbol image data, and comparator means responsive to the first count signal and to the output of said vertical positionmemory to enable said gate to transfer the symbol image data from said addressable storge means to the selected one of said registers.
25. The system as claimed in claim 24, wherein there is included a plurality of counters for receiving via said enabled gate a second count initiate signal indicative of the position within a horizontal line of the display at which the displayof the symbol is to begin, and said timing means provides its dot clock signal to each of said counters, whereby upon reaching the count as set by the second count initiate signal, said counter generates an initiate signal to be applied to itscorresponding serial register, whereby its symbol image data is read out to be displayed by said color display means.
26. The system as claimed in claim 3, wherein the data storage unit also stores audio data to be transferred by said means for reading data to said addressable storage means, and there is further included a waveform generator for producing aplurality of sound signals and audio control means coupled to said storage means and responsive to the audio data stored therein to select of the sound signals from said waveform generator.
27. The system as claimed in claim 26, wherein said audio control means comprises a first frequency circuit for receiving from said addressable storage means a signal indicative of the initial frequency to be generated, and a second gain circuitfor receiving from said addressable storage means a signal indicative of the gain of the sound to be generated, said first frequency circuit coupled to said waveform generator to control the frequency thereof, and a variable amplifier connected to theoutput of said waveform generator and responsive to the output of said second gain circuit to control the amplitude of its output signal to be applied to an audio speaker.
28. The system as claimed in claim 27, wherein there is comprised a first latch for receiving the initial frequency signal, a second latch for receiving the initial gain signal and a third latch for receiving signals for increasing or decreasingeither the frequency of the audio sound to be generated or to increase or decrease the gain of the audio sound, and a decoder responsive to the output of said timing system for respectively enabling said first, second and third latches to receive theaudio data as applied by said input/output data bus to said first, second and third latches.
29. A data processing and display system for transferring data between said system and a data storage unit, the data storage unit storing a set of characters from which a plurality of composite images may be formed, and image data identifyingthe sequence in which the characters are to be arrayed to form the desired image, said system comprising:
(a) display means for displaying images of a selected arrangement of the characters chosen from the set;
(b) means for reading data from and writing data upon the data storage unit;
(c) addressable storage means for storing data derived from the data storage unit indicative of the set of characters;
(d) viewer entry means manipulatable by the system's viewer to enter data into said system;
(e) control means for selectively addressing information within said addressable storage means to read out selected characters of the set and for applying same to said display means, whereby a desired image is displayed thereby, and forselectively applying the data entered upon said viewer entry means and to apply same to said data reading/writing means, whereby the viewer data is stored upon the data storage unit.
30. The system as claimed in claim 29, wherein there is included an input/output data bus for bidirectionally conveying data between said addressable storage means and each of said display means, said data reading/writing means, said viewerentry means and said control means.
31. The system as claimed in claim 30, wherein said control means comprises timing means for providing therefrom address signals and a clock signal, and there is further included an address bus interconnected between said timing means and saidaddressable storage means, by which the address signals are applied to said addressable storage means.
32. The system as claimed in claim 31, wherein the data storage unit further stores a clock signal, said timing means further providing a read/write command signal, and said data read/write means comprises a select clock signal circuitresponsive to the read/write signal to send either the clock signal as derived from the data storage unit or from said timing means to provide the corresponding clock signal.
33. The system as claimed in claim 32, wherein said read/write means comprises first and second latches coupled to said input/output data bus, and decoder means responsive to the read/write command signal to correspondingly enable said firstlatch to receive data from said input/output data bus and to write same upon the storage unit, and to enable said second latch to apply data to said input/output data bus from the data storage unit.
34. The system as claimed in claim 33, wherein there is comprised third and fourth latches and a command decoder, said timing system further providing a tape timing signal, said decoder means responsive to the tape timing signal to receive atape command signal from said data bus, said third latch responsive to an output of said decoder, whereby the tape command signals are applied to said command decoder to control the driving of the tape of said storage unit.
35. The system as claimed in claim 34, wherein the storage data unit further stores control signals indicative of the beginning and end of data stored upon the storage unit, and said decoder is responsive to a timing signal of said timing systemto actuate said fourth latch, whereby said fourth latch is enabled to transmit the control signals via the input/output data bus to said control means.
36. The system as claimed in claim 31, wherein said viewer entry means comprises a keyboard-type entry device actuatable by the viewer to enter data in alphanumeric form via said input/output data bus to said addressable storage means.
37. The system as claimed in claim 36, wherein there is further included decoder means responsive to a timing signal derived from said timing means indicative of a time interval in which image data is not being displayed by said display meansfor actuating said keyboard-type device to transmit the alphanumeric data as entered thereon.
38. The system as claimed in claim 31, wherein said viewer entry means comprises a joy stick maneuverable in at least two coordinate directions for providing output signals indicative repetitively of the movements in the coordinate directions.
39. The system as claimed in claim 38, wherein there is included multiplexer means actuatable by an output of said timing means during an interval in which image data is not being displayed by said display means, to read out signals indicativeof the movements of said joy stick and applying same to said addressable storage means.
40. A data processing and display system for transferring data between said system and a data storage unit, the data storge unit storing a set of characters from which a plurality of composite images may be formed, image data identifying thearrangement of the characters to form a desired image, and color information identifying a palette of colors from which the characters may be colored, said system comprising:
(a) color display means for displaying images of a selected arrangement of characters chosen from the set and the characters colored with selected colors from the palette;
(b) means for reading data from the data storage unit;
(c) addressable storge means coupled to said reading means for receiving and storing data derived from the storge unit indicative of the set of characters and the palette of colors; and,
(d) display control means for first addressing the image data in a first portion of said addressable storage means to obtain a first readout, and secondly for using the first readout data for addressing a second portion of said storage means toobtain signals indicative of the character color, said display control means being coupled to said color display means to apply the character signals to be displayed by said color display means.
41. A data processing and display system for transferring data between said system and a data storage unit, the data storage unit storing a set of characters from which a plurality of composite images may be formed, image data identifying thearrangement of the characters to form a desired image, and color information identifying a palette of colors from which the characters may be colored, said system comprising:
(a) color display means for displaying images of a selected arrangement of characters chosen from the set and the characters colored with selected colors from the palette;
(b) means for reading data from the data storage unit;
(c) addressable storage means coupled to said reading means for receiving and storing data derived from the storage unit indicative of the set of characters and the palette of colors; and
(d) display control means comprising timing means for developing timing signals for facilitating the display of characters upon said display means and for providing and applying first address signals to a first portion of said addressable storagemeans to obtain a first readout, and secondly for using the data of the first readout and the timing signals and being coupled to said addressable storage means to provide and apply a second address to a second portion of said addressable storage meansto obtain a second readout in the form of signals indicative of the character color, said color display means being coupled to said display control means to apply the character signals to be displayed by said color display means.
42. The system as claimed in claim 41, wherein said color display means displays the colored image in a raster format comprised of a series of characters disposed in a text line with a plurality of the text lines forming an image upon thedisplay means, each character comprised of a plurality of raster lines, and said timing means comprising a counter for counting the number of raster lines within a given character, and using the output of said raster counter and the first readout data toform the second address to said second portion of said addressable storage means.
43. The system as claimed in claim 41, wherein said color display means displays the colored images, each comprising an arrangement of the characters, each character comprised of a plurality of incremental areas, and said timing means using dataindicative of the current incremental area of a character being displayed by said display means and the first readout data to form the second address for addressing said second portion of said addressable storage means.
44. A data processing and display system comprising:
(a) display means for displaying images of a selected arrangement of characters each chosen from a set of characters;
(b) a control processor for controlling said system;
(c) addressable storage means for storing data corresponding to the set of characters;
(d) display control means including timing means;
(e) a data bus coupled to each of said display means, said addressable storage means and said control means whereby data may be applied therealong to each of said aforementioned means and control processor;
(f) an address bus coupled to each of said display means, said addressable storage means, said control processor, and said display control means; and,
(g) said timing means of said display control means operative in a first time slot to provide address signals via said address bus to said addressable storage means, whereby at least one of said characters is transferred via said data bus to saiddisplay means to be displayed thereon, and operative in a second distinct time slot which enables said control processor to address said storage means and transmit signals via said data bus to at least one of said above-recited means of said system.
45. The data processing system as claimed in claim 44, wherein said addressable storage means comprises a first portion for storing image data identifying the order and arrangement of the characters to form the desired image upon said displaymeans and a second portion for storing the set of characters, and said timing means generating within the first time slot a first address signal to be applied via said address bus to said addressable storage means to obtain a first readout andthereafter, generating a second address using the first readout data to be applied via said address bus to said addressable storage means, whereby the character so read out is applied via said data bus to said display means to be displayed thereby.
46. A data processing and display system comprising:
(a) color display means for displaying images of a selected arrangement of characters chosen from a set of characters with the characters colored with selected colors from a selectable palette of colors;
(b) image source means for applying to said color display means encoded signals indicative of a series of the characters to said display means to be displayed thereby;
(c) addressable color memory means for storing the palette of colors from which the characters are to be colored the encoded signals being indicative of an addressable location of said color memory means for storing a selected color of thepalette; and
(d) display control means for facilitating the display of the characters upon the color display means and for applying address signals to said addressable color memory means, whereby the selected color is read out from said addressable colormemory means and applied to said color display means to color at least a portion of a character being displayed thereon.
47. The data processing and display system as claimed in claim 46, wherein said source of character data comprises a second addressable storage means.
48. The data processing and display system as claimed in claim 47, wherein said second addressable storage means includes a first portion for storing image data identifying the arrangement and sequence of the characters to form an image thereofon said color display means and a second portion for storing image data indicative of each of said characters, and said display control means provides a first address signal to said first portion of said second addressable storage means to obtain areadout thereof and using the readout to form a second address to a second portion of said second addressable storage means to read out the selected characters to be applied to said display control means, whereby the characters are ordered and arrangedto form the desired image.
49. A data processing and display system comprising:
(a) display means for displaying an image comprising selected of a plurality of symbols;
(b) a plurality of symbol generators, each for applying symbol data indicative of a distinct symbol to said display means to be displayed thereby; and
(c) priority means coupled to each of said plurality of symbol generators for assigning priorities to each of said symbol generators and responsive to the occurrence of the generation of symbol image data from more than one of said plurality ofgenerators to apply only that image data from said generator of highest priority to be displayed by said display means.
50. The data processing and display system as claimed in claim 49, wherein there is included display control means for applying control signals to said display means to display an image thereon in the form of a series of scan lines formed in araster, and said priority means for ensuring that only one symbol image data of the image is applied to be displayed at one point in a line, in accordance with the priority assigned thereby to each of said signal generators.
51. A data processing and display system comprising:
(a) color display means for displaying images of a selected arrangement of characters selected from a set of characters;
(b) addressable storage means having a first portion of variable size for storing image data identifying the order and arrangement of the characters to form a desired image upon said display means, and a second portion of a size varying inverselyto that of said first portion for storing the set of characters; and,
(c) display control means for selectively addressing said first portion to obtain a data readout, and using the data readout to address said second portion and to readout the set of characters in a desired configuration to be applied to saiddisplay means to provide a desired image, and for setting the size of said characters, thereby determining the sizes of said first and second variable portions of said addressable storage means.
52. The data processing and display system as claimed in claim 51, wherein a character is comprised of a given number M of raster lines and is arranged in a pattern comprised of N text lines of characters, said display control means settable toreceive varying numbers of M raster lines and N text lines.
53. The data processing and display system as claimed in claim 52, wherein the size of said first portion is increased as the number N of text lines is increased and the number M of raster lines is decreased, and the size of said second portionis inversely decreased. .Iadd.
54. A data processing and display system for displaying on a color display means an image of an arrangement of characters selected from a set of characters and colored from a palette of colors where the image is stored as image data inaddressable memory locations, the system including a display control means for first addressing the image data in a first portion of the addressable memory locations to obtain a first readout indicative of a character to be displayed, and secondly, forusing the first readout data for addressing a second portion of said addressable memory locations to obtain signals indicative of the character color, said display control means being coupled to said color display means to apply the character signals tobe displayed by said color display means. .Iaddend. .Iadd.
55. A data processing and display system for displaying an image of an arrangement of characters selected from a set of characters which are colored from a palette of colors, said system comprising:
(a) a color display means for displaying the image;
(b) an addressable storage means for storing data signals indicative of the set of characters and of the image to be displayed; and
(c) a display control means for first addressing the data in the first portion of said addressable storage means to obtain a first readout, and secondly for using the first readout data for addressing a second portion of said storage means toobtain signals indicative of a character to be displayed and of its color, said display control means also being coupled to said color display means to apply the character signals to be displayed by said color display means. .Iaddend. .Iadd.
56. A data processing and display system for displaying an image of an arrangement of characters selected from a set of characters which are colored from a palette of colors, said system comprising:
(a) a color display means for displaying the image;
(b) an addressable storage means for storing data signals indicative of the set of characters and of the image formed from a selection of characters chosen from the set; and
(c) a display control means comprising timing means for developing timing signal for facilitating the display of characters upon said display means and for providing and applying first address signals to a first portion of said addressablestorage means to obtain a first readout, and secondly for using the data of the first readout in the signals and being coupled to said addressable storage means to provide and apply a second address to a second portion of said addressable storage meansto obtain a second readout in the form of signals indicative of a character to be displayed and of its color, said color display means being coupled to said display control means to apply the character signals to be displayed by said color display means. .Iaddend. .Iadd.57. A color graphics display generating circuit for use with a color raster-scan video display unit to generate a color image having a selected arrangement of symbols selected from a plurality of symbols where each symbol is coloredfrom a palette of colors, the circuit comprising:
(a) a plurality of addressable image memory location for storing image generating data which includes information for generating image memory addresses;
(b) a plurality of addressable color memory locations for storing color generating data to generate selected colors from the palette of colors, said addressable color memory locations outputting color generating data in response to indirectmemory addresses generated from said image generating data; and
(c) a video timing and control means for generating first and second addresses to said addressable image memory locations, and responsive to the image generating information outputted therefrom, for generating addresses to said addressable colormemory locations whereby an image is generated on the video display device as an arrangement of symbols colored from the palette of colors. .Iaddend. .Iadd.58. A system for displaying on a raster-scan color video display unit an image comprised of aselected arrangement of characters and/or graphic symbols colored from a palette of colors, where the image is stored as image generating signals in an addressable memory, the system including:
(a) a color memory for storing color generating signals to generate selected colors from the palette of colors, said color memory outputting color generating data in response to image generating signals outputted from said image memory; and
(b) a timing and control means synchronized to the scanning of the video display unit for generating first and second memory addresses to the image memory, and responsive to the image generating signals output therefrom in response to said firstand second memory addresses, for generating addresses to said color memory whereby the image is generated on the color
video display device. .Iaddend. .Iadd.59. A color graphics display system for displaying an image having position therein, comprising:
(a) a plurality of symbol generators, each for supplying symbol generating data representative of a distinct symbol to be displayed at a position in said image; and
(b) a priority means coupled to each of said plurality of said symbol generators for assigning priorities to each of said symbol generators, whereby the symbol displayed at any given location in the image is determined according to the highestpriority among those symbols which are to be displayed at the given position..Iaddend. |
| Description: |
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and in particular to such systems capable of displaying images, as upon a cathode ray tube, in accordance with any of a variety of programs as stored upon a low-cost, limited capacity storage unit suchas a tape cassette, and capable of viewer interaction to control the selection of the displayed image as well as to store data upon the storage unit.
2. State of the Prior Art
There is presently known in the art the adaptation of a television receiver to play a number of games, e.g. a paddle-type game where one or more players operates control sticks to cause the image of a ball to move repeatedly from side to side asthe players manipulate the displayed paddle to intercept the ball and to return it to the opposing player. Typically, these systems are implemented in hardware game circuitry including, for example, a power supply and an oscillator producing a mastertiming signal for the TV display system. A horizontal sync circuit provides a clock frequency into clock submultiples, which are variously combined to generate reset, blanking and sync signals. A vertical sync circuit provides a horizontal reset intovertical submultiples for combination into vertical reset, blanking and sync signals. The two sync signals usually are combined into a composite sync signal that synchronizes the data display of the receiver's cathode ray tube (CRT) with the gamecircuitry. A stationary image is displayed upon the CRT that makes up the background as generated by a playfield display section. The remaining images are generated by an object display circuit and moved around at various speeds by horizontaldeflection and motion circuits, which are coupled to the aforementioned sync circuits. A score occurs when a ball is not returned and an appropriate signal is generated and applied to a storage circuit which counts each such unreturned ball and controlsa display circuit to present the correct scores upon the CRT. Typically, there also is included a game length circuit in the form of a timer or a score counting circuit that has a time limit or the number of points scored, to disable the game circuitry. Further, a sound circuit is provided including an appropriate amplifier and speaker, whereby appropriate game-like sounds, e.g. the ping and pong of a ping-pong ball striking a paddle, are provided upon the occurrence of a ball hitting the displayedpaddle and also to indicate the scoring of a point.
A variety of such games has been implemented by integrated circuits and are adapted to display, as upon a television CRT, games such as tennis, hockey featuring a goalie and a forward for each side, squash, practice one-man squash, and a varietyof rifle-shooting games. As development of such games has proceeded, the control circuitry has become increasingly sophisticated, whereby the difficulty of the games may be varied. For example, the size of the bat or racket, as well as the ball speed,may be changed. Further, the angles of return from the paddle or racket may be changed to increase the difficulty of the game. In addition, ball service may be automatic or manually-controlled, whereby the players can control how the on-screengenerated ball is put into play after each point is scored. In a rifle-shooting game, a manual control in the game circuitry initiates the movement of a target upon the CRT screen, and a rifle in the form of a light source is aimed at the target. Whenthe rifle's trigger is pulled, a shot counter in incremented. If the rifle is on-target, the rifle light source as focused upon a photocell inidicates a hit and the output from the photocell is applied to a hit counter which is incremented, andthereafter a hit noise is generated and the target is blanked for the duration of the hit signal. After fifteen shots, the score appears on the screen to indicate the total shots and the number of hits.
In more recent developments, such games have been adapted for display upon color CRT's, and have included large-scale integrated circuits that first process the color or chroma information to be applied in a format similar to that of abroadcasted color TV signal. Basically, the color signals are treated as two vectors defined by the blue (B-Y luminance) and red (R-Y luminance) as provided by an integrated circuit chip that includes a series of field-effect transistor switches and aresistor matrix. The integrated circuit chip also includes logic that is programmed to produce appropriate colors in any portion of a line then being scanned. By controlling the switching matrix, two separate voltages are produced, corresponding to theB-Y and R-Y vectors that are programmed to produce a desired color signal. The two vectors are applied to a chroma modulator having a stable color transmission frequency provided by a 3.58 MHz crystal oscillator; in this manner, the color signal isphase-modulated and transmitted to the color CRT receiver.
It is contemplated that most of the above-described games are implemented by "hard-wired circuitry", taking the form of large-scale integrated circuits. The level of their sophistication is relatively low and permits only a limited amount ofadaptability as determined by the configuration of the game's control circuitry. In this regard, it is contemplated that presently-available microprocessors could well be adapted to such game systems whereby a variety of more sophisticated games couldbe played with circuitry implemented by a microprocessor. At present, there is available such a game including a microprocessor, a static memory interface, a read-only memory (ROM) and a random-access memory (RAM) including a light-emitting diodedisplay whereby a game of chess may be displayed. In addition, such a game may be readily adapted to show the board and chess pieces upon a conventional CRT display. By the use of the increased sophisication provided by the microprocessor, each playerin the game is able to control the move of each piece by pressing control keys specifying and entering the "from" and the "to" squares in terms of ranks and files, giving the coordinates of each square. The counter move is determined by themicroprocessor and is initiated by the player pressing the designated key, thus instructing the processor to analyze the move and to respond thereto. Significantly, the degree of complexity in responding to the player's move may be changed to a varietyof levels. The higher the level, the more time the processor requires to respond.
In addition, a microprocessor has been adapted to be used in a "gunfight" game wherein two figures are displayed on the CRT screen and the players try to shoot each other by viewer input to maneuver the displayed image on the screen and pressingtrigger controls. In such a game, the microprocessor is adapted for use with a CRT, by storing image data indicative of the gunfighter as well as background images, in a relatively large random-access memory and reading out the image data, whileconventional horizontal deflection circuits generate the raster of the CRT. In an illustrative format, the pattern on the screen is composed of 224 horizontal lines, each being 256 dots long, whereby the RAM holds 224.times.256 bits of information,which are sequentially read out during the scanning process. Further, it is contemplated that the game that the program plays may be changed by storing game information upon a storage means in the form of a cartridge or tape cassette, thus providingflexibility with respect to a fixed game as implemented by hard-wire LSI circuits.
The above-described system, whether implemented by conventional circuitry, LSI circuits or microprocessors, have been limited to a great extent to playing games, even though at increasing levels of sophistication. It is contemplated by thisinvention to provide a computer system illustratively implemented by a microprocessor, that is capable of many different functions, only one of which relates to playing a game, involving images to be displayed upon a cathode ray tube. In this regard,there are many applications besides the playing of games, where such systems would have application, such as a "home computer", capable of performing many functions within the home. For example, a computer could be used to store information such asChristmas lists or telephone numbers. A further contemplated application of such a system would be as an educational device that could be used in schools or in the home to teach children or adults. In addition, such a system could be used in business,for recordkeeping or for teaching purposes. The applications for such systems are limitless and the introduction of flexibility into the previously game-oriented systems would permit the basic components of these systems to be used in a great number ofdifferent applications.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a computer system capable of being adapted by the input of program data from a limited storage unit, such as a cartridge or cassette, to a great number of different applications.
It is a further object of this invention to provide data by viewer input, whereby the program material displayed by the system's display means is changed.
It is a further object of this invention to provide a computer system, wherein there is included viewer input means whereby the viewer's response may be written onto the limited storage unit, e.g. a tape cassette, which stores the program dataincluding control and image data.
In accordance with these and other objects, there is provided a computer system including a control means, illustratively in the form of a microprocessor, a color display means in the form of a color CRT, means for receiving a limited storageunit such as a tape cassette, means for reading and writing data from and to the storage unit, and viewer input means in the form of a control stick and/or keyboard whereby the viewer may readily respond to the images displayed upon the display means,making entries to the system through the viewer input means, whereby the images displayed are controlled thereby in accordance with a program of data stored upon the limited storage unit and/or for writing data via the input means upon the storage unit.
More specifically, the computing system further includes a memory in the form of a random-access memory (RAM), whereby control data, and image and audio data may be read out from the limited storage unit to be stored therein, for use in forming avariety of images to be displayed by the CRT, under the control of the control data program as stored upon the limited storage unit. In this regard, it is contemplated that the images are displayed in color and that various portions of the image may bevariously colored as determined by the program data as stored upon the limited storage unit.
Color or chroma data is supplied from the limited storage unit in terms of control data to the RAM, whereby the color of various portions of the displayed image may be changed periodically in accordance with the control program data as derivedfrom the limited storage unit. A set or plurality of selected colors from a larger number thereof of which the system is capable of reproducing, is transferred from the storage unit to the RAM and then is transferred from the RAM to be stored in asuitable color memory in the color processing circuit whereby the image then being displayed may be selected from that set of colors. If it is desired to display a different image with different colors, a new set of colors may be loaded into RAM 16 tobe transferred from there to the color memory and new image data may also be loaded into the RAM 16, all under the control of the program control data.
Further, the image formed is formed in a first or text mode of operation, of a plurality of "characters" that are assembled in accordance with the control data. In this fashion, the limited storage unit can provide the basic data in the form ofa set or library of characters to the RAM, which are selectively read out and applied through a color processing circuit to the color CRT whereby a variety of color images may be displayed from a limited amount of data. In particular, indirect addressesare provided from a timing system and applied to a first portion of the RAM. During display, the indirect addresses are read out and applied to a timing circuit, whereby data indicative of the vertical line position of the CRT are applied thereto, toprovide new addresses, which are used to read out from a second portion of the RAM a series of characters in terms of dot patterns, to control the display of images upon the color CRT. Thus, a limited number of characters may be assembled to form avariety of images.
In a second or paint mode of operation, the timing system provides first and second direct addresses to the RAM, whereby image data including color pointers identifying the color to be painted upon the display screen of the color CRT, isdetermined. In an illustrative embodiment of this invention, the second address is formed by shifting within the timing system the binary data of the first address to form the second address and applying same to the RAM to read out additional image datato be combined with the first readout of data from the RAM, to obtain a complete set of color pointers or addresses to read out the selected color from a color memory.
In a further aspect of this invention, the viewer may write in data to the computing system to be appropriately interpreted by the control data and to be stored in the RAM, then to be transferred from the RAM via the read and write means to thelimited storage unit. In this way, a library of information, such as a Christmas address list or personal business records, may be stored upon the storage unit to be used at a subsequent time. As a further modification of this aspect, the input devicemay form a keyboard having an overlay especially coordinated with the program data derived from the selected limited storage unit, e.g. the interpretation of the input from the keyboard is dependent upon the particular program data.
In a further aspect of this invention, a set of software programs is stored into a ROM associated with the microprocessor whereby various operations of the computing system are controlled thereby. For example, a program is developed forunloading the program data from the limited storage unit into the RAM and for initiating the execution of the program data. In this regard, it is contemplated that control data in the nature of utility subroutines, e.g. tape loading and searching, audiosynthesis, keyboard scanning and computation by the computing system, also may be stored in the ROM, to be selectively read out therefrom; thereafter, these stored subroutines are used in accordance with the control data of that particular program. Inthis fashion, the control data stored upon the limited storage medium may be minimized, in that a set of the control data common to a number of programs is stored in the ROM.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of the present invention will become more apparent by referring to the following detailed description and accompanying drawings, in which:
FIG. 1 is an overall schematic diagram in block form of the computer system of this invention;
FIG. 2 is an illustration of the makeup of a displayed image as composed by the computer system of FIG. 1;
FIGS. .[.3A-3J.]. .Iadd.3A to 3H and 3J .Iaddend.and 4A-4E variously show the timing signals as developed by a timing system as shown in FIG. 1, for timing the transfer of various data within the system of FIG. 1;
FIGS. 5A .Iadd.to 5C.Iaddend., and FIGS. 6A, B, C, D and E and FIGS. 7A and 7B, respectively show the color processor of FIG. 1 in the form of a functional block diagram, and a schematic of the detailed circuit elements thereof, whereas FIGS. 5Band 5C show, respectively, the configuration of a character, and the display of information upon a CRT.
FIGS. 8 and 9A, B and C are, respectively, schematic drawings of the symbol generator as shown in FIG. 1, in the form of a functional block diagram and in the form of a detailed circuit schematic;
FIGS. 10 and 11 show schematic drawings of the keyboard and the control stick and its associated circuitry, in the form of a functional block diagram and in the form of a detailed circuit schematic, respectively;
FIGS. 12 and 14 are functional block diagrams of the cassette interface circuit as shown in FIG. 1;
FIGS. 13A, B and C 15, 16, 17 and 18 are detailed schematic drawings of the cassette interface circuit as generally shown in FIGS. 12 and 14;
FIGS. 19 and 20 are, respectively, a graphical showing of the electrical signals as developed in the circuits of FIGS. 17 and 18;
FIGS. 21 and 22A and B, 23, 24, 25 and 26 are schematic drawings of the audio circuit of FIG. 1, in the form of a functional block diagram, and of detailed schematic drawings, respectively;
FIGS. 27A and 27B, and 28A and 28B and 29, are schematic drawings of the timing system as shown in FIG. 1, in the form of a functional block diagram and in the form of detailed schematic circuit drawings, respectively; and
FIGS. 30 and 31A, B and C are, respectively, a functional block diagram and a detailed schematic drawing of the random-access memory (RAM) and its associated interface circuitry, as more generally shown in FIG. 1.
DETAILED DESCRIPTION OFTHE PREFERRED EMBODIMENT
In the following, the computer system 10 will first be described in a general fashion as to its components and operation, with respect to FIG. 1. Thereafter, an illustrative number of applications for this computing system 10 will be provided interms of the games, educational programs and personal programs that may be adapted for this system. Thereafter, each of the components or component systems making up the computing system 10 will be first described in terms of a functional block diagram,which will be related to a detailed circuit diagram thereof. As shown in FIG. 1, the computer system 10 includes a microprocessor (.mu.P) 12 and an associated ROM 14, wherein a variety of programs may be stored to assist in the control of the data to bedisplayed. Illustratively, the ROM 14 may receive programs related to the loading of data (program "LOAD"), the energization of the system 10 (program "POWER ON"), the formation of images (program "ARTWORK") and routines for performing various computingfunctions (program "ARITHMETIC").
General Description of the Components of the Computing System 10
With regard to the drawings and in particular to FIG. 1, there is shown the computer system in accordance with the teachings of this invention, capable of receiving data from a limited storage unit 29, illustratively taking the form of a tapecassette that is coupled to an interface circuit 28 (see FIGS. 12 and 13 for details thereof) for reading and writing data to and from the storage unit 29; further, the interface circuit directs data to and from the computer system 10 and in particularto a memory 16 in the form of a random-access memory (RAM). As will be explained in detail later, the data stored upon the limited storage unit 29 defines the type of program to be processed by the computer system 10 and may illustratively comprise anyof a large variety of programs including games, educational presentations including viewer feedback, storage of information such as Christmas address lists or telephone numbers, etc. More specifically, the data stored upon the storage unit 29 controls inpart the operation of the system 10 and further includes data as to the composition and color of images to be displayed by the system's display means in the form of a color CRT 34. Further, the data as stored by the unit 29 includes data for controllingat least parts of the control processes or steps carried out by the computer system 10.
The control and in particular the timing of the computer system 10 is determined by the timing system 18, which generally controls the transfer of information between various of the components of the computer system 10 as shown in FIG. 1, and inparticular provides addresses via a multi-port RAM address bus 24 to the RAM 16, whereby selected portions of the RAM 16 are addressed, to read out data therefrom or to store data therein from a bi-directional input/output (I/O) data bus 22 thatinterconnects the operating components of the computer system 10. As will become clear from further explanation, the computer system 10 is a multiplexed system wherein the transfer of data and the subsequent control operations are effected in a timedsequence, with each such data transfer or control step occurring in a sequenced time slot. In particular, the timing system 18 controls the multiplex timing in accordance with the display of images upon the CRT 34 at a horizontal rate set at 15,720horizontal lines per second, and a vertical rate of 60 Hz. In particular, the transfer of data, as seen in FIGS. 3 and 4, between the various components of the computer system 10 occurs in the vertical and horizontal blanking periods imposed upon theCRT 34.
Further, the timing system 18 controls the transfer of data indicative of the image from the RAM 16 to a color processor 32, whereby a series of dots is displayed, with corresponding color or chroma information, upon the CRT 34 to provide a colorimage thereon. As seen in FIG. 1, timing information in the form of clock trains indicative of the horizontal lines, and vertical dots and characters as displayed upon the CRT 34, are applied via a timing bus 26 to the components of the computer system10, to energize tristate drivers associated with each of the components, whereby data upon the I/O data bus 22 commonly connected to these components, is selectively applied to one of the components of the computer system 10, at its multiplexed, timedslot.
As shown in FIG. 1, the color processor 32 receives image data in a dot-by-dot fashion, as read out from selected portions of the RAM 16 to be sequentially displayed as the cathode ray beam is scanned in a vertical and horizontal raster patternby the CRT 34. Further, as will be explained in detail later, the color processor 32 stores a plurality of color or chroma data signals, from which the various portions of the displayed image may be variously colored. Thus, at the time of display, aselected color is imposed by the color processor system 32 onto a particular dot as it is then being displayed. Further, the set of colors as stored within a color memory of the color processor 32 may be selectively changed from time to time so that thenext, subsequently displayed image may be formed of a different set of colors. In this regard, the color data is first programmed and stored in the storage unit 29, and is subsequently read out therefrom and stored in the RAM 16 so that the color of theimages displayed by the CRT 34 may be changed subsequently and a new set of colors selected from a relatively large library of possible colors. In particular, the color processor 32 includes a color memory (to be described) capable of storing a finitenumber of colors, e.g. eight, from which the colors for a given frame or colored image may be chosen. However, the system is capable of reproducing a larger library of colors, for example sixty-four colors, and the programmer selects eight of thepossible sixty-four colors to color the various areas of a particular image or frame of video information, by programming the storage unit to color the frame with the eight designated colors. In this regard, it is understood that the programmer mayselect further sets of colors from which subsequent frames or images of video information may be colored.
Special characters or symbols are applied selectively to and displayed by the CRT 34 in connection with games or various other presentations that may be displayed upon the system 10. In particular, in a war-type game, an image of a tank could beprogrammed into one of a plurality of the symbol generators 20 so that upon command, that image could be read out and applied via the color processor 32 to be displayed by the CRT 34. Further, a cursor symbol in the form of an arrow could be stored inanother section of the symbol generators 20 and read out at appropriate times. Viewer input or reaction to the data displayed upon the CRT 34 is transmitted into the system 10 via the keyboard and/or stick control 30. Illustratively, two or morecontrol or joysticks are provided with the computer system 10 and are capable of viewer manipulation. In addition, a keyboard in the form of a matrix of conductors which may be selectively depressed is provided, over which an overlay designating variousfunctions in terms of control of the system or of data input, may be disposed over the matrix of conductors. It will be apparent that the overlay is dependent upon the program derived from the storage unit 29 and that various control functions as wellas data input may be effected by the same keyboard, dependent upon the response made thereto by the control data as dnetered into the RAM 16 from the storage unit 29.
Further, an audio circuit 58 is provided, whereby various audio signals, including voice and special effects, may be applied to a speaker 59 in coordination with the image displayed by the CRT 34. For example, in the presentation of aneducational program, there typically would be a series of images displayed upon the CRT 34 presenting educational material in conjunction with a voice track explaining same. In other instances, especially where a game is involved, special effects inconjunction with the game are made; for example, if a war game were programmed by the storage unit 29, special effect generators within the audio circuits 58 are programmed to generate corresponding sounds, e.g. the sound of exploding munitions.
The computer system 10 is under the control of a control processing unit in the form of the microprocessor 12, as manufactured by the assignee of this invention under its designation PPS-8 and further described in its publication entitled,"Microcomputers", Document No. 19480N40, March 1975, to receive instructions from its associated memory in the form of the read-only memory (ROM) 14 or the RAM 16, to perform various logical and mathematical operations and to act as a central controlunit for the entire system 10. As shown in FIG. 1, the microprocessor 12 is connected via a microprocessor address bus 40 and a microprocessor instruction/data bus 42 to the ROM 14, which is a 2048.times.8 bit dynamic ROM having a capability of storing16,000 bits. In an illustrative embodiment of this invention, the ROM 14 may be that ROM as manufactured by the assignee of this invention under their designation A52XX. Further, the RAM 16 may in one preferred embodiment of this invention take theform of a RAM as manufactured by Texas Instruments Corporation under their designation TMS-4050, or that RAM as manufactured by the assignee of this invention and described in a publication entitled, "4096.times.1 Bit Dynamic Random-Access Memory". Themicroprocessor 12 performs mathematical and logical operations on eight bits of data in its accumulator, sending out control signals via the RAM 16 to the color processor 32 and also to the audio circuit 58. In addition, the microprocessor 12 scans oractivates the keyboard and/or control stick 30 to interpret viewer input and based upon its control operation, sends appropriate signals in eight-bit bytes to the RAM 16 via the address interface 36 and the data interface 38. It is contemplated that inalternative embodiments of this invention, the microprocessor 12 could communicate directly with the components of this system without being transferred via the RAM 16.
As will become clear from the discussion below, the timing circuit 18 generates vertical and horizontal count signals indicative of the position along the horizontal line being scanned upon the CRT 34, as well as the vertical position of the CRTscan, and uses such counts as addresses to access various portions of the RAM 16. In particular, the horizontal count signals are applied via the timing bus 26 from the timing system 18 to a horizontal input/output circuit 54 which acts as an interfacebetween the timing circuit 18 and the RAM 16 to address data to be applied vai the memory data bus 22 to the cassette interface circuit 28, the symbol generator 20 and the color processor 32, typically during the horizontal retrace period. In somewhatsimilar fashion, the vertical count signals are provided by the timing circuit 18 via the vertical input/output circuit 56 via the RAM address bus 24 to the RAM 16, whereby the address of data within the RAM 16 corresponding to data to be transferred tothe keyboard and/or control stick, the symbol generators 20 and the color processor 32 is effected, typically during the vertical retrace period. Further, as seen in FIG. 1, a raster preset signal identifying the number of raster lines M (as will beexplained), as developed by the color processor 32, is applied via the bus 57 to the timing system 18.
General Description of the Operation of the Computing System 10
The computing system 10 as generally illustrated in FIG. 1 displays, as a part of its operations, an image upon the CRT 34 by scanning the CRT in a rather conventional horizontal and vertical fashion. The timing system 18 provides timing signalsalong the timing bus 26 to the components of the system 10 in a locked fashion, whereby each component is enabled to transmit data via the input/output data bus 22 at a selected interval or time slot within a recurring time framework synchronized to theraster scanning of the color CRT 34. Generally, image data signals in the form of data are read out from the RAM 16 and transferred to the color processor system 32 during those time portions of the horizontal scan of the CRT 34. During the horizontaland vertical retrace intervals, data is transferred between the RAM 16 and the various other components of the system 10. It is understood that during the entire time period of operation, time slots in the locked system are provided for transmittingsignals from the microprocessor 12 via the RAM 16 to the various components of the system 10 under its control.
An understanding of the locked timing operation will become more evident in view of a description of the manner in which images are formed upon the display screen of the CRT 34, with respect to FIG. 2. As will become clear from a furtherdescription, the color processor 32 may be operated in a first or text mode, or in a second or paint mode. In the text mode, images are displayed upon the display screen of the CRT 34 in terms of a plurality of characters, marked as shown in FIG. 2 bythe letter "C", an entire image of characters being formed by N text lines of characters, each row of characters having 32 characters therein. In an illustrative embodiment, N may equal 16. As seen in FIG. 2, each character is composed of an array ormatrix of dots, six dots wide by M raster lines high. It is understood that the number of raster lines M within a given character C, and thus the number of text lines N within a given image, may be varied dependent upon the data to be displayed. Forexample, if the amount of data and thus the detail of the image is to be increased, the number of raster lines M per character C is decreased, thus increasing the number of text lines N, with the number of horizontal lines being kept a constant, e.g.about 192 scan lines. As will be explained generally with respect to FIG. 1, a given program, as is stored upon the cassette storage unit 29, contains a plurality or library of characters or symbols C, from which a plurality of images may be formed. Inthe process of displaying a given image, the characters are selected from the library and are arranged in rows and columns as shown in FIG. 2 to form the desired image. Generally, this selecting process is performed by using a set of indirect addressesthat are read from the RAM 16 and applied via the I/O data bus 22 to the color processor 32, whereat data as to the vertical position of the then current position of the electron beam scan of the CRT, is added to the indirect address. The indirectaddress identifies a particular character of the library of characters from which the image is to be displayed and when modified with data according to the vertical position, is reapplied via the timing system 18 and the RAM address bus 24 to the RAM 16to read out a pattern of dot signals to be stored in the color processor 32. The pattern of data signals according to the selected characters is applied to the CRT 34, whereby as its beam is scanned across its face, it is modulated to produce acorresponding series of dots of the image in consecutive order across a horizontal line of the CRT scan. As shown in FIG. 2, each character "C" and as illustrated, character C31 indicating the first character in the third row, includes, as does eachcharacter, a pattern of dots formed of M raster lines, for example 12, each line having six dots. With such a format, the entire image is formed of N times M lines, for example 192, each line having 192 dots therein. In particular, by scanning thefirst line of the image as shown in FIG. 2, the first six dots are determined by character C11, the next six dots of the first line are determined by the dots of character C12, and so forth, the last six dots being determined by the characters C1, 32. In this fashion, the 192 X (M X N) dots are determined in accordance with the selected pattern of characters C. In an illustrated embodiment of this invention, the CRT 34 is scanned at a rate of 15,720 lines/second, with a vertical rate of 60 Hz, with adot size of approximately 252 nanoseconds.
In the second or paint mode of operation, the image is made up of square arrays, as shown in FIG. 5B, each array comprised of three squares. Each square is comprised illustratively of a dot matrix, illustratively two dots wide and three rasterlines high. In this mode of operation, the timing system 18 provides direct addresses to the RAM 16 during first and second look-ups to provide data in the form of three color pointers, one for each of the three squares or dot patterns of the squarearray as seen in FIG. 5B. Each color pointer identifies the color for which its square is to be colored and in effect provides an address within the color memory of the color processor 32 from which that color may be addressed and read out, to beapplied to the color CRT 34.
The operation of the computing system 10 as shown in FIG. 1 will become clearer as an explanation of the timing signal diagrams of FIGS. 3 and 4 is given. The timing system 18 includes a master clock for providing a master clock signal as shownin FIG. 3A, at a rate of 3.96144 MHz, from which the various other timing signals of the system 10 are developed, as will be explained in greater detail with respect to FIGS. 27A and 27B. From the master signal, horizontal and vertical control signalsare developed by the timing system 18 and are applied via the color processor 32 to control the scan of the CRT 34. Within the timing system 18, there is a character counter synced with the master clock for providing six clock signals, as seen in FIG.3F, which are used to variously address the RAM 16, as will be explained, and also to time the various operations of the system 10. The train of pulses of FIG. 3F1 defines the time slots for the display of a series of characters as illustrated in FIG.2. As seen in FIG. 3F, there are 32 characters, beginning with character 1 and proceeding through character 32. In FIG. 3G, there is indicated a first dot pattern of six dots (corresponding to the first character), whereas at time slot 32, the last dotpattern or character is indicated. As FIG. 3F illustrates, there are ten additional time slots, i.e. 32 to 41, provided during the horizontal retrace period, as indicated by the blank signal going high, as illustrated in FIG. 3G. During the horizontalblanking period, the timed lock system provides for the transfer of data between selected components of the system 10. Since, as shown in FIG. 1, the components are tied to a common I/O data bus 22, the components must be selectively connected theretoin a timed, locked manner.
Reference is made to FIG. 3H, where the time slots for data transfer are specifically shown. In particular, the designation "CHAR" that occurs during the horizontal scan of the CRT 34, indicates that the RAM 16 is being addressed via the RAMaddress bus 24 to read out data corresponding to one of the characters C, whereby that data is transferred via the I/O data bus 22 to the color processor 32. Subsequently, a second look-up of the RAM 16 occurs, whereby the indirect address firstprovided during the CHAR period, is processed by the color processor 32, to be applied via the timing bus 26, the timing system 18 and the RAM address bus 24 to address a second portion of the RAM 16 to read out a pattern of dots, during the "DOT" timeperiod. As shown in FIG. 3H, between successive sets of "CHAR" or first look-up, the "DOT" or second look-up, a time slot PPS is provided, during which address signals from the microprocessor 12 are transmitted to ROM 14 and RAM 16 to address datatherein.
During the horizontal retrace period when no images are being displayed upon the CRT 34, the dot patterns of special characters as may be desired to be displayed upon the CRT 34, are transferred from the symbol generator 20 via the data bus 52 tothe color processor 32, wherein they are stored for use at selected points in the scan of the CRT 34, whereby various special images may be displayed. For example, in the display of a war game, it may be desired to provide an image of a tank. Inanother instance, it may be desired to provide a cursor or arrow symbol in the display. As illustrated in FIG. 3H, there are eight different time slots, beginning with SGO DOTS through SG7 DOTS, during which up to eight sets of dot patternscorresponding to eight different special characters may be transferred to the color processor 32. Further, at regular periodic intervals during the horizontal trace, time slots PPS are provided for transferring of control signals from the microprocessor12 via the RAM 16 to various of the components of the system 10. Further, time slots "tape data in" and "tape data out" are provided for transferring data as read from the tape storage unit 29 to be stored in the RAM 16, and for writing tape via thecassette interface circuit 28 onto the tape storage unit 29, respectively. Thus, the viewer can respond selectively to the image displayed by the CRT 34, to write desired data via the keyboard 30 onto the tape storage unit 29. Further, there isprovided by VER SCAN I/O slot, during which data as input by the viewer is transferred via the stick control 30 into the RAM 16. After the horizontal blanking period, the first look-ups occur during the CHAR and DOT time slots to display the first sixdots of the first character of the next line.
Thus, the time slots as shown in FIG. 3H define the periods in which the corresponding components of the system 10 are addressed via timing bus 26 to permit the transfer of data via bus 22. As will be explained in detail later, each of thecomponents of the system 10 includes a tri-state driver and decoder unit, whereby during its specified clock time slot, its tri-state driver is enabled, whereby the particular component is connected to the I/O data bus 22 to permit the transfer of data. For example, during the tape-data-in period, the tri-state driver associated with the cassette interface circuit 28 is enabled, thereby to actively connect the circuit 28 with the data bus 22.
A selected tri-state driver is energized in accordance with an address as applied via the timing bus 26 to each of the components. In particular, the timing system 18 includes a character counter providing a series of six trains of pulses viathe timing bus 26 to decoders of each of the system's components. The decoders are, in effect, counters whose logic has been set to provide an enabling signal at its specified time slot, to enable its associated tri-state drivers. Thus, it can be seenthat the trains of pulses as shown in FIG. 3F are applied via the bus 26 to each of the components to selectively enable the decoder of a selected component to enable its tri-state driver during one of the time slots, as shown in FIG. 3H. Thoughsimilar, the actual transfer of data is shown in FIG. 3J, whereby after a component's tri-state driver is enabled, the data is transferred via the data bus 22. As a comparison of FIGS. 3J and 3H reveals, the timing or address signals first are appliedand in the subsequent time slot, the transfer of data occurs.
The timing system 18 also includes a vertical counter for providing, as shown in FIG. 4A, nine trains of pulses VC1 to VC9, which are applied via the timing bus 26 as address or timing signals to various of the components of the system 10, toenable that component's tri-state driver to connect it to the I/O data bus 22. As shown in FIG. 2 and FIG. 4C, after the 192-to-(M X N) scans of the CRT, the image ceases to be displayed, and after a period of approximately ten vertical counts, avertical blanking signal is applied to the CRT 34, as indicated in FIG. 4B. From the 192-count to the 0-count, as seen in FIG. 4C, data is transferred selectively between the components of the system 10. As seen in FIGS. 4C and 4D, between the 192ndand 200th count of the vertical counter of the timing system 18, data is transferred from the keyboard 30 and to the RAM 16; during the period from count 200 to count 208, data is transferred from the analog-to-digital converters associated with thestick control 30 and written into the RAM 16. During the next three periods, 208 to 216, 216 to 224 and 224 to 232, horizontal, vertical and color data corresponding to the special symbols to be generated by the symbol generator 20, are transferred fromthe RAM 16 to buffers or memories within the symbol generator 20 and the color processor 32. In the next timing period between vertical counts 232 and 240, signals indicative of the colors assigned to the characters C as shown in FIG. 2, are transferredto a memory within the color processor 32 and form a palette of colors from which the characters C may be selectively colored, depending upon the image to be displayed. In the period between counts 240 and 248, interface control data is transferredbetween the interface device and the RAM 16. In the next period between counts 248 and 256, audio data is transferred between the RAM 16 and the audio circuit 58, whereby an appropriate audio message may be reproduced by the speaker 59. In FIG. 4D,there is indicated the various addresses within the RAM 16 from which data is read or written selectively, as indicated by the read/write signal as shown in FIG. 4E.
In a sequence of operation of the system as shown in FIG. 1, a cassette-type storage unit 29 is inserted within a suitable drive mechanism and the data thereon are controllably read out by the interface circuit 28. Initially, the microprocessor12 executes a POWER ON program, stored within the ROM 14, whereby the system 10 is energized and thereafter executes a LOAD program whereby data of a particular program stored upon the storage unit 29 are loaded into selected portions of the RAM 16. This program data as derived from the unit 29 indicates images to be displayed upon the CRT 34 in terms of the configuration and color of the characters "C" making up an image, the audio message corresponding to the displayed image, PPS language programsand control signals for calling on selected programs as stored within the ROM 14. If the particular program involves calculations and arithmetic programs to perform the calculations may be brought out of the ROM 14 to be available to provide a series ofcalculations, typically in response to various entries made via the keyboard 30. The exceptionally wide range of uses of the computing system 10 will become apparent in the following description of various samples of the programs that may be recordedupon a tape cassette 29.
The content of the programs is virtually unlimited and has application in the home, business and in schools. For example, a tape storage unit or cassette 29 may be programmed with an educational program where the user, for example a child, getsa brief audio-visual lesson to teach the recognition of the letter "B" and its sound in various words. Audio via the speaker 59 demonstrates how to pronounce the "B" sound, and then instructs the viewer to use the control stick 30 whereby a cursor orpointer symbol as generated by one of the symbol generators 20 is displayed via the color processor 32 upon the CRT 34. With the control stick 30, the child selects a series of color pictures, those objects with the "B" sound. Upon receipt of thechild's response via the keyboard 30, a voice is programmed to congratulate him and applause is heard in the background, while the "B" character takes a bow. The voice as programmed and reproduced via the speaker 59 tells the viewer to move to the nextsequence of the interactive learning exercises. Further, audio-visual instruction can range in sophistication from such a simple application to complex adult education, e.g. bridge bidding. Logical predetermined responses can be assessed from the tapecassette 29 after each instruction by the microprocessor 12 or series instructions by the user, either to one novel situation after another, or to various, predetermined alternate responses.
Though the computing system 10 obviously has a wide range of complex programmed functions, the system 10 can be utilized to interact with the viewer in playing games. In one program termed "PAINTBOX", a paintbox of colors is displayed upon theCRT 34, whereby the viewer, via the keyboard 30, may select one or more of the displayed colors and draw pictures on the video screen with the selected colors. The pictures can be stored for later reference upon the tape storage unit 29, or the picturescan be erased at the push of one of the buttons of the keyboard 30. Prerecorded background music of synthetic sound to accompany or respond to motions of the electronic "brush" also is available. In such an application, the keyboard 30 is adapted byplacing a thin, transparent overlay over the keyboard 30 to identify its various switch points in accordance with the paintbox tape presentation. A series of buttons as indicated by the overlay, designates the color of the line to be drawn. Anotherbutton is programmed to move the line up or down upon the screen of the CRT 34, while a third button moves the line down or reverses its direction. Color mixing is done by visual reference to the displayed "paint buckets", disposed typically at thebottom of the CRT screen. The buckets or squares relate to specific keys or points on the overlay for the keyboard 30, which are activated by depressing whereby electronically mixing and blending the various shades of the colors is performed inaccordance with the viewer's command. Still another button as identified by the overlay is provided whereby the color of the entire picture may be changed. Such a system illustrates the ease in which a set of colors may be loaded into the RAM 16 andsubsequently into a color memory of the color processor 32; the stored set of colors may be changed readily by depressing the keyboard. As indicated above, a particular picture as "painted" may be transferred via the RAM 16 and the cassette interfacecircuit 28 onto the tape unit 29.
In another application, a tape cassette 29 may be programmed to play a version of "Concentration", wherein the object for the viewer is to visualize a random pattern of colored squares displayed upon the CRT 34, and to recall the pattern secondslater after the pattern has been removed. In one embodiment, 96 brightly-colored flags are arranged in rows across the screen of the CRT 34, some of which match and some of which do not. When the game begins, two players, each operating with his owncontrol stick 30, are given a discrete time period, e.g. 10 seconds, to spot and memorize the positions of as many of the matches of the colored flags as they can. Thereafter, the screen of the CRT 34 goes blank, except for several rows of sillouettes. Thereafter, first one player and then the other moves a cursor or special symbol as derived from the symbol generator 20 via his control stick 30. Once a player identifies a potential match, he presses a button upon the keyboard 30. If the playeridentifies correctly such a match, he is given an opportunity to identify another match. If unable, the other player is given an opportunity to identify matches, with each player obtaining a score indicative of the number of matches obtained and thescores of each player are displayed upon the CRT 34.
It is apparent that the computing system 10 can be readily adapted to play such commonly-known games as tennis, paddleball or hockey, as well as to be adapted to play more complex games, including contract bridge or chess. For example, a tapestorage unit 29 may be programmed to simulate the descent of an imaginary spacecraft under the control of the viewer as he manipulates a control stick 30. In the course of the game, the viewer must keep the spacecraft on-course as it descends to thesurface of the moon, while maintaining the correct rate of descent, the weight and quantity of fuel on board, and the directional thrust of four imaginary (but functional) retrorockets. The computing system is programmed to solve many problems involvingthe physics and mathematics of such a descent. For example, when the emission starts, the imaginary vehicle is at a predetermined altitude and the system begins to calculate the vehicle's rate of descent, based on its weight, ever-diminishing fuelsupply, rocket thrust and lunar gravity. The responses by the viewer/pilot are transformed into a series of complex equations for changing the previously-stored values, whereby a series of readouts corresponding to these parameters is displayed upon theCRT 34. The viewer/pilot starts his landing by depressing a key on the keyboard 30 and guides the imaginary landing vehicle by one of the control sticks 30 to keep a movable spot of light within a cross-hair in the center of the screen of the CRT 34. Straying off-course, for example, results in wasted fuel, delayed landing time, and either an ultimate crash (because the craft ran out of fuel) or an actual "abort" of the mission. The imaginary retrorockets are fired by pressing a further button onthe keyboard 30. In the course of the game, even if the ship is kept on-course, there is the risk of descending so rapidly that the vehicle is damaged on impact, which also would be indicated upon the screen of the CRT 34. The various equations fordetermining the motion and descent of the vehicle are programmed upon the tape storage unit 29, along with control data to execute the arithmetic program whereby the required calculations in response to the viewer/pilot input through the keyboard andstick control 30 are implemented. In this regard, the computing system 10 is able to carry out these calculations with extreme accuracy, even to fourteen decimal places, and also to provide audio responses and warning sounds during the course of thegame.
Further, a tape cassette may be programmed to perform library functions to maintain and update inventories, records or financial transactions, personal history files, mailing lists and merchandise catalogues, for example. Typically in such alibrary-type program, the tape storage unit 29 instructs an appropriate readout of data from the cassette via the cassette interface circuit 28, and RAM 16, to be displayed upon the screen of the CRT 34. The user views the format displayed upon the CRT34 and operates the keyboard 30 to enter the data or information he wants to store, at a point indicated by a square of light which he moves from left to right upon the CRT 34. As indicated above, an overlay may be disposed over the keyboard 30 wherebya variety of symbols, including numbers, letters, graphic symbols, formulae notation may be entered. In a storage retrieval mode, the computing system of FIG. 1 instructs a readout from the tape storage unit 29 of a large block of data, e.g. as many as300 pages or 9,600 typewritten lines, can be stored into the RAM 16 for each tape storage unit 29 that would be utilized. Typically, there would be 32 lines/page of stored information and when the list exceeds a page, the display upon the screen of theCRT 34 would begin to "scroll", the topmost lines disappearing off the top of the screen of the CRT 34. For recalling and updating the stored data, the viewer can set up tables of contents and address a selected line of the stored program by moving thecursor under the control of the stick 30 and depressing a special button. To erase and edit words or entire lines, a backspace key of the keyboard 30 is depressed and the new information is typed in. For coding into any of four individual colors, thecursor symbol, as generated by one of the symbol generators 20, is moved by the viewer with his control stick 30 to the desired line and another key is depressed. It is apparent that thousands of items may be listed and the resultant tape storage unit29 upon which they are stored may be readily transported to distant locations.
In a further application, a tape storage unit 29 may be programmed in a prompt-and-calculate mode to present a diet plan to the viewer. A first image or page of the programmed unit 29 appears upon the CRT 34, having blank portions in the displayfor receiving vital statistics such as height, weight, circumference of wrist, age and level of activity. The viewer fills in the blanks with the appropriate numbers via the keyboard 30, at which time the next image appears. The second image displays,based upon the previous inputs, the amount of daily caloric intake he should require to maintain his current body weight, and the user then enters his desired or "ideal" weight and selects a diet program from a number of indicated alternative exercisesand daily caloric reductions. Upon viewer command, the computing system then calculates the total amount of time required with the selected caloric reduction and exercise. If the viewer is not satisfied, i.e. it is taking too long to achieve thedesired weight reduction, the viewer may go back and erase and re-enter new figures into the program. After the second image or page has been completed, a third page is presented with a color-coded graph showing how much the viewer can expect to lose bythe specified time, as well as what his weight will be at any given week during the required period. In such a program, the basic equation or algorithm for computing the length of time required to reduce a given weight dependent upon the input of theviewer, is entered into the system 10 via the interface circuit 28 from the tape storage unit 29. The various mathematical calculations to perform the operations indicated by the equation draw upon the arithmetic subroutines stored in the ROM 14.
In the following, a more detailed description will be given of the components of the computing system shown in FIG. 10.
COLOR PROCESSOR 32
The color processor 32 as shown generally in FIG. 1 has an input from the timing system 18 via the timing bus 26 and is further coupled to the input/output data bus 22 whereby data is transferred between the color processor 32 and the RAM 16. Generally, the color processor 32 stores a particular set or palate of colors, from which a particular incremental area is colored. As will be explained, the colors as originally transferred from the tape unit 29 to the RAM 16, are addressed selectivelyin the RAM 16 by addresses developed by the timing system 18, and/or the color processor 32 to be described below.
As indicated above, the color processor is operative in the first or text mode, or in the second or paint mode. Referring now to FIG. 5A, there is shown a schematic block diagram of the color processor 32 in which the I/O data bus 22 deliverscolor command signals to be variously stored in a TEXT mode color address controller 81 or in an art hardware circuit 79. As will be explained in detail later, corresponding address signals are selectively read out and applied via the color pointer bus78 to the color memory 62, to derive a selected color signal. As seen in FIG. 5A, the color memory 62 is divided into a text memory 62B having eight addressable locations for storing eight colors, from which the image is formed in either the text orpaint mode, and a second or symbol memory 62a, into which eight colors may similarly be stored. As will be described, the address or color pointer signals are applied via the color pointer bus 78 and the A or B select address circuit 65 to the colormemory 62, to address one of the eight locations within either memory 62A or 62B to read out its corresponding color signal. In an illustrative embodiment of this invention, each of the eight memory locations has room to store eight bits, two bits foreach of the primary colors, red (R1, R0), green (G1, G0) and blue (B1 and B0), and two spares.
In the second or paint mode, a set of color pointers is transferred from the RAM 16 via the input/output data bus 22 to be stored within the art hardware circuit 79. As indicated above, the images are formed upon the screen of the CRT 34 in thepaint mode by deriving a set of color pointers corresponding to each square or dot pattern of the square array as shown in FIG. 5B. In particular, the art hardware 79 derives three color pointers corresponding to the right square, the middle square andthe left square, each color pointer being comprised of three bits. It is understood that a series of the square arrays as shown in FIG. 5B are assembled horizontally across the face of the screen of the color CRT 34 to form a text line of for example 96such squares and that a plurality of such text lines for example 64 is formed down the screen of the color CRT 34 to display a color image. First and second RAM addresses are developed by the timing system 18 to be applied via the RAM address bus 24 tothe RAM 16 to read out during the first and second look-ups, the first and second groups of color pointers to provide the three color pointers, one for each square of the square array as seen in FIG. 5B. In particular, during the first look-up, thefollowing set of color pointers is transferred to a memory or latch 66 of the art hardware circuit 79; the color pointers take the following form:
______________________________________ MSB PPS Word LSB ______________________________________ 8 7 6 5 4 3 2 1 1st look-up c2 c1 c0 b2 b1 b0 a2 a1 a0 .BHorizBrace. .BHorizBrace. .BHorizBrace. right dot pair middle dot pair left dot pair ______________________________________
The bit c2, designated with an asterisk, of the right dot or square pointer is not derived during the first look-up, but instead is derived during the second look-up of the pointers within the RAM 16, and is combined with the remaining eight bits(c1 to a0) as indicated above to form the complete three pointers for each of the squares of the square array as shown in FIG. 5B. In particular, the bits a0, a1, and a2 are derived during the first look-up to provide a pointer for the left dot pair orsquare, the bits b0, b1 and b2 are derived during the first look-up to provide the pointer for the middle dot pair or square, and only the bits c0 and c1 are derived during the first look-up to derive a portion of the pointer for the right dot pair orsquare as shown in FIG. 5B. As will be explained in some detail later with respect to FIGS. 27A and 27B, the RAM address for the first look-up in the paint mode, is comprised of the following fourteen bits:
______________________________________ Page Word ______________________________________ Ad- [P6 P5 P4 P3 P2 P1 P0 W6 W5 W4 W3] W2 W1 W0 dress of 1st look- up ______________________________________
of which those eleven bits disposed within the bracket form the page and word address for the RAM 16 to read out therefrom the above-given first look-up of data, while the three bits, W2, W1 and W0, are applied via the RAM address bus 24 to aninth bit select latch 73 to determine, as will be explained, which of the eight c2 bits as derived during the second look-up, are to be combined with the first eight bits obtained during the first look-up to obtain the complete three pointers. Inparticular, the ninth bit select latch 73 acts as a decoder to apply a control signal to one of eight select circuits 74 to apply the selected ninth bit to the ninth bit latch 69.
The art hardware circuit 79 and in particular the timing of the transfer of signals to and from the circuit 79, is under the control of an art controller 80, into which the timing signals in the form of the dot clock as applied via conduit 26C ofthe timing bus 26, a text mode disable signal and the output of the character counters as applied via conduit 26C from the timing system 18. The art controller 80 provides a first strobe that is applied to the first latch 66 and to the ninth bit latch69, to be described, thus enabling the latches 66 and 69 to receive color pointers during the first and second look-ups, respectively. The additional ninth bit c2 of the right dot pointer is required to identify the color for the third square, andduring the subsequent or second look-up, the following color pointer bits are obtained:
The color pointer bits c2 are then loaded into the ninth bit latch 69, and are transferred to a third color block driver 72 to complete the three sets of color pointers. In order to appropriately display a color associated with the square of asquare array, the art controller 80 strobes the first, second and third drivers 68, 70 and 72, as well as the one-of-eight select circuit 74, whereby the color pointers corresponding to the left, middle and right dot pairs are transferred via a colorpointer bus 78 and the select address circuit 65 to address the color memory 62. As indicated above, the color pointers C21 to C28 provide the ninth bit for eight first look-ups, the bit C21 being that ninth bit for the first of the first look-ups, andthe bit C28 being the ninth bit for the eighth, first look-up. As will be explained in detail later with respect to FIGS. 27A and 27B, the RAM address of the second look-up is formed by the timing system 18 as follows:
By comparing the RAM address of the second look-up and that of the first look-up, it is seen that the second look-up is formed by merely shifting the bits of the first look-up to the right and using the selected bits P3, P2, P1, P0, W6, W5, W4and W3 to address a second portion of the RAM 16.
In the first or text mode, the color processor 32 may operate either in a LOAD NEW COLOR POINTERS process whereby new color pointers are loaded into a color pointer latch 82 of the text mode color address controller 81, or in a PAINT DOT processto address the previously-loaded color pointers therein, whereby the selected color pointers are read out via enabled drivers 84, the color pointer bus 78 and the select address circuit 65 to address selected color signals within the text memory 62B.
The timing signals for enabling the selective actuation of the controller 81 and the hardware circuit 79 take the form of the dot clock, as shown specifically in FIG. 3A, the text mode signal, the output signals CC1 to CC6 of the charactercounter of the timing system 18, as shown in FIG. 3F, the output signals VC1 to VC9 of the vertical counters of the timing system 18 as shown in FIG. 4A, and other signals as will be described. The conduit for delivering these signals from the timingsystem 18 is shown generally in FIG. 1 as a timing bus 26 interconnecting the timing system 18 and the color processor 32; in FIG. 5A, these conduits will be more specifically identified. In either the PAINT DOT process or LOAD NEW COLOR POINTERSprocess, a display strobe is applied to the select address circuit 65 to enable the color pointer bus 78 to address the color memory 62.
The loading of color data and in particular the color signals into the color memory 62 from the RAM 16 is accomplished via the I/O data bus 22 into the memory 62 during the vertical scan I/O time slot as shown in FIG. 3H. In particular, theoutput of the vertical counter is applied via the timing bus 26A to the A or B select address circuit 65, as enabled by a load strobe applied thereto, to selectively address those locations within the memory 62 to receive the corresponding color signalsapplied thereto via bus 22. In this regard, the output of the vertical counter also is applied to the RAM 16 as an address signal to address those selected portions within RAM 16 to read out therefrom the color signals to be loaded into the memory 62.
In either the PAINT DOTS PROCESS or the LOAD NEW COLOR POINTERS process of the text mode, a RAM address signal developed by the timing system 18 is applied to the RAM 16. An indirect address is read out in response thereto from a first portionof the RAM 16, as shown in FIG. 1, during the CHAR time slot as shown in FIG. 4J, and is re-applied to the timing system 18. The bits of the RAM output forming the indirect address appears as follows:
The timing system 18, as will be explained in detail later, adds to the result of the first look-up a binary signal indicative of the text line of the characters being displayed (see FIG. 2), which provides a RAM address identifying a secondportion of the RAM 16, to be read out during the second look-up as identified by the time slot DOT as seen in FIG. 4J. If it is desired to paint dots, i.e. the PAINT DOTS PROCESS, the bits of a second address are read out as follows:
The above data of the second look-up are applied to latch controller 90, of the text mode color address controller 81, which initially reviews the R3 control bit to determine whether the color processor 32 is to be operated in the PAINT DOTprocess or LOAD NEW COLOR POINTERS process. In particular, the sixth and seventh control bits of the second look-up designated R2 and R3 and, the seventh bit of the first look-up, i.e. R1, are used as control bits, and all three of these control bitsare applied via the conduit 91 to the latch controller 90. The latch controller 90 acts as a logic circuit to interpret the instructions as provided by the control bits R1, R2 and R3. The controller 81 further includes a latch and parallel to serialconvertor 88 that acts as a foreground/background decoder whereby the color pointers of these portions of the displayed image, as shown generally in 5C, may be identified. In FIG. 5C, there is shown a character "A" which is colored with a foregroundcolor against a particular background color surrounded by an edge of a still different color.
Generally, if the controller 90 detects a zero R3 control bit, the latch controller 90 will then operate the text color address controller 81 in the PAINT DOTS process in the following fashion. The latch controller 90 actuates the converter 88to strobe in and store the above d6 to d1 given results of the second look-up. In turn, the latch controller 90 strobes out in serial fashion at the rate of the dot clock DCLK the previously-entered bits to be applied via an exclusive OR gate 86 to thelatch controller 90. The latch controller 90 receives the data of the second look-up derived from the latch 88 and acts as a decoder for energizing selectively one of the foreground or background drivers 84, thereby to apply the corresponding colorpointers that have been stored previously into the latch color pointer 82, via color pointer bus 78 and the select address circuit 65 to address and to read out from the addressed location of the text memory 62b, the selected color signals. Inparticular, the bits d1 to d6 as read out from the latch 88 through the exclusive OR gate serve as control signals to the latch controller 90, whereby upon receipt of a "1" bit, a latch enable signal is generated by the controller 90 and applied viaconduit 95B to enable the foreground driver, whereas in response to a "0" bit, an enable signal is generated by the controller 90 and applied via the latch 94A to enable the background driver. In this manner, the previously-stored color pointers of theforeground and background are read out through selectively actuated drivers and applied to the color pointer bus 78.
In the text mode, the color pointers for each of the background, edge and foreground portions of the image as shown in FIG. 5C are formed of but two designated bits, shown as follows:
______________________________________ Pointers Color Memory Edge Background Foreground Address ______________________________________ e1 e0 b1 b0 f1 f0 1 1 -- -- 1 1 7 1 0 -- -- 1 0 6 -- -- -- -- 0 1 5 -- -- -- -- 0 0 4 -- -- 1 1 -- -- 3 -- -- 1 0 -- -- 2 0 1 0 1 -- -- 1 0 0 0 0 -- -- 0 ______________________________________
As indicated above, the foreground pointer is partially formed of those two bits f0 and f1 as indicated, and the third bit f2 (not shown above) is selected as a "1". Thus, the color pointer for the foreground could illustratively be 111 toaddress that color signal within that location of the text color memory 62b. Similarly, the background color pointers b0 and b1 are combined with a preselected bit b2 of "0" to address those locations within the text color memory 62b, while the edgebits e1 and e0 are combined with a bit e2 which is either a "0" or a "1" in order to be the same as e1. In this manner, a limited amount of data permits each of the edge, background and foreground portions of the image as shown in FIG. 5C to be coloredwith any one of four colors.
As indicated in FIG. 5A, the latch controller 90 also reviews the R1 and R2 control bits and in its PAINT DOT process, where the R3 bit is 0, the controller 90 is armed upon reciept of the first look-up signals wherein there is a "1" R1 signal,and upon receipt of a subsequent signal wherein R2 is "1" and R1 is a "1", the latch controller 90 applies the DOT invert signal as a "1" to EXCLUSIVE OR 86, which inverts the data (d6 to d1) being shifted from latch 88. When either R1 or R2 is a "0",the DOT invert signal is a "0" and the data shifting from latch 88 is not inverted by the EXCLUSIVE OR 86. The output of EXCLUSIVE OR 86 selectively enables the foreground driver if a "1" or the background driver of a "0". R1 and R2 can thereby be usedto reverse the background and foreground portions of an image being displayed using the PAINT DOT process.
In the LOAD NEW COLOR POINTERS process, the control bits from the first and second look-ups are also applied to the latching controller 90, and if the control bit R3 is a "1", the latch controller 90 operates the text mode color addresscontroller 81 in the LOAD NEW COLOR POINTERS process as follows. In particular, the controller 90 causes the six least significant bits of the second look-up reproduced as follows, to be loaded into the color pointer latch 82:
______________________________________ six least significant bits ______________________________________ .THorizBrace. R2R3 e1 e0 b1 b0 f1 f0 edge background foreground ______________________________________
As seen above, the two least significant bits f1 and f0 of the second look-up identify a portion of the foreground color pointer, whereas the next two bits b1 and b0 define a portion of the background color pointer, and the 5th and 6th signficantbits e1 and e0 identify a portion of the color printers for the edge portion. The third bits f2, b2 and e2 of these pointers are preselected in the manner indicated bove. These aforementioned bits are first applied to and stored in the latch 82, to betransferred to the color pointer bus 78 by the drivers 84 in accordance with the strobe signals developed by the latch controller 90. In the LOAD NEW COLOR POINTERS process, the latch controller 90 responds to the following sets of conditions. If thecontrol bits R1, R2, R3, as derived during the first and second look-ups are "0", "0" and "1", respectively, the latch controller 90 stores the new bits (e1, e0, b1, b0, f1, f0) into the latch 82 and permits the shifting of zeros into latch dots 88,applies the zeros via the non-inverted, EXCLUSIVE OR gate 86, and paints then with the new background color pointers b1 and b2, as by strobing via conduit 95a the background drivers 84. As a result, the background color pointers stored in latch 82 areapplied by the actuated background driver of the drivers 84 to the memory 62.
If the control bits R1, R2 and R3 are, respectively, "1", "0" and "1", the latch controller 90 stores the new bits into the latch 82 and energizes the foreground driver of the drivers 84 to apply the foreground corresponding f1, f0 pointers tothe text memory 62B. In similar fashion, if the control bits R1, R2 and R3 are respectively "0", "1" and "1", the latch controller 90 first stores the new bits into the latch 82 and energizes the edge driver of the drivers 84 as via conduit 95C, toapply the new edge color pointers e1, e0 via the color pointer bus 78 to the text memory 62B. In a still further operation, if the latch control bits R1, R2 and R3 are respectively "1", "1" and "1", the controller 90, after loading the new bits, then isenabled to modify the existing set of color pointers, the controller 90 acts to toggle the least significant bit of the foreground and background pointers within the register 82 and further applies the actual six-bit code of dots, i.e. d6-d1, via thedrivers 84, the bus 78 and the select address circuit 65 to the text memory 62B.
As indicated above with respect to the description of FIG. 1, there is provided symbol generators 20 that permit the display of special characters such as a cursor for particularly identifying a designated point of the CRT display. In order toselectively apply colors to the symbol portion of the CRT display, a set of tri-state generator drivers 76 permit the timed transfer of color pointers corresponding to that symbol via the color pointer bus 78 and an enabled selected address circuit 65 tothe symbol memory 62A of the color memory 62, whereby the desired color is addressed and is read out via the latch 64 to be applied to the interface circuit 33. The symbol memory portion 62A stores in selected portions thereof the library or palette ofcolors to be applied to color the displayed symbol.
An alternate mechanization of the preferred embodiment of the text mode described above incorporates a larger text color memory, for example sixteen words of 8-bit length, which is addressed by a color pointer developed from the first and secondlook-up control bits R1, R2 R3 in addition to the first look-up data bits d1-d6. In this mechanization, there is only one process, the PAINT DOT process, whereby the data d1-d6 are always gated into latch 88. The INVERT DOT signal is always falseprecluding the inverting of data by EXCLUSIVE OR gate 86. A color printer is formed from the bits R1, R2, R3, di, where di refers to the six data bits d1-d6 as they are successively shifted from the latch 88. This 4-bit color pointer is applied to anexpanded 4-bit color pointer bus 78 connected to a similarly-expanded select address circuit 65 which in turn is used to address the expanded text color memory 62B.
With reference now to FIGS. 6A to 6D, there is shown a detailed schematic circuit of the color process as shown diagrammatically in FIG. 5A. With respect to FIGS. 6A, B and C, data is transferred via bus 22 to load the color memory 62 comprisedof two tri-state memory devices, to the symbol generator drivers 76 (see FIG. 6D) comprised of tri-state drivers and the art controller 80 (see FIG. 6B) also comprised of tri-state drivers. Data is also transferred to the color memory 62 comprised ofseparate memory units and connected to the A or B select address circuit 65 (see FIG. 6C), and to the latch 66 (see FIG. 6D). Further, the specific circuitry of the latch controller 90 is illustrated in FIG. 6E. The latch controller 90 is shown asbeing coupled to receive data via the bus 22 for controlling the drivers 84, as explained above. In addition, the drivers 72, 70 and 68 (see FIG. 6E) are connected to the pointer bus 78 for conveying data to the color memory 62. Further, theone-of-eight select circuit 74 is likewise coupled to the bus 78. As shown in detail in FIG. 6C, the latch 66 is connected to receive data from the I/O data bus 22 and is coupled to the drivers 72, 70 and 68.
VIDEO INTERFACE CIRCUIT 33
In FIG. 7A, there is shown a schematic block diagram of the video interface circuit 33 generally shown in FIG. 1 as interconnecting the output of the color processor 32 to a color CRT 34, and in FIG. 7B, there is shown a detailed circuit diagramthereof. With reference to FIG. 7A, the output of the latch 64 of the color processor 32 as shown in FIG. 5A, comprises two signals R0 and R1 indicative of red, two signals G1 and G0 indicative of green, and two signals B0 and B1 indicative of blue. These color signals are applied via buffer amplifiers 96A to 96E, and enabled gates 97A to 97F to digital-to-analog (D/A) converters 98A, 98B and 98C, with the red signals being applied to the D/A converter 98A, the green signals being applied to the D/Aconverter 98B, and the blue signals being applied to the D/A converter 98C. The gates 97 are disabled by a blanking signal as derived from a level shifter 102. As generally shown in FIG. 7A, vertical and horizontal blanking information is derived fromthe timing system 18, whereby the corresponding red, green and blue signals are disconnected from the color CRT 34. The D/A converters 98 convert the inputted, digital color signals to analog signals which are applied via a corresponding cathode driveror amplifier 100 to a cathode of the electron gun of the color CRT 34, i.e. the output of the red cathode driver 100A is applied to the cathode of the red electron gun. The level shifter 102 also provides appropriate horizontal and vertical blankingsignals to the drivers 100A, 100B and 100C thereby to disable the output during the horizontal and vertical blanking of the color CRT 34. As also shown, the audio bus is connected via an audio power amplifier 106 to the speaker 59. FIG. 7B shows thedetailed circuitry of the elements generally shown in FIG. 7. In particular, the detailed circuitry of the cathode drivers 100 is set out, and similarly the details of the level shifter circuit 102 responsive to the horizontal and vertical timinginformation are shown.
SYMBOL GENERATOR
In FIGS. 8 and 9A, B and C, there is shown, respectively, a schematic diagram and a detailed circuit diagram of the symbol generators 20, generally shown in FIG. 1. Referring to FIG. 8, data in the form of the dot patterns to be used for each ofeight different symbols, is conveyed from the RAM 16 by the I/O data bus 22 to a gate 124. As will be explained, the enabled gate 124 applies via conduit 125 the dot patterns corresponding to eight symbols, into corresponding memories in the form ofserial registers 120. In particular, the gate 124 either gates the dot pattern from the I/O data bus 22 or applies an all-zero word if a dot pattern does not appear on this particular horizontal line. The dot patterns are applied to serial registers120A and 120H, and loaded into selected registers 120, under control of a one-of-eight decoder 122, to which the outputs of the character counters of the timing system 18 are applied, those outputs being illustrated in FIG. 3F. Enable signals, derivedas will be explained in detail later, are applied via cond | | | |
