Resources Contact Us Home Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE     Digital data communication system RE31319 Digital data communication system Patent Drawings: Inventor: Fraser Date Issued: July 19, 1983 Application: 06/123,970 Filed: February 25, 1980 Inventors: Fraser; Alexander G. (Bernardsville, NJ) Assignee: Bell Telephone Laboratories, Incorporated (Murray Hill, NJ) Primary Examiner: Olms; Douglas W. Assistant Examiner: Attorney Or Agent: Lipton; Roy C. U.S. Class: 370/433; 370/465 Field Of Search: 370/89; 370/86; 370/88; 370/94; 370/60; 370/85; 370/118; 370/84; 370/80; 179/18EA; 364/200 International Class: U.S Patent Documents: 3466397; 3632882; 3639904 Foreign Patent Documents: Other References: AFIPS Conference Proceedings, vol. 38, 1971 Spring Joint Computer Conference, May 18-20, 1971, pp. 211-216, "TYMNET . . . CommunicationNetwork" by L. Tymes.. AFIPS Conference Proceedings, vol. 36, 1970 Spring Joint Computer Conference, May 5-7, 1970, pp. 551-567, " . . . Interface Message Processor . . . ARPA Computer Network".. Abstract: A digital data transmission system comprising a plurality of interconnected switching units, each such unit having connected thereto at least one transmission loop, and each such loop having at least one digital device attached thereto. The system provides controllable buffering of digital data thereby allowing digital devices having different data transfer speeds and storage capabilities to communicate asynchronously. The system allocates communication resources upon request but only creates actual communication paths when the requesting device is transmitting data. Thus system resources need not remain committed between bursts of data. Claim: What is claimed is: 1. A data transmission system for .Iadd.supporting data cells among .Iaddend.a plurality of digital devices, .Iadd.a data call being comprised of randomly occurring bursts ofdata with intervening pauses, .Iaddend.comprising means for virtually allocating transmission paths upon request .Iadd.preparatory to establishing data calls .Iaddend.from any of said digital devices to any other of said digital .[.device.]. .Iadd.devices by assigning to each call a description of transmission resources to convey the data .Iaddend.and means for activating said virtually allocated transmission for .[.paths.]. .Iadd.path in accordance with the assigned description.Iaddend.only .[.when.]. .Iadd.upon determination that a .Iaddend.data .Iadd.burst of the call .Iaddend.is actually transmitted. 2. A digital data transmission system .Iadd.for supporting data calls among a plurality of digital devices, a data call being comprised of randomly occurring bursts of data with intervening pauses .Iaddend.including a plurality of transmissionloops, each including at least one digital device, comprising: means for virtually allocating a transmission path from a digital device in one loop to a digital device in another loop comprising a plurality of asynchronous links .Iadd.by assigning to each call a description of the links in the path,.Iaddend.and means for activating particular ones of said links .Iadd.in accordance with the path description .Iaddend.only when .Iadd.a .Iaddend.data .Iadd.burst of the call .Iaddend.is actually available at said particular ones for transmission. 3. A data transmission system comprising: means for receiving requests to virtually allocate communication paths; means for storing descriptions of requested communication paths; and means for using the stored descriptions to create the requested communication paths only when data is actually available for transmission. 4. A data transmission system comprising: means for receiving requests to establish communication paths; means for storing descriptions of requested communication paths comprising a plurality of asynchronous links; and means for activating particular ones of the plurality of links only when data is actually available at the particular ones for transmission. 5. A system for providing data communication between a plurality of digital devices comprising: means for receiving requests for the use of communication paths from each one of said plurality of digital devices; means for virtually allocating communication paths in response to said requests and prior to actual use of said paths; and means for actually connecting said virtually allocated communication paths at the time data is actually transmitted. 6. A digital data transmission system comprising: a first switching unit; a first digital device attached to said first switching unit; a second switching unit connected to said first switching unit; a second digital device attached to said second switching unit; means for virtually allocating a first transmission path between said first digital device and said first switching unit; means for virtually allocating a second transmission path between said first switching unit and said second switching unit; means for virtually allocating a third transmission path between said second switching unit and said second digital device; and means for selectively activating each of said first, second, and third virtually allocated transmission paths. 7. The digital data transmission system of claim 6 wherein each of the three means for virtually allocating a transmission path further comprises: means for storing parameters characterizing the data which is to be transmitted; and means for initiating the virtual allocation of the next succeeding transmission path. 8. The digital data transmission system of claim 6 wherein said means for selectively activating each of said first, second, and third virtually allocated transmission paths further comprises: means for activating said first virtually allocated transmission path only when said first digital device is actually transmitting data; means for activating said second virtually allocated transmission path only when said first switching unit is actually retransmitting data received from said first digital device; means for activating said third virtually allocated transmission path only when said second switching unit is actually retransmitting that data received from said retransmission by said first switching unit. 9. The digital data transmission system of claim 8 wherein each of the three means for activating a transmission path further comprises: means for receiving incoming data which is to be retransmitted on said transmission path; means for storing said incoming data; and means for retransmitting said data on said transmission path. 10. The digital data transmission system of claim 9 wherein said means for storing said incoming data further comprises: means for selectively limiting the total amount of incoming data which is stored at any time. 11. The digital data transmission system of claim 10 wherein said selectively limiting means further comprises: means for causing the device that is transmitting said incoming data to cease transmission when the amount of said incoming data that has not been retransmitted on said transmission path reaches a prespecified value. 12. A system for transmitting data between digital devices comprising: a plurality of interconnected program-controlled switching units; at least one program-controlled terminal interface unit attached to each one of said plurality of interconnected program-controlled switching units for communication therewith by a digital device. 13. The system of claim 12 further comprising: means for selectively limiting the amount of buffering that said system provides in each switching unit for each digital device that is attached thereto. 14. The system of claim 13 further comprising: means for selectively limiting the minimum amount of data that said system permits each digital device attached thereto to transmit in a single burst of transmission. 15. The system of claim 14 further comprising: means for selectively limiting the minimum amount of data that said system transmits to each digital device attached thereto in a single burst of transmission. 16. The system of claim 14 further comprising: means for selectively limiting the rate at which said system permits each digital device attached thereto to transmit data. 17. The system of claim 15 further comprising: means for selectively limiting the rate at which said system transmits data to each digital device attached thereto. 18. The method of transmitting data comprising the steps of: receiving requests for the use of transmission resources from transmitting devices; storing descriptions of the transmission resources necessary to honor the received requests; committing transmission resources to particular transmitting devices in accordance with the stored descriptions only at the time data is actually transmitted. .Iadd. 19. The method of transmitting data in data calls comprised of randomlyoccurring bursts of data with intervening pauses, comprising the steps of: receiving requests for the use of transmission resources from transmitting devices; storing a description of the transmission resources necessary to honor each received request; and committing transmission resources to particular transmitting devices in accordance with the stored descriptions only at a time when it is determined that a data burst is actually transmitted. .Iaddend. Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to digital transmission systems and, more particularly, to digital transmission by asynchronous message switching on a common time-divided transmission loop. 2. Description of the Prior Art It is often desirable to exchange digital information between digital machines. If such machines are separated by any significant geographic distance, it has heretofore been necessary to either purchase or lease a dedicated transmission facilitybetween such machines, or to arrange a temporary connection between such machines by means of common carrier, switched transmission facilities. Since it is the nature of digital machines to require large amounts of digital channel capacity, but only forbrief periods and only occasionally, the heretofore available facilities described above have proven very inefficient for this use. Dedicated transmission facilities, for example, remain unused the vast majority of the time. Switched, common carrierfacilities tend to be restricted in bandwidth to voice frequencies and hence are not immediately adaptable to high speed digital transmission. A further problem with switched facilities is the fact that it often takes more time to set up the transmission path than is required for the entire transmission of data. The telephone network requires real time transmission in the sense thatsignals must be delivered substantially at the same time they are generated. It therefore is standard procedure to set up the communication path in its entirety before any signals are transmitted. As a result, centralized switching has been used in thetelephone plant. Digital transmission of data, on the other hand, need not be done in real time and hence it is wasteful to set up an entire connection prior to transmission. These facts tend to make presently available interconnection facilitiesuneconomical for intermachine digital communications. It is therefore an object of the present invention to provide improved digital transmission between digital machines. It is another object of the present invention to allow digital machines having widely varying data handling capabilities to communicate efficiently and ecomonically. It is a further object of this invention to provide a system which allows a digital machine to communicate with a plurality of other digital machines without the need for reprogramming that machine when the number or capabilities of machines inthe system is changed. It is a still further object of this invention to provide an algorithm which takes advantage of the inherent characteristics of digital machines to provide a more efficient method of using transmission resources. SUMMARY OF THE INVENTION These objects are achieved in accordance with this invention by a system of interconnected transmission loops. The system includes a plurality of interconnected switching units which comprise general-purpose programmable digital computers. Eachswitching unit has at least one transmission loop connected to it. Each loop includes at least one loop access module and each module has attached to it a terminal interface unit to which a digital device is connected. Each switching unit controls the data transmission to and from the digital devices that are attached to its transmission loops. Each digital device may be allocated up to 256 different channels, one of which is used solely for signalling betweenthe digital device and its associated switching unit. The switching unit controls the allocation and actual implementation of the remaining 255 of these channels by a process that may be termed "virtual allocation." When a request to make a connection is received, the switching unit determines and stores the characteristics of the transmission path required to honor the request. No actual transmission paths are set up at this time and no actual systemresources are assigned except for the amount of the switching unit memory used to store the transmission path characteristics. The transmission path is actually set up only when the digital device begins to transmit data. The data flow is thencontrolled in accordance with the previously determined characteristics by a novel algorithm embodying a request-acknowledge process. A transmission path is actually maintained only as long as data is being transmitted. The transmission path otherwiseremains only virtually allocated. Since it is characteristic of digital devices to transmit data in bursts with pauses between bursts, this method of controlling the system eliminates idle transmission paths. This more efficient use of transmissionresources allows a greater volume of data to be handled. The loop access modules serve to keep data flowing around the transmission loops and to provide an interface between the loops and the terminal interface units. The terminal interface units transfer data on a full duplex basis between theirassociated digital device and the rest of the system. Each terminal interface unit includes a small programmable digital computer which interacts with the computer in the switching unit to control the signaling between the switching unit and theassociated digital device and which serves to control the transfer of data to and from the digital device. The algorithm that governs the transmission of data in the system comprises two program portions, one stored in and executed by the switching unit, the other stored in and executed by the computer contained in the terminal interface unit. Thisalgorithm utilizes the characteristics of the requested data transfer to determine the system resources that will be required. During the actual data transmission, the algorithm provides for the buffering that is required to allow the requesting digitaldevice to transmit data to the receiving digital device. Thus the algorithm serves to match the data transmission characteristics of the transmitting digital device to the data reception characteristics of the receiving digital device. BRIEFDESCRIPTION OF THE DRAWING FIG. 1A is a general block diagram of a digital transmission system in accordance with this invention; FIG. 1B illustrates the manner in which data and signalling information is transmitted in the system of FIG. 1A; 2A is a more detailed diagram of the switching unit shown in FIG. 1A; FIG. 2B is a more detailed diagram of a part of the transmission system shown in FIG. 1A; FIG. 3A illustrates the format of the signals appearing on the transmission lines and transmission loops shown in FIG. 1A; FIG. 3B is an expanded view of a portion of FIG. 3A; FIG. 4A shows the manner in which the line format shown in FIG. 3A is utilized in this invention; FIG. 4B is an expanded view of a portion of FIG. 4A; FIG. 4C is a further expanded view of a portion of FIG. 4A; FIGS. 5A and 5B are a logic diagram of the loop transmit buffer shown in FIG. 2B; FIG. 5C is a logic diagram of the rising edge trigger circuit used in the loop transmit buffer shown in FIG. 5A; FIGS. 5D and 5E are a logic diagram of the loop receive buffer shown in FIG. 2B; FIG. 5F is a logic diagram of the falling edge trigger circuit used in the loop receive buffer shown in FIG. 5D; FIGS. 6A through 6H are a logic diagram of the data multiplexer shown in FIG. 2B; FIG. 6I shows the interconnection of FIGS. 6A through 6H; FIG. 7A is a block diagram of the terminal buffer shown in FIG. 2B; FIG. 7B is a timing diagram useful in understanding the operation of the terminal buffer shown in FIG. 7A; FIG. 7C is a more detailed diagram of the data receive buffer shown in FIG. 7A; FIG. 7D is a more detailed diagram of the data transmit buffer shown in FIG. 7A; FIG. 7E is a more detailed diagram of the channel select circuit shown in FIG. 7A; FIG. 7F is a more detailed diagram of the channel break circuit shown in FIG. 7A; FIG. 8 is a representation of an instruction word used by the interface computer shown in FIG. 2B; FIG. 9A is a block diagram of the interface computer shown in FIG. 2B; FIG. 9B is a timing diagram useful in understanding the operation of the interface computer shown in FIG. 9A; FIGS. 9C, 9D, and 9E are a logic diagram of the interface computer shown in FIG. 9A; FIG. 9F shows the interconnection of FIGS. 9C, 9D, and 9E; FIG. 9G is a logic diagram of a clock circuit used in the interface computer shown in FIG. 9A; FIG. 10A is a functional diagram that illustrates the data and signal transfer between the digital device, terminal interface unit, and switching unit shown in FIG. 1A; FIG. 10B is a functional diagram that illustrates the data and signal transfer between the switching units shown in FIG. 1A; FIGS. 11A, 11B, and 11C show the formats of the data and signals that are transmitted in the system of FIG. 1A; FIG. 12 is a flow chart of the initialization instructions executed by the interface computer shown in FIG. 2B; FIGS. 13A and 13B are a flow chart of the data output routine executed by the interface computer shown in FIG. 2B; 14A and 14B are a flow chart of the data input routine executed by the interface computer shown in FIG. 2B; FIG. 15 is a flow chart of the signal output routine executed by the interface computer shown in FIG. 2B; FIGS. 16A and 16B are a flow chart of the signal input routine executed by the interface computer shown in FIG. 2B; FIGS. 17A through 17L show the data structures used by the control computer shown in FIG. 2B; FIGS. 18A, 18B, 18C and 18D are a flow chart of the call management routine executed by the control computer shown in FIG. 2B; FIG. 19A is a flow chart of the decode route routine executed by the control computer shown in FIG. 2B; FIG. 19B is a flow chart of the trace route routine executed by the control computer shown in FIG. 2B; FIG. 19C is a flow chart of the remove subchannel routine executed by the control computer shown in FIG. 2B; FIGS. 19D and 19E are a flow chart of the create subchannel routine executed by the control computer shown in FIG. 2B; FIG. 19F is a flow chart of the find queue routine executed by the control computer shown in FIG. 2B; FIGS. 20A-20D are a flow chart of the data input routine executed by the control computer shown in FIG. 2B; FIGS. 21A and 21B are a flow chart of the data output routine executed by the control computer shown in FIG. 2B; FIGS. 22A through 22F are a flow chart of the signal input routine executed by the control computer shown in FIG. 2B; FIGS. 23A and 23B are a flow chart of the signal output routine executed by the control computer shown in FIG. 2B; FIGS. 24A and 24B are a flow chart of the timeout routine executed by the control computer shown in FIG. 2B; FIG. 25A is a flow chart of the S.BURST.IN subroutine executed by the control computer shown in FIG. 2B; FIG. 25B is a flow chart of the E.BURST.IN subroutine executed by the control computer shown in FIG. 2B; FIG. 25C is a flow chart of the S.BUNDLE.IN subroutine executed by the control computer shown in FIG. 2B; FIGS. 25D and 25E are a flow chart of the S.BURST.OUT subroutine executed by the control computer shown in FIG. 2B; FIG. 25F is a flow chart of the E.BURST.OUT subroutine executed by the control computer shown in FIG. 2B; FIG. 25G is a flow chart of the S.BUNDLE.OUT subroutine executed by the control computer shown in FIG. 2B; FIG. 25H is a flow chart of the REQSIG subroutine executed by the control computer shown in FIG. 2B; FIG. 25I is a flow chart of the REQOUT subroutine executed by the control computer shown in FIG. 2B; FIG. 25J is a flow chart of the ASSIGN.SPACE subroutine executed by the control computer shown in FIG. 2B; FIG. 25K is a flow chart of the RELEASE.SPACE subroutine executed by the control computer shown in FIG. 2B; FIG. 25L is a flow chart of the ASSIGN.TRUNK subroutine executed by the control computer shown in FIG. 2B; FIG. 25M is a flow chart of the RELEASE.TRUNK subroutine executed by the control computer shown in FIG. 2B; and FIG. 25N is a flow chart of the RETREAT subroutine executed by the control computer shown in FIG. 2B. DETAILED DESCRIPTION Before proceeding to a detailed description of the drawings, it should be noted that all of the circuits described herein may be realized, in the illustrative embodiment, by using integrated circuits. Suitable circuits can be found, for example,in "The Integrated Circuit Catalog," first edition, Catalog CC401, published by Texas Instruments, Inc. and, alternatively, in "The Microelectronics Data Book," second edition, by Motorola Semiconductor Products, Inc., dated December, 1969. Referring more particularly to FIG. 1A, there is shown a graphical representation of a data transmission system in accordance with the present invention. The system comprises a plurality of switching units 10 which are interconnected by means oftransmission lines 12. Each switching unit 10 has attached thereto at least one transmission loop 14. Each such transmission loop 14 is connected to at least one loop access module 16. Loop access module 16 serves to steer data around loop 14 and totake data from the loop and place data on the loop in the manner to be described in greater detail hereinbelow. Each loop access module 16 is connected to a terminal interface unit 17 which provides an interface between an attached digital device 18 andthe remainder of the system. Data transmission in the system is primarily controlled by the interaction of terminal interface unit 17 and switching unit 10. This interaction is shown schematically in FIG. 1B. FIG. 1B illustrates a full-duplex transmission path in which one terminal interface unit 19 of the type shown in FIG. 1A transmits data to another terminal interface unit 23 which receives it. The receiving terminal interface unit 23 responds by sending either data or signals or both back to the transmitting terminal interface unit 19. Since the transmission path is full-duplex, these actions can occur simultaneously. While it is possible for two terminal interface units 17 (FIG. 1A) on the same transmission loop 14 to communicate, a typical communication will, as shown in FIG. 1B, involve more than one switching unit. The detailed system algorithm by whichthis communication takes place is described hereinbelow following the detailed descriptions of the apparatus shown in FIG. 1A. However, a consideration of the following brief description of the process of communication in the system of FIG. 1A will makethe apparatus description more readily understandable. The digital transmission system of FIG. 1A provides each digital device 18 that uses the system with the capability of selecting up to 256 other devices in the system to which it can transmit data or from which it can receive data. Each suchselection comprises a "channel" which is used herein to mean a previously selected route. Thus it is as if each digital device had attached to it 256 full-duplex channels each of which it could use on a one-at-a-time basis to send or receive data. Although each device has only 256 channels, the destinations of these channels can be changed by the device as desired. One of these channels is reserved for communication with the switching unit that controls the transmission loop to which theparticular device is attached. This channel, termed the "control channel," is used by the terminal interface unit associated with the digital device to set up a data transmission path by providing the most immediately associated switching unit with thefull address of the intended destination of the data appearing on each of the remaining 255 channels. The control channel is also used by the switching unit to command the digital device to pick the channel on which it wishes to receive data being sentby another digital device. The switching unit maintains a list showing the correspondence between the absolute addresses and the 256 channels of each of the digital devices connected to it. Thus for each transmission or reception, a digital device needonly handle an eight bit address. FIG. 1B illustrates a single full-duplex channel between a transmitting terminal unit 19 and a receiving terminal unit 23. Terminal interface units 19 and 23 and the switching units 20, 21, and 22 are shown ascomprising components labeled with subscripted .alpha.'s and .beta.'s. The label ".alpha." is associated with the transmission of data while the label ".beta." is associated with the reception of data. The connection between a particular .alpha. andthe .beta. to which it transmits is termed a "link." The subscript "T" is associated with that half of the full-duplex path, which is termed a "subchannel" and shown in FIG. 1B as path 15, that transmits data from the transmitting terminal interfaceunit 19 to the receiving terminal interface unit 23. The subscript "R" is associated with the other subchannel of the full-duplex path. The .alpha. and .beta. "components" referred to above and shown in FIG. 1B refer not to apparatus but to stored processes and parameters which serve to control the transmission and reception of data between the terminal interface units and theswitching units. The .alpha. processes use the .alpha. parameters to control transmission of data while the .beta. processes use the .beta. parameters to control reception of data. The exact manner in which these processes provide the desired datacommunication will be discussed in greater detail below. In general, a terminal interface unit will only have a single set of .alpha. parameters and a single set of .beta. parameters, both sets of which are uniquely determined by the characteristicsof the particular associated digital device. Hence the .alpha. and .beta. parameters of a terminal interface unit remain the same for each of the 256 channels on which it can communicate. This is not true, however, for the switching units. Each switching unit will, at any instant, be communicating on only a particular one of the 256 full-duplex channels of a specified terminal interface unit. Each half of this channel has anassociated .alpha.-.beta. pair which need not correspond to the .alpha.-.beta. pair on the other half of the channel. In the example shown in FIG. 1B, .alpha..sub.T1 represents the transmitting characteristics of transmitting terminal interface unit19, while .beta..sub.Rn represents the receiving characteristics of that unit. Switching unit 20 receives data on link 24 from terminal interface unit 19 in accordance with the parameters .beta..sub.T1 and retransmits the data to switching unit 21 onlink 25 in accordance with parameters .alpha..sub.T2. Similarly, switching unit 20 receives data sent by receiving terminal interface unit 23 from switching unit 21 on link 28 in accordance with parameters .beta..sub.R(n-1) and retransmit it totransmitting terminal interface unit 19 on link 29 in accordance with parameters .alpha..sub.Rn. Each switching unit has two .alpha.-.beta. pairs for each full-duplex channel which is routed through it. Thus switching unit 22 may have, for example, not only the two .alpha.-.beta. pairs shown in FIG. 1B, but also other such pairs allocatedfor other channels from other terminal interface units associated with both switching unit 20 and switching unit 21. The allocation of such pairs in various switching units is termed "virtual allocation" since all that need be done is to store thecorrect .alpha.-.beta. pairs. Thus many channels may be virtually allocated at any one time. A particular channel may be actually activated by directing the pertinent switching units to begin receiving and retransmitting data on a half duplex basis inaccordance with that particular channel's .alpha.-.beta. appropriate pair. Continuing then with the description of the apparatus of FIG. 1A, FIG. 2A is seen to be a more detailed description of a single switching unit 10. Each switching unit 10 comprises a single control computer 30 which communicates with a pluralityof line terminating units 31. One line terminating unit 31 is required for each transmission loop 14 and each transmission line 12 that is connected to switching unit 10. These units serve to output data from control computer 30 onto transmission loops14 and transmission lines 12. Transmission lines 12 as well as transmission loops 14 are of the type suitable for synchronous, digital, fixed-frame transmission. In the following discussion of the exemplary embodiment of this invention, it will beassumed that transmission lines 12 and transmission loops 14 comprise standard T1 carrier lines of the type well known in the prior art. FIG. 2B is a more detailed diagram of the apparatus required to control a single transmission loop to which is connected a single loop access module 16. Since each line terminating unit 31 operates in the same manner irrespective of whether itis connected to a transmission line 12 or a transmission loop 14, a detailed description of the apparatus shown in FIG. 2B will suffice to explain the operation of the system shown in FIG. 1A. Turning then to control computer 30 shown in FIG. 2B, it is this device that performs the aforementioned processes of virtual allocation and actual activation of channels that is required to enable terminal interface unit 17 to communicate withother terminal interface units in the system. Control computer 30 may be any of the many commercially available general-purpose digital-computers. The computer chosen for any particular implementation will be determined by the size of the system thatis desired. In the following discussion, computer 30 is assumed to be a TEMPO 1 computer which is manufactured by TEMPO Computers, Incorporated, a division of General Telephone and Electronics, Incorporated. Control computer 30 is connected to loop transmit buffer 34 of line terminating unit 31 by means of lines 32. Since the TEMPO 1 computer has a sixteen-bit output, lines 32 shown in FIG. 2B comprise 16 separate wires which interconnect the outputregister of the TEMPO 1 computer and the loop transmit buffer 34. Loop transmit buffer 34 temporarily stores the sixteen-bit words output by the control computer 30. After buffering this data, the loop transmit buffer 34 outputs it to the bytedisassembler 40. Each such output comprises a ten-bit word, eight bits of data from the control computer 30 and two bits of control information which are supplied by the circuitry of the loop transmit buffer 34 in the manner which is described inconjunction with FIGS. 5A and 5B. These twelve-bit words are transferred from loop transmit buffer 34 to byte disassembler 40 of line terminating unit 31 by means of lines 38 which comprise twelve wires, one for each bit. Byte disassembler 40 serves to transform the output ofloop transmit buffer 34 into serial data for transfer to terminal matching unit 42 over line 44. Terminal matching unit 42 of line terminating unit 31 supplies the interface that connects the input and output of control computer 30 to the transmission loop 14 or, alternatively, to a transmission line 12 for those line terminating units 31that are connected to transmission lines 12. This terminal matching unit comprises standard T1 equipment which can be commercially obtained from the Vicom division of the Vidar Corporation as the Vicom 2020 Terminal Matching Unit. Terminal matchingunit 42 is connected to office repeater 50 by means of lines 46 and 48. Lines 46 comprise a pair of wires which allow data to be transmitted from control computer 30 to transmission loop 14 and lines 48 comprise a pair of wires which allow data to betransmitted from transmission loop 14 to control computer 30. Office repeater 50 serves to provide power for the T1 line comprising transmission loop 14. This unit is also commercially available under the name of Vicom 2010 Office Repeater. As can be seen in FIG. 2B, data flows out of office repeater 50 onto transmission loop 14 and is transferred to line repeater 52 which is contained in loop access module 16. Line repeater 52 serves to retransmit data received on transmissionloop 14 from office repeater 50 and also serves as the means by which loop access module 16 takes data from line 14 and places data onto loop 14. Line repeater 52 is also a piece of commercial T1 equipment which is obtainable under the name of the Vicom1550-04 Self-Equalizing Line Repeater. Line repeater 52 is line powered and serves to automatically adjust for variations in the length of cable between adjacent repeaters subject to a range limitation. In those implementations in which loop accessmodules are very close together and hence out of the compensation range of the repeaters, 15 decibel artificial cable networks may be inserted between repeaters in a manner which will be apparent to those of ordinary skill in the art. In order to insure proper operation of the system if power should fail at a particular loop access module, each loop access module 16 is provided with a protection relay 54. Protection relay 54 has transfer contacts which when unenergizedconnect lines 78 and 80, and when energized connect lines 79 and 80. Thus if a signal is not supplied to protection relay 54 on line 77 by power monitors 76, the protection relay will short-circuit loop access module 16 and simply allow data to beretransmitted on transmission loop 14 by line repeater 52. Power monitor 76 is a triggerable one-shot multivibrator and will hence supply an output signal as long as it is supplied with power from terminal interface unit 17 and is also continuously triggered by AND gate 73. AND gate 73 has two inputs,one from interface computer 62 which is periodically supplied if interface computer 62 is functioning properly, and one from data multiplexer 58 through inverter 74. The signal supplied by data multiplexer 58 indicates that a framing error was detectedin the data input on lines 71. Inverter 74 thus inhibits AND gate 73 when an error signal is supplied by data multiplexer 58 on line 75. Matching unit 56 of loop access module 16 shown in FIG. 2B serves the same function as terminal matching unit 42. Indeed, matching unit 56 may also comprise a Vicom 2020 Terminal Matching Unit. Data multiplexer 58 of terminal interface unit 17 shown in FIG. 2B serves to receive data from matching unit 56 of loop access module 16 on lines 71, and to transfer data to matching unit 56 on lines 72. Data multiplexer 58, shown in greaterdetail in FIGS. 6A-6I, serves to assemble the serial data coming from matching unit 56 into eight-bit words for transmission to terminal buffer 60, and also serves to disassemble eight-bit words from terminal buffer 60 into serial data to be transferredback to matching unit 56. Terminal buffer, 60, which is explained in greater detail in conjunction with FIGS. 7A-7F, serves to buffer data going to and coming from digital device 18. This buffer serves to isolate digital device 18 from the synchronous speed oftransmission loop 14. The control of terminal interface unit 17 is provided by the interface computer 62. Interface computer 62, which is explained in greater detail in conjunction with FIGS. 9A-9F, is a digital computer which has a limited instruction repertoire. This instruction repertoire is, however, sufficiently flexible to allow programming the interface computer 62 to do the variety of tasks which are of critical importance in the implementation of the aforementioned transmission algorithm. In thisillustrative embodiment a specially designed digital computer is disclosed; however, the functions performed by interface computer 62 could alternatively be implemented by using a commercial digital computer as will become apparent to those of ordinaryskill in the art by the further discussion of interface computer 62. Serial data emerging from line repeater 52 of loop access module 16 returns to control computer 30 by way of the office repeater 50 and terminal matching unit 42. The data is transferred serially from terminal matching unit 42 by line 6200 tobyte assembler 64. Byte assembler 64 performs the converse of the operation performed by byte disassembler 40; that is, it assembles the serial data from terminal matching unit 42 into eight-bit bytes for transmission to loop receive buffer 66 on lines68. Loop receive buffer 66 operates in a manner analogous to loop transmit buffer 34 and is explained more fully in conjunction with FIGS. 5D and 5E. Before proceeding to the more detailed diagrams of the apparatus shown in FIG. 2B, it will be advantageous to consider first the data format of the system as shown in FIGS. 3A and 3B. The format shown in FIG. 3A is seen to be the standard T1 line format. The bit sequence appearing on the T1 line is divided into standard frames each comprising a framing bit followed by 192 time slots. The framing bit alternates between a "1"and a "0" on successive frames. The concatenation of two successive standard frames will be termed herein a "master frame" and is understood to always begin with a frame whose framing bit is a 1. The 192 time slots of a standard frame are seen in the expanded view in FIG. 3B to be further subdivided into 24 subgroups of eight slots each. These slots in each subgroup are labeled "1" through "8," respectively. As shown, a 1 line bitoccupies fifty percent of the time slot allotted to it, thereby resulting in a fifty percent duty cycle pulse train. As is well known in the prior art, it is necessary when using a T1 line to insure that there are enough 1 bits on the line to keep thesystem clocks operational. To accomplish this, a 1 bit, which is commonly termed a "keep-alive bit," is inserted into the sixth slot of every eight-slot subgroup. When the serial data on the transmission line is used in the system, such as by byte assembler 64 and data multiplexer 58 shown in FIG. 2B, the framing and keep-alive bits are ignored in the formation of the byte. Excluding these two types ofbits, it can thus be seen that 42 eight-bit bytes are formed in a master frame. The line format provided by the standard T1 line is utilized by the apparatus of the illustrative embodiment of this invention in the manner shown in FIGS. 4A, 4B, and 4C. Both the network signaling and the transmission of system data aremultiplexed onto the same line in the same manner. Of the 42 bytes that exist in a master frame, the first four bytes shown in FIG. 4B are reserved exclusively for network control signaling, and the remaining 38 bytes are reserved for user supplieddata. The first four bytes will be termed hereinafter a "signal packet" and the remaining 38 bytes will be termed a "data packet." As can be seen in FIG. 4B, signal packets and data packets are completely independent even though they occur as a pairwithin a master frame. The first byte of each packet is understood to be reserved for an identification code or a special code indicating that the packet is currently empty. The packet formats are discussed in greater detail hereinbelow in conjunctionwith FIGS. 11A through 11C. LOOP TRANSMIT BUFFER Continuing then with the detailed description of the circuitry shown in FIG. 2B, FIGS. 5A and 5B are seen to comprise a detailed diagram of the loop transmit buffer 34 shown in FIG. 2B. As shown in FIG. 5A, the input to the loop transmit buffer34 comprises a sixteen lines 150 from control computer 30. The output of the loop transmit buffer comprises eight lines 151 which are applied to byte disassembler 40. Loop transmit buffer 34 buffers data coming from control computer 30 and outputs it to byte disassembler 40 in the proper sequence at the proper time. This function is accomplished through the control of memory 152 shown in FIG. 5B. Memory 152is a thirty-two word by sixteen-bit store which can be formed, for example, of eight integrated circuit memories such as bipolar LSI memory 3101 manufactured by Intel Corporation. Under the control of the logic circuitry shown in FIGS. 5A and 5B,sixteen-bit words are read into memory 152 from control computer 30 while, on alternate byte strobe signals issued on line BS from byte disassembler 40, eight-bit words are read out of memory 152 on either of the eight lines 154 or the eight lines 155into eight-bit register 156 from whence they are clocked out to byte disassembler 40. The manner in which the control logic accomplishes this is as follows. Clock 186 shown in FIG. 5A provides the basic timing for loop transmit buffer 34. This clock comprises an astable multivibrator which runs at a 5 megahertz rate. The output of clock 186 is applied to flip-flop 158 which is a triggeredflip-flop; that is, it changes state each time it receives a pulse from clock 186. Flip-flop 158 serves to divide the pulse train from clock 186 into two pulse trains operating at one-half the frequency of clock 186. The Q output of flip-flop 158 isapplied to AND gate 159 while the Q output of flip-flop 158 is applied to AND gate 160. Additionally, each of these two gates have as their second input the output of clock 186. Thus the outputs from AND gates 159 and 160 are seen to be two 2.5megahertz pulse trains that are 180.degree. out of phase. The pulse train from AND gate 159 is used to read sixteen-bit words from control computer 30 into memory 152, while the output from AND gate 160 is used to read eight-bit bytes from memory 152to byte disassembler 40. First consider the reading of sixteen-bit words from control computer 30 into memory 152. This process is accomplished on a command-acknowledge basis. Commands from control computer 30 are transferred on line 163 to rising edge trigger 164. This trigger, which is shown in greater detail in FIG. 5C, provides a strobe output to NAND gate 161 upon receipt of a command from control computer 30 unless an inhibit signal has been received from six-bit comparator 166 in accordance with thediscussion hereinbelow. The rising edge trigger circuit 164 also serves, unless it is inhibited, to supply an acknowledge signal to control computer 30 on line 165 each time it receives a command. RISING EDGE TRIGGER CIRCUIT OF THE LOOP TRANSMIT BUFFER Rising edge trigger circuit 164 is shown in greater detail in FIG. 5C. In the circuit's quiescent state both of D-type flip-flops 189 and 193 have a 1 on their Q outputs causing the strobe output to be a 0 and the acknowledge output to be a 1. A strobe pulse is generated in response to a command being applied to the D input of flip-flop 189. When a command is applied, flip-flop 189 changes to its set state the next time a clock pulse is applied to the clock input of flip-flop 189. Since atthe time flip-flop 189 becomes set flip-flop 193 is still reset, AND gate 194 goes to a 1 output, thus beginning the strobe pulse output. The trailing edge of the clock pulse that sets flip-flop 189 is coupled through inverter 192 to the clock input of flip-flop 193. This allows the 0 on the Q output of flip-flop 189 to be coupled through NAND gate 191 to the D input of flip-flop193, causing it to change state. The acknowledge line thus falls, causing the output of AND gate 194 to fall, thereby terminating the strobe pulse output. The circuit remains in this state until the command line falls, at which time it returns to itsquiescent state until the command line is again raised. The generation of the strobe pulse output will be inhibited if a 1 is applied to the inhibit input. Inverter 190 converts this into a 0 which prevents NAND gate 191 from responding to the Q output of flip-flop 189. This, in turn, prevents theacknowledge output from going to a 1. Returning then to FIG. 5A, NAND gate 161 is thus seen to be enabled whenever the strobe signal from rising edge trigger 164 corresponds with the output from gate 159. When both these inputs are simultaneously present at gate 161, it generates anoutput signal to memories 167 and 152 and to six-bit counter 168. This output signal causes memories 167 and 152 to store the words currently appearing on their inputs. Memory 167 is a thirty-two-word-by-two-bit memory which serves to store two bits of information which are applied to memory 167 by control computer 30 on lines 169 and 170. These two bits comprise status information which is output to bytedisassembler 40 at the appropriate time. The bit appearing on line 169 signifies the type of packet currently being transmitted, either a data packet or a signal packet, and the bit on line 170 serves to indicate when byte zero of either a signal packetor a data packet is being transmitted. Six-bit counter 168 serves to keep track of the address in each of memories 167 and 152 which is currently being written into by control computer 30. The same addresses in each of memories 167 and 152 are always simultaneously addressed. Theoutput from gate 161 increments six-bit counter 168 each time a command is received from control computer 30 to store another word into memories 167 and 152. This serves to provide the correct address for the storage that follows the next command fromcontrol computer 30. Turning then to the apparatus which transfers eight-bit bytes of the words stored in memories 152 and 167 to byte disassembler 40, this apparatus is seen to be under the control of ten-bit shift register 171. Shift register 171 receives both ofits inuts from byte disassembler 40. One of these inputs, the D.sub.36 input, comprises a signal that falls to a 0 ech time byte disassembler 40 requests the thirty-sixth byte of a thirty-eight byte data packet. This input serves to put a 0 into shiftregister 171. This particular signal is used to provide a reference point from which the type of packet which is currently being transmitted can always be determined. The other input to shift register 171 is the byte strobe signal, BS, which issupplied by byte disassembler 40 each time it requests a new byte to be transferred from the memory 152. The 0 bit that is inserted in the left side of shift register 171 is right-shifted each time the byte strobe signal occurs. After shift register 171 has been right-shifted twice, once for the D.sub.36 and D.sub.37 byte strobes, the next byte strobe will be the beginning of a signal packet. Since the third through the sixth output taps of shift register 171 areconnected to NAND gate 171B, the output of this gate, which is applied to two-bit comparator 173, is a 1 when a signal packet is being processed by byte disassembler 40. A 0 on the third output tap of shift register 171 indicates that the first byte of a signal packet is being processed while a 0 on the seventh output tap of shift register 171 indicates that the first byte of a data packet is being processed. Thus the output of NAND gate 171A is a 1 when the first byte of a packet is being processed. The outputs of NAND gates 171A and 171B are applied to the two-bit comparator circuit 173. Comparator circuit 173 also receives input from register 174 whichserves as a holding register for memory 167 in the same manner that register 156 serves as a holding register for memory 152. Comparator circuit 173 thus serves to compare the packet type and byte number which is currently being processed by bytedisassembler 40 with the packet type and byte number which are currently resident in register 156. When these inputs are the same, comparator 173 supplies an output signal through gate 175 to six-bit counter 176. Gate 175 is a four-input AND gate having 2 of its inputs inverted by inverters 175A and 175B. Thus the output signal fromcomparator 173 passes through gate 175 to counter 176 at the proper time as determined by the inputs to gate 175 which are supplied by flip-flop 172, NAND gate 146, and comparator 166. The output of gate 175 causes counter 176 to be incremented. Counter 176 serves as an address counter which keeps track of the current address in memories 167 and 152 from which the byte disassembler 40 is reading in a manner analogous to that in which counter 168 keeps track of the address into which controlcomputer 30 is writing. Memory 152 comprises thirty-two memory words each containing sixteen bits. However, since it is desired to read each of these words out to byte disassembler 40 in eight-bit bytes, it is necessary to alternate reading out one-half of the memoryon the eight lines 155 and reading the other half of the memory on the eight lines 154. This alternate reading is accomplished by means of flip-flop 172 and OR gates 177 and 178. Flip-flop 172 receives its clocking input from the BS signal line of byte disassembler 40. Thus flip-flop 172 serves to divide the byte strobe pulses into two pulse trains, one pulse train appearing on the Q output of flip-flop 172 and the otheron the Q output of flip-flop 172. These two pulse trains are applied respectively, to OR gates 177 and 178; the Q output of flip-flop 172 being applied to OR gate 178, and the Q output of flip-flop 172 being applied to OR gate 177. The outputs of thesetwo gates go to the "Select" inputs on the aforementioned memory circuits. The memory circuits which comprise memory 152 are characterized in that the contents of the currently selected addressed location are available as the output whenever the select signal is given. Since the select signals are given in analternating fashion by the outputs from OR gates 177 and 178, register 156 is loaded first from one-half of memory 152 and then from the other half, and then, in the following time period, from the first half again. Thus it is seen that register 156 isloaded by alternate bytes of each word that is output from memory 152. The outputs of six-bit counters 176 and 168 are applied to memories 167 and 152 by means of select circuit 179. For simplicity, only one detailed portion of select circuit 179 has been shown in FIG. 5B. in actuality, circuit 179 comprises fivesets of circuits 179A through 179E. Each of these comprises, as shown in detail in circuit 179A, AND gates 180, 181, OR gate 182 and inverter 183 that are shown in FIG. 5B. That is, the circuit 179A comprises the circuitry needed to gate one bit of thefive least significant bits from each of counters 176 and 168 to the five-bit address inputs of the two memories. AND gate 181 has as its inputs a bit from counter 176 and the Q output of flip-flop 158. Thus whenever flip-flop 158 is reset, whichoccurs during the time which is allocated for byte disassembler 40 to read bytes out of memory 152, AND gate 181 has as its output one bit from counter 176. This is applied by means of OR gate 182 to memories 167 and 152. Thus whenever flip-flop 158 isreset, the address suplied to memories 167 and 152 is that determined by counter 176 which is the counter which keeps track of the correct location from which byte disassembler 40 should be reading. In a similar fashion, AND gate 180 has as its input abit from counter 168 and the Q output of flip-flop 158 as inverted by inverter 183. Thus on alternate cycles of clock 186, AND gate 180 will supply a bit from counter 168 through OR gate 182 to the address inputs of memories 152 and 167. Thus it isseen that select circuit 179 serves to apply addresses to memories 167 and 152 in an alternating fashion, first the address into which control computer 30 is currently writing and then the address from which byte disassembler 40 is currently reading. Six-bit comparator 166 serves to compare the outputs from counters 176 and 168. When these outputs are equal, indicating that the location into which control computer 30 will next write is the same location from which byte disassembler 40 willnext read, this indicates that the memories 167 and 152 are empty and hence a signal is output on line 166A to AND gate 175 through inverter 175B. When comparator 166 determines that the address from which byte disassembler 40 will next read is equal tothe sum of the address into which control computer 30 has just written plus thirty-two, which indicates that memories 167 and 152 are full, then an output signal will be generated on line 149 and applied to rising edge trigger circuit 164. This signalwill serve to inhibit the generation of an acknowledge command on line 165 in the manner described hereinbefore. This is done because since the memories 167 and 152 are now full, control computer 30 must be prevented from writing any more informationinto them until room has been provided by means of byte disassembler 40 reading out a word of the stored information. Flip-flops 147 and 148 serve to synchronize the loop transmission buffer of FIGS. 5A and 5B. The T1 transmission line is a synchronous line while the control computer 30 is an asynchronous device. It is thus necessary to insure that the outputsfrom control computer 30 are supplied to the transmission line in the proper time sequence. The input to flip-flop 147 is the byte strobe signal on line BS from byte disassembler 40. The output of flip-flop 147 is copied into flip-flop 148 whenever ANDgate 159 generates an output. When flip-flop 148 receives its input from flip-flop 147, this is output to NAND gate 146. The next time that gate 160 generates an output, NAND gate 146 generates an output to registers 174 and 156, which causes theseregisters to read from memories 167 and 152, respectively. The outputs of these registers are then available to byte disassembler 40. Register 174 provides its output by means of inverter 185 and AND gates 184 and 186. Register 156 provides eight bitsof output on eight lines 151. LOOP RECEIVE BUFFER Continuing with the detailed description of the circuitry shown in FIG. 2B, FIGS. 5D and 5E are seen to be a detailed diagram of the loop receive buffer 66 shown in FIG. 2A. As shown in FIG. 5E, input to the loop receive buffer 66 compriseseight lines 195 from byte assembler 64. The output of the loop receive buffer comprises sixteen lines 209 which are applied to control computer 30. Loop receive buffer 66 performs the converse of the function performed by loop transmit buffer 34. That is, loop receive buffer 66 stores eight-bit bytes from byte assembler 64, forms them into sixteen-bit words, and transfers them to controlcomputer 30. This function is accomplished through the proper control of memories 196 and 203 in the following manner. Memory 196 is a sixteen-word-by-sixteen-bit memory which can be formed for example, from eight integrated circuit memories such as bipolar LSI memory 3101 manufactured by Intel, Inc. Under the control of the logic circuitry shown in FIGS. 5D and5E, eight-bit bytes are written into memory 196 from byte assembler 64 while, on alternate byte strobe signals from byte assembler 64, sixteen bit words are read out of memory 196 into sixteen bit register 197 from whence they are clocked out to controlcomputer 30. The manner in which the control logic accomplishes this is as follows. Clock 198 provides the basic timing for the loop receive buffer. This clock comprises an astable multivibrator which runs at a 5 megahertz rate. The output of clock 198 is applied to flip-flop 199 which is a triggered flip-flop, that is, itchanges state each time it receives a pulse from clock 198. Flip-flop 199 serves to divide the pulse train from clock 198 into two pulse trains operating at one-half the frequency of clock 198. The Q output of flip-flop 199 is applied to AND gate 200while the Q output of flip-flop 199 is applied to AND gate 201. Additionally, each of these two gates have as their second input the output from clock 198. Thus the outputs from AND gates 200 and 201 are seen to be two 2.5 megahertz pulse trains thatare 180 degrees out of phase. The pulse train that is output by AND gate 201 is used to write eight-bit words from byte assembler 64 into memory 196, while the output from AND gate 200 is used to read sixteen-bit words from memory 196 to register 197,from which it is available to control computer 30. The output of AND gate 201 is applied to NAND gate 202. The other input to gate 202 is the Q output of flip-flop 225. Flip-flop 225 in conjunction with flip-flop 204 serves to synchronize the operation of loop receive buffer 64 with the timingof the T1 transmission line in the same manner as flip-flops 147 and 148 shown in FIG. 5A serve to synchronize the loop transmit buffer 34 with the T1 transmission line. Thus the timing pulse from gate 201 is applied by gate 202 to the write input ofmemories 196 and 203 immediately after the byte strobe signal is applied from byte disassembler 64 on line BS. The address into which the current byte from byte assembler 64 will be written is determined by five-bit counter 205. The particular byte of that address into which the current output from byte assembler 64 will be written is determined by gates206 and 207 under the control of flip-flop 208. This determination is exactly analogous to that made by gates 177 and 178 under the control of flip-flop 172 which is shown in FIG. 5A. That is, the incoming bytes are placed in alternate bytes of theword. Counter 205 is incremented by the output from NAND gate 202 provided that it is not inhibited by the output of NAND gate 219. The inputs to gate 219 are derived from ten-bit shift register 211. One input to shift register 211 is the byte strobe signal which is supplied on line BS by byte assembler 64 each time it sends an eight-bit byte out on lines 195. The other input to shift register 211 is the D.sub.36 pulse, which when appliedthrough inverter 212 puts a 0 into shift register 211. The D.sub.36 pulse is emitted by byte assembler 64 each time it sends the thiry-seventh byte of a thirty-eight byte data packet. This particular signal is used to provide a reference point fromwhich the type of packet currently being transmitted can be easily determined. The 0 bit that is inserted in the left side of shift register 211 is right-shifted each time the byte strobe signal occurs. The output taps of the register are used asfollows. After shift register 211 has been right-shifted twice, once each for the D.sub.36 and D.sub.37 byte strobes, the next byte strobe will be the beginning of a signal packet. Thus the third output tap in FIG. 5D, is connected by means of inverter200 to the K input of JK flip-flop 208. The outputs of flip-flop 208 are applied to OR gates 206 and 207 which drive the "Select" inputs of memory 196 and thus serve to write eight-bit bytes into alternate halves of a memory word in the same manner thatOR gates 177 and 178 shown in FIG. 5B serve to read alternate halves of words out of memory 152. The fourth output tap of the shift register 211 signifies the second byte in a signal packet. This is applied through inverter 213 to OR gate 215. If a signal is simultaneously present on the READ input line, indicating that the current packetis not an empty one, then AND gate 218 will transfer a 1 to memory 203. The eighth output tap of register 211, which signifies the second byte in a data packet, is also applied to OR gate 215 by means of inverter 214. Thus it can be seen that AND gate218 will transfer a 1 bit to memory 203 whenever the second byte of either a signal or data packet that is not empty is being stored in memory 196. NAND gate 216 has as its inputs the third through tenth output taps of shift register 211. NAND gate 216 thus only has an output when any one of the signals on these output taps are 0's. This corresponds to the four bytes of a signal packet andthe first four bytes of a data packet. This information is all control information used by the system in the manner discussed hereinbelow and hence the output of NAND gate 216 is transferred on line 223 to memory 203. Memory 203 is addressed by select circuit 227 which is driven by five-bit counters 205 and 226. Counter 205 controls the address into which byte assembler 64 writes while counter 226 controls the address from which control computer 30 reads. Counter 205 is inhibited by NAND gate 219 when there is no signal on the READ input and when, simultaneously, the packet currently being processed is not the second byte of a signal packet and thus the write addressing of memory 196 is inhibited. Selectcircuit 227 is exactly the same as select circuit 179 shown in greater detail in FIG. 5B and operates in exactly the same manner to supply the correct read and write addresses to memories 203 and 196. Next consider the reading of sixteen-bit words from memory 196 into control computer 30. This process is accomplished on a command-acknowledge basis. Commands from control computer 30 are transferred on line 237 to falling edge trigger 210. This trigger, which is shown in greater detail in FIG. 5F, provides a strobe output to NAND gate 229 upon receipt of a command from control computer 30 unless an inhibit signal has been received from five-bit comparator 228 in accordance with thediscussion hereinbelow. The falling edge trigger circuit 210 also serves to supply an acknowledge signal to control computer 30 on line 238 each time it receives a command unless it is inhibited. FALLING EDGE TRIGGER CIRCUIT OF THE LOOP RECEIVE BUFFER Falling edge trigger circuit 210 is shown in greater detail in FIG. 5F. In the circuit's quiescent state D-type flip-flop 231 is in the set state and flip-flop 235 is in the reset state causing the strobe output to be a 0 and the acknowledgeoutput to be a 1. A strobe pulse is generated in response to a command being applied. Flip-flop 231 changes to its reset state the next time a clock pulse is applied to the clock input of flip-flop 231. Since, at the time flip-flop 231 becomes resetflip-flop 235 is still reset, the output of AND gate 236 goes to a 1, thus beginning the strobe pulse output. The trailing edge of the clock pulse that sets flip-flop 231 is coupled through inverter 232 to the clock input of flip-flop 235. This causes the 0 on the Q output of flip-flop 231 to be coupled through NAND gate 234 to the D input of flip-flop235, causing the output of AND gate 236 to fall, thereby terminating the strobe pulse output. The circuit remains in this state until the command line rises, at which time it returns to its quiescent state until the command line is again dropped. The generation of the strobe pulse output will be inhibited if a 1 is applied to the inhibit input. Inverter 233 converts this into a 0 which prevents NAND gate 234 from responding to the Q output from flip-flop 231 when a 1 is applied to thecommand input. This, in turn, prevents the acknowledge output from going to a 1. Reterning then to FIG. 5D and 5E, NAND gate 229 is seen to be enabled whenever the strobe signal from falling edge trigger circuit 210 corresponds with the output from gate 200. When enabled, gate 229 increments counter 226 and provides aclocking signal to checksum circuit 239. Checksum circuit 239 provides a parity-like check on the sixteen-bit words sent to control computer 30 on lines 209. Checksum circuit 239 serves to EXCLUSIVE OR sixteen data words with the checksum word immediately following it. This checksumword is generated when the data is sent in the manner to be described hereinbelow. In the absence of error, the output of the circuit is zero after each seventeenth word in a data packet. The manner in which the EXCLUSIVE OR between successive bits inthe same bit position in successive words is formed can best be appreciated by the following example. Consider for example, the ith bit position of four successive words, N1, N2, N3, and N4. The EXCLUSIVE OR of the bit in the ith bit position in wordsN1 and N2 is formed. The result of this is EXCLUSIVE ORed with the ith bit position of word N3, the result of which is, in turn, EXCLUSIVE ORed with the ith bit position of word N4. This process is continuously repeated. For simplicity, only oneportion of checksum circuit 239 is shown in FIG. 5E. Checksum circuit 239 actually comprises sixteen sets of circuits, 239A through 239P. Each of these, as shown in detail in circuit 239A, comprises EXCLUSIVE OR gate gate 242 and D-type flip-flop 241. Flip-flop 241 stores the result of each output from gate 242 and supplies it as an input to gate 242 for the next word output from register 197, thus achieving the desired result. The outputs from each of gates 242 form the sixteen lines 243 which areall inputs to OR gate 244. If any of these inputs are 1, indicating the presence of a checksum error, then OR gate 244 generates an error signal to control computer 30 on line 245. Checksum circuit 239 is reset to zero by NAND gate 244A when the fourthbyte of each data packet is given to control computer 30. DATA MULTIPLEXER Byte disassembler 40 and byte assembler 64, shown in FIG. 2B, perform functions analogous to that performed by data multiplexer 58, also shown in FIG. 2B. In fact, a subset of the apparatus of data multiplexer 58 can be used to implement bytedisassembler 40 and byte assembler 64. Therefore, before discussing these latter two units, the logic diagram of data multiplexer 58 which is shown in detail in FIGS. 6A through 6H will be discussed. FIG. 6I shows the manner in which FIGS. 6A through6H are connected. As shown, data multiplexer 58 serves as an interface between matching unit 56 of loop access module 16, and terminal buffer 60 and interface computer 62 of the terminal interface unit 17. The purpose of the multiplexer 58 is to collect therelevant data and signal packets from the transmission loop and to insert new ones onto the loop when circumstances permit. The general manner in which data multiplexer 58 achieves this purpose is as follows. All of the timing for the operation of data multiplexer 58 is determined by system clock 250, although functional control is exercised by the interface computer 62. Transmission line bits, excluding the "keep-alive" bit, are serially clockedinto shift register 251. When a full byte has been clocked into shift register 251 it may be decoded, left untouched, or removed from the shift register on a parallel basis. Transmission is accomplished on a packet-by-packet basis. Once transmission of a packet commences, it continues until the entire packet has been transmitted. Transmission from terminal buffer 60 or from interface computer 62 can occur when anempty packet is detected, or where the contents of a packet are removed by the terminal buffer, provided the packet type being processed by the data mltiplexer matches the packet type that interface computer 62 wants to have transmitted. This matchingrequirement must be observed because signal packets and data packets are not interchangeable, as was discussed in connection with FIG. 4B. In addition, the request from interface computer 62 to transmit information must be detected by the datamultiplexer before an appropriate time in order for transmission to be considered during the next packet time interval. In addition to the basic function mentioned above, the data multiplexer checks for incoming bipolar violations in the T1 line format and provides a means for pulse injection into the outgoing bit stream. This pulse injection inserts the"keep-alive" bit into the outgoing bit stream and is also used to insert a special error format into the outgoing bit stream at the appropriate time. This error format provides a means to signal subsequent stations on a loop that a bipolar violation hasoccurred in a particular packet. The manner in which these functions are performed by data multiplexer 58 will now be described in greater detail with specific reference to FIGs. 6A-6H. The order of the description below follows the order in which the various portions of theapparatus actually function during the typical operation of multiplexer 58. In order to facilitate this discussion and to provide better continuity between figures, various ones of the input and output lines shown in FIGS. 6A-6H are labeled inaccordance with the signals which they transmit or receive. Referring then specifically to FIG. 6C, matching unit 56 is seen to provide a two wire input 353 to circuit 352. Circuit 352, which provides an interface between matching unit 58 and data multiplexer 58, is standard T1 equipment obtainable underthe name of Vicom 5120 Data Receive Unit. Circuit 352 provides a clocking singla (RCV CLOCK) to system clock 250. Circuit 352 also provides a repetitive set of eight pulses on lines D1 through D8 which correspond to the eight slots in the subgroup in astandard T1 frame. It is to be noted that these pulses correspond to the line slots and not to either the bits in a byte or to the bytes in a data packet. These bytes can be distinguished in that they are referred to by subscripted D's, D.sub.0 throughD.sub.37. The RCV CLOCK signal is also applied to receive flip-flop 253 which serves to read the line bits serially into shift register 251. CLOCKS, COUNTING AND STEERING CIRCUITS OF DATA MULTIPLEXER 58 Data multiplexer 58 has one system clock 250 and three subclocks driven from the system clock. System clock 250 comprises a one-shot multivibrator which serves to regenerate the RCV CLOCK signal from the matching unit 56, and thus its outputcomprises a near-perfect fifty-percent duty cycle waveform. The subclocks comprise serial strobe generator 254, parallel strobe generator 300, and status read pulse generator 358. Serial strobe generator 254, which also comprises a one-shot multivibrator, generates a pulse on the falling edge of each pulse from system clock 250 which is used to strobe data serially into shift register 251. The pulse train from serialstrobe generator 254 cannot, however, be used directly. As previously mentioned, the standard T1 line format includes a "keep-alive" bit in the line bit stream. In order that this "keep-alive" bit not be permitted into shift register 251, the serialstrobe corresponding to the time at which this "keep-alive" bit appears at the input to shift register 251 must be inhibited. This is accomplished by the strobe steering circuit 255. The strobe steering circuit 255 has applied thereto the inverted D6 output (D6) from circuit 352. This inversion is obtained by means of inverter 261. When the D6 signal falls it serves to preset flip-flop 256. When flip-flop 256 is preset,AND gate 257 is enabled and AND gate 258 is disabled. Therefore the strobe signal from serial strobe generator 254 cannot pass through gate 258. During the time that gate 257 is enabled the serial strobe instead passes through gate 257 to the sixthslot error detector 262 enabling it to operate in the manner to be described hereinbelow. When signal D7 is generated by circuit 352, it is passed through inverter 355 and applied to flip-flop 256 thereby clearing it. This enables gate 258 and disablesgate 257. Therefore the serial strobe generated by serial strobe generator 254 is again allowed to pass through gate 258 to shift register 251. Gate 258 is disabled only during the time period when the serial strobe corresponding to the "keep-alive"bit appears. Therefore the "keep-alive" bit is the only bit that is not permitted to enter shift register 251. The output of AND gate 258 is also applied to the input of NAND gate 260. The output of NAND gate 260 is applied to three-bit counter 263which in turn provides its output to six-bit counter 264. The outputs of counters 263 and 264 provide timing signals for data multiplexer 58. One timing signal generated by AND gate 361 is output on line D.sub.36 to terminal buffer 60 and to interfacecomputer 62. That line is set to a 1 when counter 264 contains the value 41. NAND gate 260 inhibits the steered serial strobe from AND gate 258 whenever the strobe corresponding to the framing bit occurs. This action is analogous to that in which ther serial strobe corresponding to the "keep-alive" bit is inhibited. NAND gate 260, in conjunction with flip-flop 259, removes the pulse strobe corresponding to the framing bit in order that the framing bit will not be counted as a bit of usable information. Whenever the signal DF is output from circuit 352 to inverter265, the output of the inverter, DF, goes to zero, thereby presetting flip-flop 259. During the time that the Q output of flip-flop 259 is 0, the output of NAND gate 260 is 1. When the pulse D1 occurs flip-flop 259 is cleard. Therefore, flip-flop 259only inhibits NAND gate 260 for the time period in which the strobe corresponding to the framing bit occurs. It is thus seen that the output of NAND gate 260 comprises a series of strobe pulses excluding those corresponding to the "keep-alive" bit andthe framing bit. This pulse train is then counted using the beginning of a master frame as a reference point. This counting is initialized in the following manner. As previously mentioned, the beginning of a master frame occurs when the framing bit is a 1 bit. Data multiplexer 58 is initialized at the beginning of each master frame by the output of master frame reset pulse generator 266, which comprises anAND gate. The inputs to the master frame reset pulse generator 266 comprise the DF pulse and the U pulse which is output from inverter 267. The U pulse, which is generated by circuit 352, is normally used in standard T1 systems, as is well known bythose of ordinary skill in the art, to compare the actually received framing bit with the desired framing bit in order continuously to check that the incoming signal is correctly framed. Therefore, rather than use the actual framing bit as a criterionfor the beginning of the master frame, the U pulse, which is a 1 when the framing bit should be a 1, is used. Thus the beginning of a master frame is not dependent upon a line bit which may be in error. After counters 263 and 264 have been initialized by the output signal from master frame reset pulse generator 266, as inverted by inverter 168, the output of NAND gate 260, which contains a series of serial strobe pulses excluding thosecorresponding to the "keep-alive" bit and the framing bit, is applied to the count input of three-bit counter 263. After the eighth one of these strobe pulses the output of three-bit counter 263 will fall. At this time the eighth bit of the first bytehas been clocked from receive flip-flop 253 into shift register 251. Whenever output 252, the most significant bit of three-bit counter 263, falls, mode control flip-flop 271 in mode control circuit 269 is set. Flip-flop 271 had previously been clearedat the beginning of the master frame by the output from master frame reset pulse generator 266. Flip-flop 271 comprises a triggered flip-flop and hence any negative-going transition at the clock input will cause the flip-flop to change state. After the falling edge of output 252 of three-bit counter 263 occurs, the mode control flip-flop 271 output changes to a 1. Therefore, shift register 251 is ready to clock data in on a parallel basis before the next serial strobe occurs if it isdecided to do so. Note that mode control flip-flop 271 is set to the parallel mode after a complete eight-bit byte has been shifted into the shift register 251 irrespective of whether a parallel read-in will occur. If it is determined that transmissionwill occur, the parallel read-in to shift register 251 from select circuit 380 will occur prior to the falling edge of system clock 250. After the first byte of a packet has been completely read into shift register 251, a comparison identification byteof the packet must occur. To accomplish this identification, incoming packet status decoder 27 is used along with incoming packet status detector 273. To detect any empty packet, the outputs of shift register 251, inverted by inverters 274-281, are applied to NAND gate282 of incoming packet status decoder 272. If an empty packet is being passed through date multiplexer 58, the first eight-bit byte will necessarily be all 0's; therefore, since the inputs to NAND gate 282 are all the inverted outputs of shift register251, all of the inputs will be 1, thereby causing the output of gate 282 to be a 0. NAND gate 283 decodes the identification number (ID) of the packet. The outputs of shift register 251, along with the inverted outputs of shift register 251 frominverters 274-281, are supplied to two patch blocks 356 and 357. These patch blocks comprise supporting structures containing terminals which are appropriately interconnected so that when the ID of the attached terminal interface unit is present inshift register 251, all of the inputs to gate 283 will be 1 thereby causing its output to be 0. The outputs of NAND gates 282 and 283 are supplied to NOR gates 284 and 285, respectively of incoming packet status detector 273. Soon after the start of the first byte of a newly received packet, either OR gate 286 or NAND gate 287 of transmit packet type initialization pulse generator 363 will output a zero-going pulse to indicate the start of a new date packet or a newsigal packet, respectively. Note that these two pulses occur while the new packet is actually being read into shift register 251. This instant of time is after the parallel strobe corresponding to the last byte of the preceding packet and before theparallel strobe corresponding to the first byte of the next packet. The outputs of NAND gate 287 and OR gate 286 are applied to AND gate 288. Therefore the output of AND gate 288 will be a zero-going pulse during the first byte of a received packet,whether it is a signal packet or a data packet. The output of AND gate 288 is used to present flip-flop 289 and to clear flip-flops 290 and 291 of incoming packet status detector 273. By presetting flip-flop 289, a 0 output of either of NAND gates 282or 283 is able to propagate through NOR gates 284 or 285, respectively, as a 1. The clock pulse used to clock the J input of JK flip-flops 290 and 291 into the flip-flops is generated by the status read pulse generator 358 which comprises a NAND gate whose inputs are the output of mode control circuit 269 and the output fromsystem clock 250. After the first byte of a new packet has been fully clocked into shift register 251, as after every complete byte, the mode control circuit 269 output rises to a 1. At that instant however, the output from system clock 250 is in its low state. When the output from system clock 250 rises to a 1, the output of the status read pulse generator 358 falls to a 0. This output is used to clock flip-flops 289, 290, and 291 of incoming packet status detector 273. At that time, whatever signal is onthe J inputs of flip-flops 290 and 291 is transferred into those flip-flops and appear on their outputs. Also at this time flip-flop 289 returns to the state where its Q output is a 0 and its Q output is a 1. This is accomplished, as shown in FIG. 6E,by feeding the Q output back into the K input. Therefore, when the output of status read pulse generator 358 falls, the 1 input to the K input of flip-flop 289 will cause the Q output to go to 0 and the Q output to go to 1. With the Q output going to 1the outputs of NOR gates 284 and 285 remain 0 until flip-flop 289 is again present. The output of NOR gate 284 is applied to the J input of JK flip-flop 290 and the output of NOR gate 285 is applied to the J input of JK flip-flop 291. Thus if an empty packet is identified, flip-flop 290 is set so that its Q output goes to 1. If a terminal ID is decoded satisfactorily, flip-flop 291 is set so that its Q output goes to a 1. Either flip-flop will remain in the set state until cleared by the zero-going pulse generated by AND gate 288 during the start of the next packet. When the associated terminal interface unit wishes to transmit data, the first thing that data multiplexer 58 must do is to find either an empty packet in the line bit stream or a packet that is addressed to the associated terminal interfaceunit. In the latter case, the terminal interface unit removes the information in the packet addressed to it thereby leaving the packet empty. Next interface computer 62 must apply either or both of two distinct signals to data multiplexer 58. One signal, SENDD, indicates a request to transmit a data packet and the other, SENDS, indicates a request to transmit a signal packet. Thedata multiplexer identifies these two signals by means of request-to-send recognition circuit 292. Specifically, the SENDD signal is applied to AND gate 294 of request-to-send recognition circuit 292 and the SENDS signal is applied to AND gate 293. Theother inputs to these two gates come from transmit packet type indicator circuit 295, which comprises a flip-flop. When a signal packet is being received by the data multiplexer, the Q output of flip-flop 295 will be a 1, thereby enabling AND gate 293. When a data packet is being received by the data multiplexer, the Q output of flip-flop 295 will be a 1, thereby enabling AND gate 294. It is the function of AND gates 293 and 294 to gate the SENDD and SENDS signals with the packet type that is beingreceived at that time. Therefore, if signal packet transmission is requested and the date multiplexer is receiving a date packet, the outputs of AND gates 293 and 294 will both be 0 and hence the output of OR gate 296 will be 0. Therefore no outgoingdate packet or signal packet transmission will take place. The same holds true in the reverse situation where date packet transmittion has been requested and a signal packet is being received. Thus, in order to transmit a signal packet, a signal packetmust be used; and in order to transmit a date packet, a date TRANSMISSION OF A SIGNAL PACKET BY THE DATE MULTIPLEXER The manner in which a signal packet is transmitted by data multiplexer 58 can best be appreciated by a consideration of the following example. In this example it is assumed that the SENDS signal has been received, thereby causing one input toAND gate 293 to be a 1 and, further, that a signal packet has just begun to be received. Therefore, the Q output of flip-flop 295 will be a 1 thereby causing the output of AND gate 293 to be a 1. This 1 output, which is applied to the input of OR gate296 will cause that gate's output to be a 1. This 1 output is applied to the D input of D-type flip-flop 297, which is also contained in a request-to-send recognition circuit 292 shown in FIG. 6E. When the output of AND gate 288 rises, the signal onthe D input of flip-flop 297 will be transferred to its Q output. In this way it is insured that the SENDS signal is received and the match between received packet type and desired type of transmission is made before there is any parallel clocking intoshift register 251. This insures that there can be no errors generated as a result of signals changing at critical times. The Q output of flip-flop 297 of request to send recognition circuit 292 is applied to transmit-enable gate 298, which comprises an AND gate. The other input to transmit enable gate 298 comes from OR gate 299. The output signal from OR gate299, when it is a 1, indicates, as described above, that either an empty packet has been detected or the ID of the associated terminal interface unit was successfully decoded. In this situation both imputs to AND gate 298 are 1 thereby causing itsoutput to be a 1. The output of AND gate 298 is returned to interface computer 62 as the SEND line to indicate when data is being transmitted. The output of OR gate 299 is input to parallel strobe steering circuit 307. Thus when the output of OR gate299 is a 1, a parallel strobe is applied to shift register 251 as described below. The timing signals for the parallel insertion of data in shift register 251 are provided by parallel strobe generator 300 which comprises a one-shot multivibrator that is driven by the output of parallel strobe gating circuit 301 which comprisesan AND gate. To insure that the parallel strobe occurs at the proper time, one-shot multivibrator 304 is used as a delay and is triggered at the time the system clock 250 output rises. The Q output of delay 304 is applied to one of the inputs ofparallel strobe gating circuit 301. Delay 304 will output a pulse every time the system clock 250 output rises. However, the parallel strobe is required only after a complete eight-bit byte. Therefore, the Q output of delay 304 is gated with the modecontrol circuit 269 output by parallel strobe gating circuit 301. Hence only when the output from mode control 269 is a 1 does a pulse generated by delay 304 propagate to the output of parallel strobe gating circuit 301. At all other times the outputof gating circuit 301 is clamped to a 0 level by the mode control 269 output being a 0. When the Q output of flip-flop 271 of mode control 269 is a 1, the pulse generated by delay 304 will appear at the output of gate 301. The falling edge of thispulse triggers the parallel strobe generator 300. Thus it is seen that this strobe, denoted the "byte strobe" signal, is generated after every complete eight-bit byte has been completely read into shift register 251 irrespective of whether transmissionwill be initiated by the terminal interface unit. At the time that a complete byte of data has been assembled in shift register 251, the byte strobe from parallel strobe generator 300 clocks the data into register 251A. The eight output lines MDI from register 251A go to interface computer 62and terminal buffer 60. At the same time that data is clocked into register 251A, a pulse appears on line 308 if the data belongs to an empty packet or if the data belongs to a packet whose ID was recognized. The pulse on line 308 strobes the output ofselect circuit 380 into register 251A. Select circuit 380 comprises eight circuits, 380A through 380H, as shown in FIG. 6B. Each of these circuits contains the gates shown in detail in circuit 380A, that is, AND gates 382, 383, 384, 385 and 389, inverters 386 and 387, and OR gate388. Each of circuits 380A through 380H provides one bit of the eight bits of the data supplied to shift register 251 as follows. When interface computer 62 indicates that it wants to send, the output of transmit enable gate 298 will be a 1 if transmission is actually taking place. That output is a 0 when there is no request to send even if the opportunity exists. Inthese latter circumstances, AND gate 389 is inhibited and zero bytes are strobed into shift register 251. When a request to send has been received, and the output of gate 298 is a 1, AND gate 389 is enabled, and the source of data strobed into shiftregister 251 is determined by lines 392 and 393. When the byte of data to be loaded into shift register 251 is the first of a packet, then both lines 392 and 393 are equal to 1, AND gate 382 is enabled, and the data input to shift register 251 is taken from patch block 381. Patch block 381serves to generate the associated terminal's ID on eight lines 621. When the byte of data to be loading into shift register 251 is one of the second through the fourth bytes of a packet, then lines 392 and 393 are zero, AND gate 385 is enabled, and the data on the eight lines MDO from interface computer 62 arestrobed into shift register 251. When the byte of data to be loaded into shift register 251 is the fifth through thirty-eighth of a data packet, then line 392 is a 1 and line 393 is a 0, AND gate 383 is enabled, and the data on lines SDO from terminal buffer 60 are strobed intoshift register 251. Line 392 is the Q output of JK flip-flop 390 which is preset at the start of each packet by the output and AND gate 288. Flip-flop 390 is cleared by the falling edge of the output from mode control 269 which is applied to the flip-flop's clockinput. Thus flip-flop 390 remains set only during the first byte time of a packet. When flip-flop 390 is reset, NAND gate 391 is enabled and the signal on line 393 is the inverted form of the Q output of D-type flip-flop 366. That flip-flop is resetby the output of AND gate 288 at the start of a packet. The flip-flop 366 is set when the output of NAND gate 365 rises. This occurs when counter 264 contains the valve 8, and the most significant bit of counter 263 falls to zero. The byte strobe signal output by parallel strobe generator 300 is applied to gates 305 and 306 of parallel strobe steering circuit 307, and is also applied to interface computer 62 by line BS where it is used as a timing reference for theinterface computer 62 as described hereinbelow. If, as in the case previously descussed, the output of OR gate 299 is a 1, then AND gate 305 is enabled and the parallel strobe is allowed to propagate through it. The output of AND gate 305 is applied tothe parallel load clock input 308 of shift register 251 where a parallel read-in to shift register 251 takes place. If, on the other hand, the output of OR gate 299 is a 0, then AND gate 305 will be disabled and AND gate 306 will be enabled. The strobesignal generated by parallel strobe generator 300 will then be allowed to propagate through AND gate 306 but not through AND gate 305 and the parallel load clock input 308 of shift register 251 will not be strobed. The outputs of AND gates 305 and 306are applied to the input of OR gate 309. The output of OR gate 309 comprises the parallel strobe pulse irrespective of whether transmission has been enabled or not. The output of OR gate 309 is fed back to the input of OR gate 270 in mode controlcircuit 269 where it causes the Q output of mode control flip-flop 271 to return to its 0 state, thereby preparing shift register 251 for serial operation during the next incoming byte. During this time the byte present in shift register 251 is seriallyshifted out of the shift register through the injector circuit 302 to the transmit flip-flop 303 and out onto the line. Turning then to injector circuit 302 shown in FIG. 6G, this circuit is seen to provide the means for inserting bits into the serial bit stream to comply with system constraints. It inserts the "keep-alive" bit into the sixth slot of a linesubgroup, and it also inserts an error format into the bit stream whenever the transmit error steering circuit 310 indicates that it should do so. This error format comprises a 1bit in every line slot except for the "keep-alive" slot, which contains a 0in this format. The framing bit, however, is allowed to pass through injector circuit 302 in its original state without being altered in any way. Consider now a case of normal transmission where the error format is not transmitted. In this situation the output of OR gate 311 of transmit error steering circuit 310 will be a 0, thereby causing the output of NAND gate 312 of interior circuit302 to be a 1. Flip-flop 313 and OR gates 314 and 315 are used to insert the "keep-alive" bit into the bit stream. During times other than those when the "keep-alive" bit is to be inserted, the outputs of both of OR gates 314 and 315 will be 1. Inthis situation inputs 317, 318, and 319 to NAND gate 320 are 1. Input 316 is from the output of inverter 281 which inverts the output of the last cell of shift register 251. Therefore, the output of NAND gate 320 is 1. Hence, the output of NAND gate320 is seen to be in the same state as the last call of shift register 251. The output of NAND gate 320 is passed to the input of AND gate 322. The other input to AND gate 322 comes from OR gate 323. Since one of the inputs to OR gate 323 comes fromthe output of NAND gate 312, which is a 1 when the error format is transmitted, the output of OR gate 323 will be a 1 thereby enabling AND gate 322 and passing the output of NAND gate 320 through AND gate 322 to transmit flip-flop 303. On each fallingedge of system clock 250 the output of AND gate 322 is clocked into transmit flip-flop 303 where it is sampled during the next 1 state of system clock 250. A further description of the operation of transmit flip-flop 303 in conjunction with bipolarconverter 324 is contained hereinbelow. Consider now the injection of the "keep-alive" bit into the bit stream. First considering the normal situation, that is, the situation that applies to every "keep-alive" time slot except the one immediately following the framing bit. In thisnormal situation the set output of flip-flop 313 of injector circuit 302 is a 0, which holds the output of OR gate 315 to a 1. When the set output of flip-flop 313 is 0, the output of OR gate 314 will be a 1 whenever its input from inverter 355, that isD7, is 0. D7 is a 1 at all times except for when it falls to 0 for one system clock time. Therefore when the D7 pulse occurs, the output of OR gate 314 will go to a 0, causing the output of NAND gate 320 to go to a 1 and the output of AND gate 321 togo to a 0. Since, as stated above, the output of NAND gate 312 is at this time a 1, the output of AND gate 322 will also be a 1. Therefore a 1 will be clocked to transmit flip-flop 303 on the falling edge of system clock 250. Next considering the situation of injection immediately after receiving a framing bit, it can be seen that the "keep-alive" bit injected by using the pulse D7 would cause the "keep-alive" bit to be injected into the time slot immediatelyfollowing the desired one. In this particular situation the D6 pulse is used. Note that the time slot referred to precedes the transmission of the framing bit by data multiplexer 58. The DF pulse is used to preset flip-flop 313 of injector circuit302. With the Q output of flip-flop 313 a 1, the output of OR gate 314 will be a 1, and with the Q output a 0, the output of OR gate 315 will depend upon D6. When the pulse D6 goes to 0, the output of OR gate 315 will go to 0. With the output of ORgate 315 at 0, the output of NAND gate 320 is a 1, and the output of AND gate 322 is a 0. The output of OR gate 323 and NAND gate 320 each a 1 causes the output of AND gate 322 to be a 1. The output of AND gate 322 is clocked into transmit flip-flop303. Using the pulse D6 in this situation causes the "keep-alive" bit to be inserted in the proper line time slot, the sixth slot. Two system clock pulse periods after pulse D6 occurs, pulse D8 occurs, D8 being used to clear flip-flop 313. Theclearing of flip-flop 313 inhibits OR gate 315, therefore pulse D7 will again be the pulse that inserts a 1 into the "keep-alive" slot until the next framing bit is received. TRANSMISSION OF THE ERROR FORMAT BY THE DATA MULTIPLEXER When the output of OR gate 311 of transmit error steering circuit 310 is a 1, the error format is transmitted. In this format all the bit slots except the "keep-alive" bit slot contain 1's and the "keep-alive" bit slot contains a 0. In order topreserve synchronization in the system, the framing bit is allowed to propagate through the injector circuit 302 without alteration. Assume now that no transmission has been initiated and that therefore the transmit error disable circuit comprising flip-flop 325 has not been set to inhibit the error format. The Q output of flip-flop 325 is then a 1. The remaining input toNAND gate 312 comes from the output of OR gate 326. Assuming for the moment that flip-flop 327 is in its reset state, then the output of OR gate 326 is a 1. Therefore, since the three inputs to NAND gate 312 are all 1, the output of the gate is a 0. This causes the output of NAND gate 320 to be a 1. Except at those times when a signal is injected into the "keep-alive" slot through OR gates 314 or 315, the output of both of these gates is a 1. Since both of the inputs to AND gate 321 are 1, itsoutput is a 1 thereby causing the output of OR gate 323 to be a 1. Since both inputs to AND gate 322 are also 1, its output is a 1. Hence a 1 level is applied to transmit flip-flop 303 to be clocked into it on the falling edge of the next pulse fromsystem clock 250. Now consider the "keep-alive" slot. As previously described, the D7 pulse normally causes a 1 to be inserted into the "keep-alive" slot. In this situation, when the D7 pulse goes to 0, thereby causing the output of OR gate 314 to go to 0, thecorresponding input to AND gate 321 goes to 0, and therefore the output of AND gate 321 will be a 0 for the time that the D7 pulse is present. With the output of NAND gate 312 a 0, and the output of OR gate 314 a 0, both inputs to OR gate 323 are 0thereby causing its output to be 0. Thus one input to AND gate 322 is 0 which causes its output to be a 0. A 0 is thereby clocked into transmit flip-flop 303 at the time of the occurrence of the "keep-alive" slot. As previously described, immediately,following the receipt of a framing bit, the "keep-alive" bit must be generated one slot earlier than usual in order that it be in the correct line time slot. This is accomplished by presetting flip-flop 313 by using the DF pulse. This, therefore,enables OR gate 315 and disables OR gate 314. Note that in this context "enable" means applying a 0 input to OR gate 315. When the D6 pulse appears from inverter 261, the output of OR gate 315 goes to 0, causing the output of AND gate 321 to go to a 0,thereby making one input to OR gate 323 a 0. Since the other input to OR gate 323 comes from NAND gate 312, whose output is also a 0, the output of OR gate 323 is a 0. Thus the output of AND gate 322 will also be a 0 and a 0 will be clocked into the"keep-alive" time slot. As soon as the D8 pulse occurs, flip-flop 313 is cleared so that until the framing bit occurs again the D7 pulse will be used to fill the "keep-alive" slot. Another special situation occurs when the framing bit is clocked into shift register 251. In order to preserve line synchronization, it is necessary to transmit the framing bit exactly as it was received without regard to the action of injectorcircuit 302. Note that one of the inputs to NAND gate 312 comes from the output of gate 326, which is a 1. In the normal situation, flip-flop 327 is in its reset state with its Q output equal to 1. The Q output of D-type flip-flop 327 is fed back to its D input so that when the clock lead is pulsed the Q output of the flip-flop will go to 0. Theinput to the clock lead of flip-flop 327 comes from the Q output of flip-flop 313. The DF pulse presets flip-flop 313 to allow the unaltered framing bit to pass through injector circuit 302 and the following D8 pulse clears it. When the D8 clear pulseoccurs, the Q output goes from a 0 to a 1. This 0 to 1 transition causes the signal on the D input of flip-flop 327 to transfer to the Q output of flip-flop 327 and its complement to the Q output. Therefore on the D8 pulse immediately following the DFpulse the Q output of flip-flop 327 is fed to one input of OR gate 326. The other input to gate 326 is from the D1 pulse which is output from inverter 328. This pulse is normally a 1 except during the time of the D1 time slot at which time it is a 0. When the D1 pulse does go to 0, and with the other input to ORgate 326 also a 0, the output of OR gate 326 also goes to 0. This 0 signal applied to the input of NAND gate 312 causes the output of NAND gate 312 to be forced to a 1. With the output of NAND gate 312 a 1 and the output of both gates 314 and 315 a 1,inputs 317, 318 and 319 of gate 320 are 1. With the output of NAND gate 312 a 1 the output of OR gate 323 is also a 1, therefore AND gate 322 is enabled and the inverted output of the end cell of shift register 251, which is the framing bit, istransferred on input line 316 to NAND gate 320 where it is inverted again and passes through AND gate 322 to transmit flip-flop 303. Hence at the next clock pulse from system clock 250, the unaltered framing bit is transmitted. When flip-flop 313 is cleared by the D8 pulse, the output of OR gate 314 returns to its normal 1 value, thereby removing the inhibit from NAND gate 312 and returning the injector circuit 302 to the previous condition whereby the 1 bit errorsignal from OR gate 311 causes the output of NAND gate 312 to be 0, thereby causing the error format to be properly injected into the bit stream. TRANSMIT ERROR DISABLE When transmission is initiated by a terminal interface unit it is desired that incoming errors do not cause injector circuit 302 to output a signal to transmit flip-flop 303 indicating that errors were received. When transmission is to beinitiated, it is undesirable and unnecessary to send out only an error format. The transmit error disable circuit 325, which comprises a flip-flop, inhibits transmission of the error format in this case as follows. Whenever the output of OR gate 299 is a 1, this 1 output is applied to the D input of D-type flip-flop 325. This 1 input causes the Q output of flip-flop 325 to fall to 0 upon being clocked by the rising edge of parallel strobe generator 300. This 0 input is applied to NAND gate 312 and causes the output of NAND gate 312 to remain a 1 as long as the Q output of flip-flop 325 is a 0. This inhibits the transmission of the error format by transmit flip-flop 303. Once flip-flop 325 has been set, it remains in that state until the first parallel strobe associated with the next packet occurs. At that time, if no transmission is to be made, the output of OR gate 299 will be 0. This 0 is applied to the Dinput of D-type flip-flop 325 and causes its Q output to go to 0 and its Q output to go to 1 when the first parallel strobe associated with the next data packet occurs. Since the reset output of flip-flop 325 is one of the inputs to NAND gate 312, theoutput of NAND gate 312 will now be determined by its other two inputs. TRANSMIT FLIP-FLOP AND BIPOLAR CONVERTER OF THE DATA MULTIPLEXER As shown in FIG. 6G, the output of AND gate 322 of injector circuit 302 is applied to the input of flip-flop 303 the tansmit flip-flop. With each falling edge of system clock 250, the output of AND gate 322 is clocked into transmit flip-flop303. Once a bit has been clocked into this flip-flop no further insertions or changes can be made. The output of flip-flop 303 is fed to AND gate 329 of biopolar converter 324. Bipolar converter 324 converts the unipolar logic level of the data multiplexer to a line-compatible bipolar signal. The output of flip-flop 303 that was clocked in on the falling edge of system clock 250 is sampled by AND gate 329 during thenext clock pulse interval. If a 1 bit was clocked into flip-flop 303 the output of AND gate 329 is a 1 during the next clock pulse interval. If a 0 was clocked into flip-flop 303 the output of AND gate 329 is a 0 during the next clock pulse interval. In the case where the output of AND gate 329 is a 0, both AND gates 331 and 332 will have 0 output thereby causing both of transistors 334 and 335 to be off. With these transistors both off, zero volts will appear across the secondary winding oftransformer 336. In the situation where the output of AND gate 329 is a 1, the output of either AND gate 331 or 332 will be a 1 causing transistor 334 or 335, respectively, to turn on during the duration of the system clock pulse. This action causeseither a positive or negative pulse to appear at the secondary winding of transformer 336. Flip-flop 330 causes adjacent one-bit line pulses to be of opposite polarity. Assume, for example, that the Q output of flip-flop 330 is a 1, thereby enabling AND gate 331. When the system clock pulse falls, the output of AND gate 331 falls,thereby causing flip-flop 330 to change to a state where its Q output is a 1. AND gate 332 is now enabled for the next 1 bit that is to be transmitted. Since flip-flop 330 requires a falling edge to change state, it will only change state after a 1 bithas been transmitted. In this manner adjacent 1 bits on the line will be of opposite polarity. ERROR DETECTION Error detection occurs in two different circuits in data multiplexer 58. First, there is an error detector that detects the 1 bit inserted in the "keep-alive" slot. The output of receive flip-flop 253 is applied to the input of inverter 337 ofsix-slot error detector 262. The output of inverter 337 is fed to the D input of flip-flop 338. When the signal in the "keep-alive" slot is a 1, the output of inverter 337 will be a 0 thereby applying a 0 to the D input of flip-flop 338. When thesignal in the "keep-alive" slot is a 0, the output of inverter 337 will be a 1, thereby applying a 1 to the D input of flip-flop 338. The clock for flip-flop 338 comes from the strobe steering circuit 255, which supplies a clock pulse to the clock input of flip-flop 338 corresponding to the "keep-alive" slot only as has been previously explained. A 0 input clocked into theflip-flop will cause its Q output to apply a 1 to the input of AND gate 339, thereby indicating an error. The other error detecting circuit is the PCM error detecting circuit in receive unit 352. This circuit outputs a PCM ERROR pulse whenever the bipolar nature of the incoming signal has been violated by two adjacent 1 bits being of the samepolarity. The pulse is of the same width and in the same position as a line pulse that violates the bipolar code. The PCM ERROR pulse is aplied through inverter 340 to the other input of AND gate 339. Under normal conditions the output of inverter 340is a 1. When an error is detected, its output will go to 0. When either of the two inputs to AND gate 339 go to 0, thereby corresponding to an error, the output of AND gate 339 goes to 0. The output of AND gate 339 is applied to one input of OR gates 341 and 342 of incoming packet type detector and steering circuit 343. The other input to these two gates comes from flip-flop 344, which steers the error signal to the proper one ofOR gates 341 and 342. It is important that the packet type, either signal or data, in which the error was detected be noted so that the correct packet will be made to contain the error format when it is transmitted. Flip-flop 344 indicates which typeof packet is currently being received. It derives its preset signal from NAND gate 345. The inputs to NAND gate 345 are the pulse D8 and outputs 264A, 264D and 264F of six-bit counter 264 and output 252 of three bit counter 263. When the output ofNAND gate 345 falls to 0, thereby presetting flip-flop 344, a 0 input to OR gate 341 corresponding to a detected error is allowed to propagate to its output. Note that flip-flop 344 is preset and set using the digit pulse corresponding to the last timeslot in the packet. In order to insure that a PCM error detected in the first bit of a new packet is directed to the flip-flop corresponding to that new packet, it is necessary to use the digit pulse corresponding to the last line bit of the previous packet. Theappropriate steering is provided by flip-flop 344. When flip-flop 344 is in the preset state, any errors detected and thereby output as a 0 by AND gate 339 will be directed through OR gate 341 to flip-flop 346 in incoming error detector 347. The 0 signal will serve to preset flip-flop 346thereby indicating that there was an error in the incoming signal packet. Flip-flop 346 will remain in this state until the signal packet has been completely transmitted out of shift register 251. In the same manner, when flip-flop 344 is in the resetstate as a result of NAND gate 348 applying a 0 pulse to its clear input, its Q output will be 1. Therefore any 0 output of AND gate 339 will propagate through OR gate 342 to preset flip-flop 349. Since it is possible that an error may be detected in the first byte of a new incoming packet while the last byte of the previous packet is still being transmitted, the error format is not transmitted until the new packet is being transmitted. This is insured by the action of transmit error steering circuit 310. Flip-flop 350 forms the basis of this circuit. The JK inputs to this flip-flop come from the Q and Q outputs, respectively, of flip-flop 295. Flip-flop 295 indicates the type ofpacket that will be transmitted starting with the serial strobe following the next parallel load strobe. The clock pulse of flip-flops 350, 346, and 349 is derived from the Q output of flip-flop 289 in incoming packet status detector 273. Flip-flop 289is normally in the reset state. The output of gate 288, which is a zero-going pulse to indicate the start of a new data packet or a new signal packet, is applied to the preset input of flip-flop 289. This action occurs after the last parallel loadstrobe of the previous packet and before the first parallel load strobe of a new packet. The output of the status read pulse generator 358 is applied to the clock input of flip-flop 289. When the output of status read pulse generator 358 falls, which action precedes the parallel load strobe corresponding to the first byte of a newpacket, the Q output of flip-flop 289 will go to 0. This is the result of tying the Q output back to the K input with the J input grounded. The falling edge of the Q output is the clock for flip-flops 346, 349, and 350. The time at which this happensis immediately preceding the parallel load strobe corresponding to the first byte of a new packet. The transmit error steering circuit 310 will therefore have time to settle and to apply the proper signal to injector circuit 302 in time for the nextserial strobe to shift register 251. The output of transmit error steering circuit 310 is also applied to interface computer 62 on line BPER. Flip-flop 350 has the secondary function of providing the means to clear flip-flops 346 and 349 at the appropriate time. For example, assume that an error is detected in the signal packet thereby causing flip-flop 346 to preset at theappropriate time. Also assume that signal packet transmission has been completed and data packet transmission is about to start. Therefore, sometime between this time and the time the next signal packet is received, flip-flop 346 must be cleared sothat if no new signal packet errors are detected, the next signal packet can be transmitted without the error format. To accomplish this, the Q output of flip-flop 350 is applied to the K input of flip-flop 346. Likewise, the Q output of flip-flop 350is applied to the K input of flip-flop 349 to accomplish this same clearing function for the data packet. Assume further that the data multiplexer 58 has just completed transmitting the signal packet in which the Q output of flip-flop 350 is still high. When the clock for flip-flops 350, 346, and 349 occurs, which is prior to the parallel loadstrobe corresponding to the first byte of a packet, the 1 on the Q output of flip-flop 350 is fed back to the K input of flip-flop 346 causing flip-flop 346 to go to the state where its Q output is 0. Therefore flip-flop 346 is cleared ready to receivean error signal on its preset lead at the next time that a signal packet is being received. The same situation holds true when a data packet is being transmitted. The Q output of flip-flop 350 will be a 1 and the Q output of flip-flop 350 will be a 0. Therefore when the clock pulse generated by flip-flop 289 of incoming packet status detector 273 occurs, the 1 output of flip-flop 350 on its Q output that is fed back to the K input of flip-flop 349 will cause flip-flop 349 to clear itself and be readyto accept an error signal on its preset lead the next time that a data packet is being received. As mentioned above, a subset of the apparatus comprising data multiplexer 58 can be used to implement byte disassembler 40 and byte assembler 64. The inputs to and outputs from data multiplexer 58 have been labeled A through E in FIG. 2B and inFIGS. 6A-6H to facilitate the following discussion. BYTE DISASSEMBLER Turning then to byte disassembler 40, this device can be made from the apparatus shown in FIGS. 6A-6H by connecting the eight lines 38 shown in FIG. 2B to the eight lines labeled "C" in FIG. 6B, and by connecting the pair of wires labeled "B" inFIG. 6G to terminal matching unit 42 shown in FIG. 2B. Lines A, D and E shown in FIGS. 6C, 6B, and 6A are not used by byte disassembler 40. Additionally, since byte disassembler 40 must transmit all packets it receives rather than merely those having aparticular identification number, patch blocks 356 and 357 shown in FIG. 6A must be reconfigured so as to match any zero or non-zero identification number. Further, flip-flop 390 shown in FIG. 6F must be replaced by a patch block configured so that thesignals appearing on lines 394 and 392 are each a 0. BYTE ASSEMBLER Byte assembler 64 can be made from the apparatus shown in FIGS. 6A-6H by connecting the eight lines labeled "E" in FIG. 6A to loop receive buffer 66 shown in FIG. 2B and by connecting the pair of wires labeled "A" in FIG. 6C to terminal matchingunit 42 shown in FIG. 2B. Lines B, C, and D shown in FIGS. 6B and 6C are not used by byte assembler 64. Additionally, since byte assembler 64 must transmit all packets with non-zero identification numbers that it receives rather than merely thosehaving a particular identification number, patch blocks 356 and 357 shown in FIG. 6A must be reconfigured to match any non-zero identification number. Further, the output of NAND gate 282 must be applied to patch block 356. TERMINAL BUFFER Terminal buffer 60 of terminal interface unit 17 shown in FIG. 2B is shown schematically in FIG. 7A. As shown in FIG. 7A, terminal buffer 60 comprises four major parts: data receive buffer 450, data transmit buffer 451, channel select circuit452, and channel break circuit 453. Data receive buffer 450 receives data from data multiplexer 58 on eight lines MDI and transfers it to digital device 18 by means of eight lines 455. Data receive buffer 450 assembles a complete packet of data before any of it is made avaiable todigital device 18. Similarly, data transmit buffer 451 receives data from digital device 18 on eight lines 456 and transfers it to data multiplexer 58 on eight lines SDO. Again, a complete packet of data is assembled before it is transmitted. Channel select circuit 452, in response to a command on eight lines 458 from digital device 18, selects a channel for the data transmission and passes this information to interface computer 62 on eight lines SBC. Finally, channel break circuit 453 transfers a signal from interface computer 62 on eight lines RCH that notifies digital device 18 about a change in status of a non-selected channel. This information is transferred to digital device 18 by eightlines RCH. Each of the four functional units 450, 451, 452, and 453 of terminal buffer 60 operates under the control of both digital device 18 and interface computer 62. The manner in which this control is exercised and the manner in which each of themajor blocks shown in FIG. 7A accomplishes its function may best be appreciated by means of FIGS. 7B-7F which illustrate terminal buffer 60 in greater detail. FIG. 7B illustrates the timing signals used in the operation of terminal buffer 60. Timing signals for the entire terminal interface unit 17 are generated by data multiplexer 58 and transmitted to terminal buffer 60 and interface computer 62. The key timing signal is the byte strobe signal appearing on line BS in the datamultiplexer logic diagram of FIG. 6E. This strobe occurs forty-two times during each master frame and coincides with the complete assembly of one eight-bit byte in register 251A of data multiplexer 58. At the time data multiplexer 58 issues a bytestrobe it puts the eight-bit byte of data into register 251A and simultaneously reads data from one set of its data input lines, either MDO or SDO. When the first four byte strobes in a master frame occur, the four eight-bit bytes of the signal packetare put on the data output lines MDI, and when the subsequent thirty-eight byte strobes in one master frame occur the thirty-eight bytes of a data packet are put on the data multiplexer output lines MDI. The time interval following one byte strobe isidentified by the name of the byte which for that time interval is available on the eight data multiplexer output lines MDI. The four time intervals during which the four bytes of a signal packet are available are known respectively as S.sub.0, S.sub.1,S.sub.2, and S.sub.3. The thirty-eight time intervals during which the thirty-eight bytes of a data packet are available are known respectively as D.sub.0, D.sub.1, et cetera, through D.sub.37. Each of these time intervals starts when the byte strobeoccurs and ends just before the occurrence of the next byte strobe. DATA RECEIVE BUFFER FIG. 7C is a logic diagram of data receive buffer 450 shown in FIG. 7A. This unit assembles and stores the thirty-two bytes of data from a data packet in response to a pulse being applied on line RCV to flip-flop 468. This