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Electronic musical instrument |
| RE31090 |
Electronic musical instrument
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| Patent Drawings: | |
| Inventor: |
Yamaga, et al. |
| Date Issued: |
November 30, 1982 |
| Application: |
06/221,578 |
| Filed: |
December 31, 1980 |
| Inventors: |
Aoki; Eiichiro (Hamamatsu, JP)
Nakada; Akira (Hamamatsu, JP)
Okumura; Takatoshi (Hamamatsu, JP)
Oya; Akiyoshi (Hamamatsu, JP)
Uchiyama; Yasuji (Hamamatsu, JP)
Yamaga; Eiichi (Hamamatsu, JP)
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| Assignee: |
Nippon Gakki Seizo Kabushiki Kaisha (Hamamatsu, JP) |
| Primary Examiner: |
Witkowski; S. J. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Spensley, Horn, Jubas & Lubitz |
| U.S. Class: |
84/617; 84/627; 84/655; 984/336 |
| Field Of Search: |
84/1.01; 84/1.03; 84/1.24; 340/365R; 340/365S |
| International Class: |
G10H 1/18 |
| U.S Patent Documents: |
4134320; 4134321; 4141268; 4142433 |
| Foreign Patent Documents: |
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| Other References: |
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| Abstract: |
A tone production assignment circuit produces control information representing assigned key code, key-on etc. Such information has a large number of bits with respect to each channel. A multiplexing circuit has output lines the number of which is smaller than the bit number of the information and divides the information with a plurality of time slots with respect to one channel. The multiplexing circuit is controlled by a signal from a timing signal generation circuit. The multiplexing circuit is capable of rearranging information for transmitting information required for the respective individual channels and also capable of inserting a timing data in an available time slot. A multiple data analysis circuit decodes the information provided by the multiplexing circuit. Tone generators are provided for the respective channels and each one of them functions to latch only corresponding information among the decoded information by a latch circuit. |
| Claim: |
What is claimed is:
1. A keyboard electronic musical instrument having a specified number of tone production channels connected by a number of output lines, comprising:
a tone production assignment circuit for assigning production of a tone selected by depression of a key to one of said channels and generating key information representing the note name of the assigned tone and key-on information representingdepression or release of the key with respect to each channel to which tone production has been assigned, said key information and said key-on information for each channel together having a certain total number of bits;
data dividing means, connected to said assignment circuit and having parallel output lines of a number which is smaller than said certain total number of bits of the key information and the key-on information for each channel, for dividing thekey information and the key-on information of the tone assigned to the particular channel into groups of data, each group having a number of bits matching the number of said output lines;
data multiplexing means, cooperatively connected to said data dividing means, for time division multiplexing said groups of divided data by delivering each group of data on said output lines in parallel data format, said groups being deliveredsequentially in time division multiplexed order; and
a tone generator for generating the tone assigned to each channel in accordance with the multiplexed data.
2. An electronic musical instrument as defined in claim 1 wherein said data multiplexing means comprises means for periodically inserting data representing a reference timing in said output lines.
3. An electronic musical instrument as defined in claim 2 wherein said data multiplexing means further comprises means for inserting control information used commonly throughout all of the channels or used for only a specified channel in any oneor more of the output lines at a suitable timing when component data of the key information or the key-on information is not provided on said one or more of the output lines.
4. An electronic musical instrument as defined in claim 1 wherein said data dividing means comprises:
first through N-th selection means for dividing said total number of bits of the key information and the key-on information into N groups (where N represents an integer of 2 or a larger number) with respect to each of the channels and forsequentially selecting each of the divided groups of data with a time delay; and wherein said data multiplexing means comprises:
gating means for selecting one or more control information used commonly throughout all of the channels or for only a specified channel at a predetermined timing;
OR gate groups having a specified number of parallel output lines for combining the outputs of said first through N-th selection means and said gating means;
control means for generating first through N-th pulses sequentially and repeatedly with a delay of a predetermined time period for controlling the timing of sequential selection by said first through N-th selection means;
timing pulse generation means for generating a timing pulse which controls the timing of selection by said gating means; and
reference data insertion means for inputting a control pulse generated at a certain reference time within each repetitive cycle in which information of all of the channels is multiplexed, and for supplying a unique group of data representing thereference timing to said OR gate groups in response to said input control pulse.
5. An electronic musical instrument as defined in claim 4 which further comprises multiplexed data distribution means which receives the multiplexed data provided by said data multiplexing means through said output lines and distributes each ofthe multiplexed data to each of separate tone generators in accordance with the channel of the multiplexed data.
6. An electrical musical instrument as defined in claim 5 wherein said multiplexed data distribution means comprises:
means for detecting the data representing the reference timing from among the multiplexed data supplied by said data multiplexing means for generating a reference pulse in response to the detection;
shift means for successively shifting the reference pulse; and
latch means for successively latching the multiplexed data provided by said data multiplexing means in accordance with the reference pulse successively shifted in said shift means thereby to distribute the key information and the key-oninformation contained in the multiplexed data to the respective channels. .Iadd. 7. A polyphonic keyboard electronic musical instrument having a specified number of tone production channels, comprising:
key information generating means for generating key information relating to depressed ones among keys in a keyboard,
channel assignment means for assigning said key informations to available ones of the specified number of tone production channels,
multiplexing means for time division multiplexing said assigned key informations by delivering each key information in parallel data format, said key informations being delivered sequentially in time division multiplexed order;
tone generating means having the same number of tone generators as said specified number of tone production channels, each of said tone generators corresponding to a respective one of said tone production channels, and
demultiplexing means connected between said multiplexing means and said tone generating means for demultiplexing said delivered key informations and for supplying each demultiplexed key information to the tone generator corresponding to the toneproduction channel to which said delivered key information is assigned, so that said tone generators respectively generate tone signals in accordance with the respective supplied key information. .Iaddend. .Iadd. 8. A polyphonic electronic musicalinstrument comprising:
keyboard means having a plurality of keys,
key information generating means for generating key information relating to depressed ones among said keys,
channel assignment means for assigning said key information to available ones of a specified number of tone production channels,
envelope information generating means for generating envelope information serving to determine an envelope characteristic of a tone, said envelope information being used commonly throughout all of said tone production channels,
multiplexing means connected to said channel assignment means and said envelope information generating means for transmitting said key information and said envelope information over output lines using a predetermined number of time slots, each ofsaid key information being allotted to a predetermined time slot in accordance with the assigned tone production channel of the key information and the envelope information being allotted to a predetermined time slot on one or more of said output linesin which said key information is not provided,
tone generating means having tone generators each of which corresponds to a respective one of the tone production channels,
envelope imparting means having envelope imparting circuits each of which is connected to a respective one of said tone generators; and
demultiplexing means connected to said output lines for supplying said transmitted key information to the tone generators corresponding to said tone production channels to which said transmitted key information is assigned respectively and forsupplying said transmitted envelope information to all of said envelope imparting circuits, said tone generators generating tone signals in accordance with said supplied key information respectively and said envelope imparting circuits imparting theenvelope characteristic to the corresponding tone signals. .Iaddend. .Iadd. 9. In a keyboard polyphonic electronic musical instrument of the type having plural tone generator channels, the number of such channels being considerably fewer than thetotal number of keys, the improvement comprising:
memory means storing a channel assignment table containing for each assigned channel a key code and associated key depression state data for the selected key which is assigned to that channel,
data transmission lines,
time division multiplex means for repetitively, consecutively transmitting the contained key codes and associated key depression state data via said data transmission lines during corresponding intervals in each time division multiplex cycle, and
demultiplexer means, connected to said data transmission lines and receiving said time division multiplex key codes and data, for demultiplexing the same and supplying to each tone generator channel only the demultiplexed key code and associatedkey depression state data for the selected key assigned to that channel. .Iaddend. .Iadd. 10. An electronic musical instrument according to claim 9 further comprising:
envelope information generating means for producing envelope ascertaining information for common usage by all of said tone generator channels,
said multiplexer means including circuitry for transmitting said envelope ascertaining information from said envelope information generating means onto said data transmission lines as part of each time division multiplex cycle, and
an envelope imparting circuit in each tone generator channel, each envelope imparting circuit utilizing said transmitted common envelope ascertaining information and the key depression state data for the corresponding channel to impart therequisite envelope to the tone generated in that channel. .Iaddend..Iadd. 11. An electronic musical instrument according to claim 10 wherein said multiplexer means gates said envelope ascertaining information onto said data transmission lines at thebeginning of each time division multiplex cycle. .Iaddend. .Iadd. 12. A keyboard electronic musical instrument having a specified number of tone production channels connected by a number of output lines, comprising:
a tone production assignment circuit for assigning production of a tone selected by depression of a key to one of said channels and generating key information representing the note name of the assigned tone and key-on information representingdepression or release of the key with respect to each channel to which tone production has been assigned, said key information and said key-on information for each channel together having a certain total number of bits;
a number of parallel output transmission lines;
data multiplexing means for time division multiplexing said key information and key-on information by delivering the same on said output transmission lines in parallel data format, said information being delivered sequentially in time divisionmultiplexed order,
a tone generator for generating the tone assigned to each channel in accordance with the multiplexed information, and
means for inserting envelope control information used commonly throughout all of the channels or used for only a specified channel in any one or more of the output transmission lines at a suitable timing when component data of the key informationor the key-on information is not provided on said one or more of the output transmission lines. .Iaddend. .Iadd. 13. In a keyboard electronic musical instrument of the type having a small number of tone generator channels, for which channels key codeand key depression state data are supplied in time division multiplex format, the improvement comprising:
assignment memory means containing a channel assignment table in which there is a data entry position for each tone generator channel,
first means for ascertaining by comparison with prior entered data in said table whether a key code for a selected key is already entered in said table and if not, for entering the key code and associated key depression state data for thatselected key into an available data entry position of said table,
second means for reading out all of the entered key codes and associated key depression state data from said channel assignment table in a certain order and in certain delivery time zones for time division multiplex transmission to said tonegenerator channels, and
timing control means, cooperatively connected to said first and second means, for establishing a timing and order for key code and data entry into said table by said first means, and for establishing a different timing and order for readout andtransmission of key codes and data from said table by said second means. .Iaddend. |
| Description: |
BACKGROUND OF THE INVENTION
This invention relates to a compound tone type electronic musical instrument employing a tone production assignment circuit.
DESCRIPTION OF THE PRIOR ART
An electronic musical instrument is known in the art in which a tone selected by key depression is assigned to a suitable tone production channel by a tone tone production assignment circuit, and the tone is produced by using the tone generatorof that channel. In producing a tone by using a tone generator, there are a number of pieces of information as to the tone which should be supplied to the tone generator. In a device disclosed by the specification of U.S. Pat. No. 3,882,751 entitled"Electronic Musical Instrument" or by the specification of U.S. Pat. No. 4,114,495, entitled "Channel Processor", in addition to information (key code) representative of a key name assigned to a relevant channel, information representative of thedepression of the key, information representative of the release of the key, and clear information representative of the fact that the assignment to the channel has been cancelled are outputted by a tone production assignment circuit and are applied to atone generator. The information (key code) representative of a key name consists of a note code representative of a note, an octave code representative of an octave, and a keyboard code representative of a keyboard. If key depression information andother control data are added to the aforementioned codes, data of the order of ten to fifteen bits is applied to the tone generator section from the tone production assignment section. In manufacturing the tone production assignment section and the tonegenerator section in the form of integrated circuits, it is required to provide as many pins as the number of bits of data used between the two sections. Therefore, as the number of bits of data supplied to the tone generator section from the toneproduction assignment circuit increases, the number of pins in the integrated circuit is increased, which will be an obstacle to miniaturization of the sections.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an electronic musical instrument including tone generators individually functioning for each of tone production channels, in which the number of wires between the tone production assignmentcircuit and the tone generators is remarkably reduced by supplying information concerning tones assigned to the respective channels to the tone generators in a time division multiplexed form. It is another object of the invention to provide anelectronic musical instrument in which, in distributing the time division multiplexed information to the respective tone generators, timing for the distribution is determined by using single reference data representing a reference timing in a time slottrain and information transmitted from the tone production assignment circuit to the tone generators thereby is simplified.
These and other objects and features of the present invention will become apparent from the description made below in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a block diagram illustrating one example of an electronic musical instrument according to this invention;
FIG. 2 is a diagram explaining a method of illustrating various circuit elements;
FIG. 3 is a timing chart of various signals employed for controlling a variety of circuits included in a channel processor shown in FIG. 1;
FIG. 4 is a block diagram illustrating a timing signal generating circuit in FIG. 1, in detail;
FIG. 5 is a detailed block diagram illustrating a key code memory circuit, a key code comparison circuit and a data multiplex circuit shown in FIG. 1;
FIG. 6 is a block diagram illustrating an assignment control circuit and an attack system key-on signal generating circuit shown in FIG. 1, in detail;
FIG. 7 is also a block diagram illustrating a truncate circuit and an automatic chord key-on signal generating circuit in FIG. 1 in detail;
FIG. 8 is a timing chart for a description of the operation of the data multiplex circuit shown in FIG. 5;
FIG. 9 is a diagram for a description of the contents of data for every time slot with respect to data KC.sub.1 -KC.sub.4 outputted by the data multiplex circuit shown in FIG. 5;
FIG. 10 is a clock diagram showing one example of a digital tone generator shown in FIG. 1.
FIG. 11 is a block diagram illustrating a multiplex data analysis circuit in FIG. 10 in detail;
FIG. 12 is a timing chart for a description of the operation of the multiplex data analysis circuit shown in FIG. 11;
FIG. 13 is a block diagram illustrating in detail the submultiple frequency wave signal generator shown in FIG. 10;
FIG. 14 is a timing chart showing a state of submultiple frequency data generated in series by the submultiple frequency wave signal generator;
FIG. 15 is a circuit diagram illustrating in detail an example of the upper keyboard tone generator shown FIG. 10;
FIG. 16 is a circuit diagram illustrating in detail an example of each of the lower keyboard tone generator and the automatic chord tone envelope control section shown in FIG. 10; and
FIG. 17 is a circuit diagram showing the pedal keyboard tone generator shown in FIG. 10.
DETAILED DESCRIPTION OF THE INVENTION
Description of the general arrangement of this invention
This invention will be described with reference to its preferred embodiment illustrated in the accompanying drawings.
Referring to FIG. 1, a keyboard section 10 comprises an upper keyboard, a lower keyboard, a pedal keyboard, and a variety of switches for control. A key coder .Iadd.or key information generating means .Iaddend.11 operates to detect the on-offoperations of the keys and the switches in the key-board section 10, thereby to output pieces of information representative of depressed keys and various pieces of control information. A channel processor 12 comprises a tone production assignmentcircuit .Iadd.or channel assignment means .Iaddend.13, a data multiplex circuit 14, and a timing signal generating circuit 15 for the above-described assignment and multiplex. The tone production assignment circuit 13 is to assign a depressed key (or atone to be produced) to any of a certain number (sixteen, for instance) of tone production channels, and the assignment is carried out in accordance with information (key code) representative of a depressed key from the key coder 11. In this toneproduction assignment circuit 13, a key code memory circuit 17 has a certain number of memory positions, which corresponds to the number of tone production channels, the key code memory circuit 17 having a gate in its input side. As a result of anassignment operation, a key code N.sub.1 -B.sub.3 delivered from the key coder 11 is stored in one of the memory positions in the key code memory circuit 17. The fundamental conditions in the assignment operation of the tone production assigning circuit13 are as follows:
(A) The assignment should be done for a memory position where no storage is made (or an empty channel), and
(B) A key code representative of the same key as a key (being depressed) whose tone is being produced should not be stored, in duplication, in a plurality of memory positions.
However, as far as the condition (B) concerns, in the case where the same key code as an old key code (not used for tone production) which is stored in a channel which is not in tone production (not in key depression) is newly supplied upon keydepression, the new key code may be assigned to a different channel. Such assignment control is effected in the case of "key on again" described later.
A key code comparison circuit 18 operates to compare a key code N.sub.1 -B.sub.3 applied thereto from the key coder 11 with an assigned key code N.sub.1 *-B.sub.3 * which has been stored in the memory circuit 17, and it outputs a comparisonoutput EQ depending on coincidence or non-coincidence. An assignment control section 19 operates to detect whether the assignment conditions such as the above-described conditions (A) and (B) are satisfied or not. Upon satisfaction, the section 19outputs a load signal LD which is applied to the key code memory circuit 17, thereby to cause the latter 17 to store an input key code N.sub.1 -B.sub.3. In addition, the assignment control section provides a key-on signal KO.sub.1 or KO.sub.2representative of the fact that a key assigned to a channel is being depressed.
An attack type key-on signal generating circuit 20 operates when an attack type envelope waveform is employed as a musical tone amplitude envelope, and the circuit 20 serves to reduce the generation time width of the key-on signal KO.sub.1 orKO.sub.2 provided by the assignment control section 19 to a relatively short time width (of the order of 10 ms, for instance). A truncate circuit 21 is to detect a channel to which a key which was released earliest is assigned, and the circuit 21outputs a truncate channel designating signal TR in accordance with this detection. In the assignment control section 19, control is effected so that the old assignment of a channel represented by the truncate channel designating signal TR is cancelledand that a key newly depressed is assigned to that channel.
A key-on signal generating circuit 22 for automatic chords (hereinafter referred to as "an automatic chord key-on signal generating circuit 22" when applicable) outputs a key-on signal KO.sub.3 in accordance with a signal CG representative of thetone production timing of an automatic chord. An automatic arpeggio circuit 23 detects successively the key codes N.sub.1 *-B.sub.3 * which have been stored in the key code memory circuit 17 and, for instance, concern the lower keyboard only, thereby tooutputs the key codes AN.sub.1 -AB.sub.2 of tones to be produced as automatic arpeggio tones. The key codes AN.sub.1 -AB.sub.2 of automatic arpeggio tones are inputted in an arpeggio-only-channel of the key code memory circuit under the control of theassignment control section 19.
The timing signal generating circuit 15 outputs a timing signal for controlling the tone production assignment of the tone production assignment circuit 13, and a timing signal for controlling the time division multiplex operation of variouspieces of information in the data multiplex circuit 14. The data multiplex circuit 14 multiplexes assigned key information (such as the key code N.sub.1 *-B.sub.3 *, and the key-on signals KO.sub.1, KO.sub.2 and KO.sub.3) applied thereto from the toneproduction assignment circuit 13 and control information from the key coder 11 (or other relevant switches) into time division multiplexed data in accordance with the timing signal applied thereto from the timing signal generating circuit 15. Keyinformation or control information of a large number of bits inputted into the data multiplex circuit 14 is multiplexed into data of a smaller number of bits (for instance, it is outputted as four-bit data KC.sub.1, KC.sub.2, KC.sub.3 and KC.sub.4). Themultiplex data KC.sub.1, KD.sub.2, KC.sub.3 and KC.sub.4 outputted by the data multiplex circuit 14 are delivered, as the output of the channel processor 12, to a digital tone generator section 16. In the digital tone generator section 16, variouspieces of information (such as the key codes N.sub.1 *-B.sub.3 *, the key-on signals KO.sub.1, KO.sub.2 and KO.sub.3, and the control information) are restored from the multiplex data KC.sub.1, KC.sub.2, KC.sub.3 and KC.sub.4 thus delivered, separatelyaccording to the tone production channels, and in accordance with these pieces of information musical tone signals are provided separately according to the channels. The digital tone generator section 16 comprises a tone generator of the type thatmusical tone signals having tone pitches corresponding to digital information can be produced in accordance with the digital information. In the example shown in FIG. 1, the key coder 11 and the channel processor 12 is in the form of one chip ofintegrated circuit, while the digital tone generator section 16 is in the form of another chip of integrated circuit.
Detailed description of the constructions and operations of various sections
(1) Explanation of a Method of Illustrating Various Circuit Elements in the Accompanying Drawings, and Timing Signals:
FIG. 2 shows one example of a method of illustrating various circuit elements in the accompanying drawings. In FIG. 2, the part (a) shows a multiple-input type AND circuit; the part (b), a multiple-input type OR circuit; the part (c), a delayflip-flop, and the part (d), a shift register. In a multiple-input type logical circuit element (the part (a) or (b) in FIG. 2), one input line is provided on the input side of the circuit, a plurality of signal lines are intersected with the inputline, and the point of intersection of a signal line for a signal to be inputted to the circuit and the input line is encircled. Accordingly, the logical expression of the part (a) of FIG. 2 is Q=A.multidot.B.multidot.D, while the logical expression ofthe part (b) of FIG. 2 is Q=A+B+C. The digit "1" in the block indicating a delay flip-flop, as shown in the part (c) of FIG. 2, is intended to mean that input data is delayed by one bit time (one stage). In the part (d) of FIG. 2, the numerator of afraction indicates the number of all stages in the shift register, while the denominator indicates the bit number of a stage. Where no clock pulse is indicated for a delay flip-flop or a shift register in a drawing, it should be understood that it isdriven by a main clock pulse .phi..sub.1 (which is, for instance, a two-phase clock pulse having a period of 1 .mu.s). Where an output is led out of a stage in a shift register, the stage's order is indicated by a number in the block, from which anoutput line is extended.
In the tone production assignment circuit 13, the tone production channels are formed in time division manner. The time-division time slots of the channels are segregated successively with the timing of the main clock pulse .phi..sub.1. In thisexample, the period of the main clock pulse .phi..sub.1 is one .mu.s. The part (a) of FIG. 3 shows the channel time slots (channel times) in the tone production assignment circuit 13, and sixteen time slots each having a time width of 1 .mu.s correspondthe first through sixteenth channels, respectively.
In this example, the tone production channels are determined separately according to the keyboards, and the tone production assignment circuit 13 operates to assign key depression tones of relevant keyboards to any of the tone production channelsthus determined. For instance, the upper keyboard tones are assigned to the third, fourth, sixth, seventh, tenth, thirteenth and sixteenth channels, while the lower keyboard tones are assigned to the second, fifth, eighth, ninth, eleventh, twelfth andfifteenth channels. The pedal keyboard tones are assigned to the first channel. The fourteenth channel is used for assigning the automatic arpeggio tones. Signals representative of the channels classified separately according to the keyboards and thefunctions as described above are outputted by the timing signal generating circuit 15.
(2) Description of the Timing Signal Generating Circuit 15:
Shown in FIG. 4 is a detailed example of the timing signal generating circuit 15. A counter 24 comprising four 1/2 frequency division flip-flops cascade-connected subjects the main clock pulse .phi..sub.1 to 1/16 frequency division. Thiscounter 24 is reset by an initial clear signal IC when the power switch is turned on, and thereafter it successively counts DC signals "1" applied to its count input terminal, with the timing of the main clock pulse .phi..sub.1 (not shown). When thecount value of the counter 24 reaches "1 1 1 1", an AND circuit 25 is operated to output a signal "1" having a time width of 1 .mu.s. Thus, the AND circuit 25 outputs the signal "1" every 16 .mu.s, and this output corresponds to the 16th channel time. The output of the AND circuit 25 is inputted into a 16-stage/1-bit shift register 26, where it is successively shifted according to the main clock pulse .phi..sub.1 (not shown). Accordingly, a single signal "1" is held in the shift register 26, and thissignal "1" is successively shifted toward the 16th stage from the first stage, as a result of which the channel time in time division manner as indicated in the part (a) of FIG. 3 is formed. The outputs of the 3rd, 4th, 6th, 7th, 10th and 13th stages inthe shift register 26 are applied to an OR circuit 27, the output of which is used as an upper-keyboard-only channel signal YUK. Similarly, the outputs of the 2nd, 5th, 8th, 9th, 11th, 12th and 15th stages in the shift register 26 are applied to an ORcircuit 28, the output of which is used as a lower-keyboard-only channel signal YLK. The output of the 1st stage in the shift register 26 is used as a pedal-keyboard-only channel signal YPK. In addition, the output of the 14th stage in the shiftregister 26 is used as an automatic-arpeggio-only signal YAR. The generation of these channels signals YUK, YLK, YPK and YAR are as indicated in the parts (b) through (e) of FIG. 3, respectively.
One cycle of processing operation in the channel processor 12 is accomplished in three circulations (48 .mu.s) of the time division channel time. A signal H1 indicated in the part (f) of FIG. 3 shows the first 16 .mu.s period (the firstprocessing period) of one operation cycle taking 48 .mu.s; a signal H2 indicated in the part (g) of FIG. 3 shows the second 16 .mu.s period (the second processing period); and a signal H3 in the part (h) shows the last 16 .mu.s period (the thirdprocessing period). A frequency division signal having a period of 16 .mu.s outputted by the counter 24 in FIG. 4 is inputted to a 1/3 frequency division circuit 29, from which a 2-bit output which is changed in three ways "0 0", "0 1" and "1 0" at thetime intervals of 16 .mu.s and repeats this change every 48 .mu.s is obtained. This output of the 1/3 frequency division circuit 29 is applied to a decoder 30, where the first, second and third processing period signals H1, H2 and H3 are obtained incorrespondence to the outputs "0 0", "0 1" and "1 0", respectively.
The timing signal generating circuit 15 generates twophase clock pulses .phi..sub.A, and .phi..sub.B each having a period of 48 .mu.s as indicated in the parts (i) and (j) of FIG. 3, in accordance with the processing period signals H1, H2 and H3and the contents of the shift register 26. The two-phase clock pulses .phi..sub.A and .phi..sub.B are used in the key coder 11 so as to deliver various data out of the latter 11 in synchronization with the period of 48 .mu.s of each of the first, secondand third processing period signals H1, H2 and H3.
(3) Description of the Key Coder 11
A key coder of the type that is disclosed by the specification of U.S. Pat. No. 4,114,495 may be preferably employed as the key coder 11. The key coder 11 operates to output key codes N.sub.1 -B.sub.3 representative of keys depressed in thekeyboard section 10. The key codes N.sub.1 -B.sub.3 are outputted in time division manner at predetermined time intervals when the keys are depressed. This time interval is controlled by the aforementioned clock pulses .phi..sub.A and .phi..sub.B so asto have a time width of 48 .mu.s in synchronization with the period of time from the rise of the pulse .phi..sub.A to the fall of the pulse .phi..sub.B. For example, if the key code N.sub.1 -B.sub.3 of a depressed key is applied to the channel processor12 from the key coder 11 with the time width of 48 .mu.s equal to the period of time from the rise of a clock pulse .phi..sub.A to a clock pulse .phi..sub.B, then the key code N.sub.1 -B.sub.3 of another depressed key is applied thereto in the period oftime of 48 .mu.s from the rise of the following clock pulse .phi..sub.A to the fall of the following clock .phi..sub.B. The time width for delivering one key code N.sub.1 -B.sub.3 from the key coder 11 is as indicated in the part (k) of FIG. 3.
The key code N.sub.1 -B.sub.3 is a 7-bit data consisting of a note code N.sub.1, N.sub.2, N.sub.3, N.sub.4 representative of a note and a block code B.sub.1, B.sub.2, B.sub.3 representative of an octave range. One example of the relationsbetween the contents of note codes N.sub.1 -N.sub.4 and notes is indicated in Table 1 below:
TABLE 1 ______________________________________ Note N.sub.4 N.sub.3 N.sub.2 N.sub.1 Decimal notation ______________________________________ C.music-sharp. 0 0 0 1 1 C 0 0 1 0 2 D.music-sharp. 0 0 1 1 3 E 0 1 0 1 5 F 0 1 1 0 6 F.music-sharp. 0 1 1 1 7 G 1 0 0 1 9 G.music-sharp. 1 0 1 0 10 A 1 0 1 1 11 A.music-sharp. 1 1 0 1 13 B 1 1 1 0 14 C 1 1 0 0 12 ______________________________________
In Table 1, the note code N.sub.4 -N.sub.1 of note C is "1 1 0 0" (decimal number 12); however, it is converted into "1 1 1 1" (decimal number 15) when it is practically used for musical tone production. The reason for this is that a referencedata used for restoring multiplexed data is provided by the data multiplex circuit 14 so that it has a content "1 1 1 1", and accordingly it is necessary to avoid the duplication with this.
The relation-ships between the contents of block codes B.sub.1 -B.sub.3 and octave ranges are indicated in Table 2 by way of example:
TABLE 2 ______________________________________ Octave Range Upper Lower Pedal B.sub.3 B.sub.2 B.sub.1 keyboard keyboard keyboard Arpeggio ______________________________________ 0 0 0 C.sub.3 C.sub.2 C.sub.1 0 0 1C.sub.3.sup..music-sharp. .about. C.sub.4 C.sub.2.sup..music-sharp. .about. C.sub.3 C.sub.1.sup..music-sharp. .about. C.sub.2 C.sub.2.sup..music-sharp. .about. C.sub.3 0 1 0 C.sub.4.sup..music-sharp. .about. C.sub.5 C.sub.3.sup..music-sharp..about. C.sub.4 C.sub.2.sup..music-sharp. .about. C.sub.3 C.sub.3.sup..music-sharp. .about. C.sub.4 0 1 1 C.sub.5.sup..music-sharp. .about. C.sub.6 C.sub.4.sup..music-sharp. .about. C.sub.5 C.sub.4.sup..music-sharp. .about. C.sub.5 1 0 0C.sub.6.sup..music-sharp. .about. C.sub.7 C.sub.5.sup..music-sharp. .about. C.sub.6 C.sub.5.sup..music-sharp. .about. C.sub.6 ______________________________________
As is clear from Table 2, the relationships between block codes B.sub.1 -B.sub.3 and octave ranges are different from one another separately according to the kinds of keyboard. For instance, the key range of the upper keyboard is from noteC.sub.3 to note C.sub.7, that is, notes lower in tone pitch than note C.sub.3 (exclusive) (notes lower than note B.sub.2 (inclusive)) and note higher in tone pitch than note C.sub.7 (exclusive) (note higher than note C.sub.7 .music-sharp. (inclusive))are not used, and even with the same block code B.sub.1 -B.sub.3 the octave range of the upper keyboard is different by one octave from that of the lower keyboard. In addition, the octave range to which one and the same block code B.sub.1 -B.sub.3 isnot an ordinary range of from note C to note B, but a range of from note C.music-sharp. to note C on the higher tone side. Accordingly, the block code B.sub.1 -B.sub.3 "0 0 0" in the lowest range is applied only to one tone C which is the lowest. Indicated in the column "Arpeggio" in Table 2 are tone range corresponding to the contents of the block code AB.sub.1, AB.sub.2 included in a key code AN.sub.1 -AB.sub.2 for automatic arpeggio tone which is provided by the automatic arpeggio circuit 23(FIG. 1). The tone ranges are substantially equal to those for the block codes B.sub.1 -B.sub.3 for the lower keyboard; however, it should be noted that note C.sub.2 in the lowest tone range is not used in the automatic arpeggio. Accordingly, withrespect to the block code AB.sub.1, AB.sub.2 for arpeggio, a bit corresponding the third bit B.sub.3 is not required. The key range of the pedal keyboard is from note C.sub.1 to note C.sub.3, and therefore in this case also the data of the third bitB.sub.3 is unnecessary.
Keyboard signals U, L, and P representative of keyboards to which keys represented by key codes N.sub.1 -B.sub.3 belong are outputted by the key coder 11 in synchronization with the key codes N.sub.1 -B.sub.3 and with a time width of 48 .mu.s. The signals U, L and P represent the upper keyboard, the lower keyboard and the pedal keyboard, respectively.
A depressed key's key code N.sub.1 -B.sub.3 and its keyboard signal U, L or P are provided by the key coder 11 repeatedly at suitable time intervals. Upon release of the key, provision of the key code N.sub.1 -B.sub.3 is suspended. In order todetect what key code concerns the released key among the key codes which have been provided, the key coder 11 periodically generates a key-off detecting signal X. The generation timing of the key-off detecting signal X is 48 .mu.s equal to one key codedelivery time indicated in the part (k) of FIG. 3. While this key-off detecting signal X is being produced, none of the key code N.sub.1 -B.sub.3 and the keyboard signals U, L and P are produced. The generation interval of the key-off detecting signalX is of the order of 5 ms for instance. It is a relatively long period of time for a digital system, but it is so short for a person's hearing sense that he cannot distinguish two successively produced key-off detecting signals X. The assignment controlsection 19 in the tone production assignment circuit section 13, under the conditions that no key code N.sub.1 -B.sub.3 is supplied to the channel processor 12 during one generation interval of key-off detecting signal X although it has been supplied tothe channel processor 12, determines that the key concerning the key code N.sub.1 -B.sub.3 has been released.
In this example, the key coder 11 is so designed that it delivers not only information (N.sub.1 -B.sub.3, U, L, P and X) concerning keys as was described above but also data selected by switches employed for musical tone control or functionselection. When automatic arpeggio performance is selected, the key coder 11 outputs an automatic arpeggio selection signal ARP with a time width of 48 .mu.s synchronous with one key code delivery time shown in the part (k) of FIG. 3. Furthermore, thekey coder 11 is so designed that when the automatic arpeggio selection signal ARP is outputted, pieces of information (N.sub.1 -B.sub.3, U, L P and X) concerning keys are not outputted thereby. The key coder 11 outputs an envelope control signal EC. This signal EC is to change a produced tone's amplitude envelope waveform over to either a sustain tone system envelope waveform or an attack system envelope waveform, and has a DC "1" level or a DC "0" level according to the set positions of an envelopecontrol switch .[.(not shown).]. .Iadd.S.sub.EC (FIG. 1).Iaddend.. A damper signal DU outputted by the key coder is to abruptly eliminate a musical tone envelope waveform which remains as a decayed waveform even after key release, and has a DC "1" levelor a DC "0" level according to the on-off operation of a damper switch .[.(not shown).]. .Iadd.S.sub.DU (FIG. 1). Thus the key coder 11 includes means for generating envelope information (e.g., the signals EC and DU) to determine the envelopecharacteristics of a tone.Iaddend..
Furthermore, the key coder 11 is so designed that process for automatic bass chord performance can be effected. That is, in the case where a automatic bass chord performance is selected, an automatic bass's key code N.sub.1 -B.sub.3 and anautomatic chord's key code N.sub.1 -B.sub.3 are provided with suitable timing in accordance with keys depressed in the keyboard section 10. In an automatic bass chord performance, an automatic bass chord selection signal ABC is outputted, in a directcurrent mode, by the key coder 11. A slow rock selection signal SR has a DC "1" level when a slow rock rhythm is selected. A chord timing signal CG is outputted by the key coder 11 with the timing of producing an automatic chord. These signals ABC, SRand CG are applied through the channel processor 12 to the digital tone generator, where they are used to control an automatic chord's amplitude envelope waveform.
In the "automatic bass chord performance", in general, keys in the keyboard section are depressed in chord form, a chord name is detected from the combination of the keys thus depressed, tones corresponding to the root (fundamental note) andsub-notes of the chord are automatically produced as bass tones in accordance with a bass pattern, and chord forming tones are produced automatically with chord tone producing timing. A bass automatically formed in supplied, as a pedal keyboard keycode, to the channel processor 12, while a chord is supplied, as a lower keyboard key code, to the channel processor 12. In the electronic musical instrument relating to this embodiment a device disclosed in the specification entitled as "MusicalInstrument with Automatic Bass Chord performance Device" of U.S. patent application Ser. No. 825,443 filed Aug. 17, 1977 and assigned to the same assignee as the present case, can be employed for automatic bass chord performance. Such an "automaticbass chord performance control device" is provided on the output side of the key coder 11, that is, it is provided between the key coder 11 and the channel processor 12. However, it should be noted that the "automatic bass chord performance controldevice" is included in the key coder 11 in FIG. 1. In fact, it is possible that by following the teaching of the U.S. patent application Ser. No. 825,443 an automatic bass chord performance function can be incorporated in the key coder 11 to commonlyuse the circuits. Accordingly, this embodiment may employ an arrangement in which an automatic bass chord performance function is positively incorporated in the key coder 11, or it may employ an arrangement in which an original key coder part and anautomatic bass chord performance control part are segregated from each other in the key coder 11 which is illustrated as one block for convenience in description. The detailed description of the automatic bass chord performance control will be omitted.
In addition, the key coder 11 outputs a memory signal MM representative of the fact that information representative of a key depressed should be stored even after the release of the key so as to be used for musical tone production, an up/turnselection signal UT for selecting an automatic arpeggio tone's tone pitch increment pattern or increment and decrement repetition pattern, and arpeggio pattern selection signals AP.sub.1, AP.sub.2, AP.sub.3 and AP.sub.4 when required; however, theirdetailed descriptions will be omitted.
(4) Description of the Tone Production Assigning Circuit Section 13:
One example of the tone production assignment circuit 13 will be described in detail. Referring to FIG. 5, the key code memory circuit 17 comprises a 16-stage/1-bit shift register 31, a data inputting AND circuit 32, a self-holding AND circuit33 and an OR circuit 34 for supplying input data to the first stage of the shift register 31 for each bit of the key code N.sub.1 -B.sub.3. Each shift register 31 carries out its shifting operation every 1 .mu.s in accordance with the main clock pulse.phi..sub.1. The number of stages in the shift register 31 corresponds to the number of tone production channels. The key codes N.sub.1 *-B.sub.3 * of tones assigned to the respective channels are stored in time division manner in the stages of theshift registers 31. These key codes N.sub.1 *-B.sub.3 * are successively outputted by the key code memory circuit 17 in synchronization with the respective channel times, each having 1 .mu.s as indicated in the part (a) of FIG. 3, and are applied to theone input side of a digital comparator 35 in a key code comparison circuit 18, to the other input side of which the key code N.sub.1 -B.sub.3 having a time width of 48 .mu.s delivered from the key coder 11 is applied through a group of OR circuits 36.
In the digital comparator 35, the key code N.sub.1 -B.sub.3 of a depressed key which is not changed for 48 .mu.s is compared with the key code N.sub.1 *-B.sub.3 which is changed every 1 .mu.s and has been assigned already. In the case where thesame key code N.sub.1 -B.sub.3 as the key code N.sub.1 -B.sub.3 has been stored in the memory circuit 17, the coincidence detection signal EQ.sub.1 is raised to a logical level "1" (hereinafter referred to as "1" when applicable) in synchronization withthe channel time thereof. In the digital comparator 35, the comparison is carried out independently of the keyboard of the key code N.sub.1 -B.sub.3, and the coincidence detection signal EQ.sub.1 is produced. The coincidence detection signal EQ.sub.1is applied to AND circuit 37, 38 and 39, whereby only the coincidence detection signal EQ.sub.1 which is provided in the channel time of the same keyboard as a keyboard to which a key code N.sub.1 -B.sub.3 supplied from the key coder 11 belongs isselected. For this purpose, the upper keyboard signal U or the lower keyboard signal L or the pedal keyboard signal P delivered from the key coder 11 in synchronization with a key code N.sub.1 -B.sub.3 is applied to the AND circuit 37 or 38 or 39,respectively. A key code N.sub.1 *-B.sub.3 is assigned to the special channel for the respective keyboard, and therefore the signals YUK, YLK and YPK representative of the special channels of the keyboards, as indicated in the parts (b), (c) and (d) ofFIG. 3 are applied to the AND circuits 37, 38 and 39. The outputs of the AND circuits 37, 38 and 39 are applied to an OR circuit 40, the output of which is applied, as a comparison output EQ, through an AND circuit 41 and a line 42 to AND circuits 43and 44 in the assignment control section 19 (FIG. 6). The AND circuit 41 is to suspend the application of the comparison output EQ to the assignment control circuit 19 while the automatic arpeggio selection signal ARP is supplied thereto. In this case,the signal ARP is applied through an inverter 45 to the AND circuit 41 to disable the latter 41. As was described before, while the automatic arpeggio selection signal ARP is being provided, none of the keyboard signals U, L and P are provided. Therefore, the output of the OR circuit may be introduced to the line 42 without providing the AND circuit 41. For the period of 48 .mu.s during which the automatic arpeggio selection signal ARP is outputted, the key code AN.sub.1 -AB.sub.2 of anautomatic arpeggio tone is applied to the OR circuits 36 by the automatic arpeggio circuit 23 (FIG. 1) and is stored in the key code memory circuit 17 with the timing corresponding to the fourteenth channel which is the arpeggio special channel. Thenote code N.sub.1 *-N.sub.4 * of the output of the key code memory circuit 17 is supplied to the automatic arpeggio circuit 23 (FIG. 1).
Referring to FIG. 6, the assignment control section 19 comprises a key-on memory 46, a lower keyboard key-on memory 47, a key-on temporary memory, a key-off memory 49, and a circuit for controlling the data inputting operations and storagecancelling operations of these memories. Each of the memories 46 through 49 has a 16-stage/1-bit shift register so as to store the data of the channels in time division manner. When a key concerning a key code N.sub.1 *-B.sub.3 * which has beenassigned and stored in the key code memory circuit 17 is being depressed, a signal "1" (key-on signal KO) is stored by the key-on memory 46 in synchronization with the relevant assigned channel. Accordingly, this indicates that tone assignment hasalready been done to the channel for which the output of the key-on memory is at "1", and the key of the tone is being depressed. .Iadd.Thus the key code memory circuit 17 and the key-on memory 46 together comprise a memory means or assignment memorymeans storing for each assigned channel both a key code and the associated key depression state data. .Iaddend.The aforementioned comparison output EQ, the output KO of the key-on memory 46 and a key code detecting signal KON from an OR circuit 50 (FIG.5) are applied to the AND circuit 43. A note code N.sub.1 -N.sub.4 supplied by the key coder 11 (or the note code AN.sub.1 -AN.sub.4 of an automatic arpeggio) is inputted to the 4-input OR circuit 50. Accordingly, when any key code N.sub.1 -B.sub.3 issupplied to the key code memory circuit 17, the key code detection signal KON is raised to "1".
Accordingly, the AND circuit 43 outputs a signal "1", when the following three conditions are satisfied:
(1) At present, a key code N.sub.1 -B.sub.3 (or AN.sub.1 -AB.sub.2) is supplied (KON="1").
(2) The key code N.sub.1 -B.sub.3 has already been assigned to a channel. (EQ="1").
(3) The tone assigned to the channel is of a key being depressed, (the output of the key-on memory 46 being at "1"). This output "1" of the AND circuit 43 will be referred to as "an assigned key-on signal AKON" when applicable. The signal AKONis applied through an OR circuit 51 and an AND circuit 52 to a delay flip-flop 53, where it is stored. This storage is self-maintained through the OR circuit 51 and the AND circuit 52. A signal Y48 applied to the other input terminal of the is obtainedby inverting a one cycle finish signal Y48 (the part (1) of FIG. 3). More specifically, the one cycle finish signal Y48 is provided by an AND circuit 54 in the timing signal generating circuit 15 (FIG. 4). The third process period signal H3 from thedecoder 30 (the part (h) of FIG. 3) and a pulse synchronous with the 16th channel time from the AND circuit 25 are applied to the AND circuit 54, and the one cycle finish signal Y48 is provided in the last channel time of the process operation cycle asindicated in the part (1) of FIG. 3. Since the signal Y48 is obtained by inverting the output of the AND circuit 54 by means of an inverter 55, it is maintained at "1" for the period of 47 bit-times covering the first and second process periods (H1 andH2) plus the period from the beginning of the third process period (H3) to the 15th bit-time thereof (cf. the part (m) of FIG. 3). The AND circuit 52 (FIG. 6) enabled by the signal Y48 is disabled with the generation timing of the one cycle finishsignal Y48. Therefore, the self-holding of the delay flip-flop 53 is cleared at the last channel time of the third process period (H3).
In the case where a key code N.sub.1 -B.sub.3 supplied by the key coder 11 is one which has been assigned already, an assigned key-on signal AKON is provided in a relevant assigned channel time of the 16 bit-times during which the first processperiod signal H1 is outputted. Since this signal AKON is immediately stored in the delay flip-flop 53, the output of the delay flip-flop 53 is maintained at "1" for the period of 16 bit-time during which the second process period signal H2 is ouputted. This output "1" of the delay flip-flop 53 is applied to an inverter 56, where it's level is switched to a logical "0" level (hereinafter referred to merely as "0" when applicable), as a result of which no new assignment in the second process period (H2)is effected.
In contrast, in the case where a key code N.sub.1 -B.sub.3 supplied by the key coder 11 has not been assigned yet (or in the case where an automatic arpeggio key code (AN.sub.1 -AB.sub.2 is supplied), the output of the AND circuit 43 is always at"0" while the first and second process period signals H1 and H2 are outputted. Accordingly, no signal "1" is stored in the delay flip-flop 53, and the output of the flip-flop 53 is maintained at "0". In this case, while the second process period signalH2 is provided, the output of the inverter 56 is at "1" without fail. This output "1" of the inverter 56 is applied through an OR circuit 57 to an AND circuit 58, as a result of which a new key-on signal NKO is provided which indicates the fact that akey is newly depressed. A key code detection signal KON is applied to the AND circuit 58 by the OR circuit 50 in FIG. 5. When the output of the inverter 56 is at "1" and this key code detection signal KON is at "1" also, it means that a new key codeN.sub.1 -B.sub.3 which is not assigned yet is supplied. Such a new key code N.sub.1 -B.sub.3 should be assigned to any of the channels. For this purpose, the output of the key-on memory 46 is applied through an inverter 57 to the AND circuit 58,thereby to enable the AND circuit 58 in a channel time during which key release is effected, and to provide the new key-on signal NKO in that channel time.
The new key-on signal NKO outputted by the AND circuit 58 is applied to AND circuits 60, 61, 62 and 63, and it is selected by one of the AND circuits 60 through 63 in synchronization with a single channel time. The new key-on signal NKO thusselected is applied through OR circuits 64 and 65 to the key-on memory 46, where it is stored. The output "1" of the OR circuit 64 becomes a load signal LD. The upper keyboard signal U, the lower keyboard signal L, the pedal keyboard signal P and theautomatic arpeggio selection signal ARP are applied to the AND circuits 60 through 63 by the key coder 11, respectively, as a result of which one of the AND circuits 60 through 73, which corresponds to the keyboards (or function) to which the key codeN.sub.1 -B.sub.3 being supplied belongs, is enabled. Signals YUK2, YLK2, YPK2 and YAR2 representative of the keyboards and automatic arpeggio exclusive assignment channels are applied to the AND circuits 60 through 63, respectively. These signals YUK2,YLK2, YPK2 and YAR2 are the exclusive channel signals YUK, YLK, YPK and YAR (the parts (b) through (e) of FIG. 3) which occur during the second process period indicated in the part (g) of FIG. 3, and these signals are provided by AND circuits 66 through69 in FIG. 4. The second process period signal H2 is applied to one input terminal of each of the AND circuits 66 through 69 by the decoder 30, while the upper keyboard exclusive channel signal YUK, the lower keyboard exclusive channel signal YLK, thepedal keyboard exclusive channel signal YPK and the automatic arpeggio exclusive channel signal YAR are applied to the remaining input terminals of the AND circuits 66 through 69 by the OR circuits 27, 28, 70 and 71, respectively. Thus, the signalsYUK2, YLK2, YPK2 and YAR2 are provided in the exclusive channel times of the second process period, respectively.
Each of the exclusive channels of the pedal keyboard tone and the automatic arpeggio tone is one channel. Therefore, if the new key-on signal NKO is provided while the pedal keyboard signal P or the automatic arpeggio selection signal is beingsupplied, the AND circuit 62 or 63 outputs a signal "1" in the first or fourteenth channel time of the second process period in response to the signal YPK2 or YAR2. Each of the upper keyboard tone and the lower keyboard tone has seven channels as itsexclusive channel. Therefore, in order to assign the new key-on signal NKO to a single channel, a truncate channel designation signal TR is employed. The signal TR is outputted by the truncate circuit 21 (FIG. 7) as described later. The truncatechannel designation signal TR is provided in synchronization with the assignment channel time of the key which has been released earliest in the upper keyboard and the assignment channel time of the key which has been released earliest in the lowerkeyboard, with respect to the tones being subjected to assignment. The signal TR thus provided is applied to AND circuits 72 and 73, where it is divided into an upper keyboard truncate channel designation signal TRU and a lower keyboard truncate channeldesignation signal TRL separately according to the upper keyboard exclusive channel signal YUK and the lower keyboard exclusive channel signal YLK. The signals TRU and TRL are applied to the AND circuits 60 and 61, respectively, whereby the new key-onsignal NKO is selected in a single channel time of a relevant keyboard. When a signal "1" is outputted by the AND circuit 60 or 61 once, the signal "1" is applied through an OR circuit 74 or 75 and an AND circuit 76 or 76 to a delay flip-flop 78 or 79,where it is stored. This storage is self-held by the signal Y48 applied to the AND circuit 76 or 76 until the one cycle finish signal Y48 is provided. The output "1" of the delay flip-flop 78 or 79 is applied through an inverter to the AND circuit 72or 73 to disable the latter. Accordingly, even if the truncate channel designation signal TR is provided twice or more in different channels relating to one and the same keyboard, the truncate channel designation signal TRU or TRL of the upper keyboardor the lower keyboard is generated only once in the second process period (the part (g) of FIG. 3).
When any of the AND circuits 60 through 63 provides the output "1", a new assignment is carried out. More specifically, The signal "1" outputted by any of the AND circuits 60 through 63 in a single channel time of the second process period isapplied, as a load signal LD, through an OR circuit 64 to the key code memory circuit 17 (FIG. 5). Referring to FIG. 5, the load signal LD enables data inputting AND circuits 32 provided respectively for the bits in the key code memory circuit 17. Theload signal LD is further applied through a NOR circuit 80 to self-holding AND circuits 33 to disable the latter. Therefore, the stored key code N.sub.1 *-B.sub.3 * of a channel for which the load signal LD is provided is cleared, and a new key codeN.sub.1 -B.sub.3 (or AN.sub.1 -AB.sub.2) is stored in the key code memory circuit 17 in synchronization with the relevant channel time.
Referring back to FIG. 6, the output "1" of the OR circuit 64 is applied through an OR circuit 65 to the key-on memory 46, whereby the key-on signal KO is stored in synchronization with the storage of the new key code N.sub.1 -B.sub.3 in the keycode memory circuit 17. The output KO of the key-on memory 46 is self-held by means of the OR circuit 65 and an AND circuit 81. The AND circuit 81 is disabled in the time of the channel to which a key code N.sub.1 *-B.sub.3 * relating to key releasehas been assigned, as described later.
The output of the OR circuit 65 is applied through a line 82 to an AND circuit 83. Accordingly, when a signal "1" representative of a key being depressed is inputted to the key-on memory 46, the AND circuit 83 is disabled. Applied to the otherinput terminal of the AND circuit 83 is a lower keyboard new key-on signal LNK representing the fact that a key is newly depressed in the lower keyboard. The aforementioned output of the OR circuit 57 and the key code detection signal KON are applied toan AND circuit 84, and the lower keyboard signal L and the lower keyboard exclusive channel signal YLK 2 in the second process period are applied to the remaining input terminals of the AND circuit 84. Accordingly, if a key is depressed in the lowerkeyboard, at the beginning of the depression the output LNK of the AND circuit 84 is raised to "1" only once in synchronization with the lower keyboard exclusive channel time of the second process period. In this operation, the OR circuit 65 outputs asignal "1" in synchronization with the assignment channel of the tone of a key being depressed in the lower keyboard. Therefore, the output of the AND circuit 83 is raised to "1" in synchronization with the assignment channel of the tone of the keybeing depressed in the lower keyboard. This output "1" is applied through an OR circuit 85 to the lower keyboard key-on memory 47 where it is stored. This storage in the memory 47 is self-held by means of the AND circuit 86 and the OR circuit 85. Theoutput of the NOR circuit 87 is applied to the AND circuit 86. The AND circuit is disabled when the initial clear signal Ic is provided, in channel times other than the lower keyboard exclusive channel (the signal YLK being at "1") or when the ANDcircuit 84 provides the lower keyboard new key-on signal LNK. Applied through a line 166 to the other input terminal of the AND circuit 86 is a lower keyboard key depression memory signal LKM whose level is maintained raised to "1" when a key isdepressed in the lower keyboard. Therefore, when a key is depressed in the lower keyboard, the self-holding of the lower keyboard key-on memory 47 is permitted. A lower keyboard key-on signal LKO is outputted by the lower keyboard key-on memory 47 intime division manner in synchronization with the channel time to which the tone of a key being depressed in the lower keyboard is assigned. This signal LKO is utilized in the automatic arpeggio circuit 23 (FIG. 1); however, its detailed description willbe omitted.
(KEY-OFF DETECTION)
The load signal LD representing a channel to which a newly depressed key is to be assigned is applied from the OR circuit 64 through a line 88 (FIG. 6) to an OR circuit 89, and it is stored in the key-on temporary memory 48. The key-on temporarymemory 48 operates in such a manner that, if a key is depressed even once in one generation period of the key-off inspection signal X, the memory 48 stores a signal "1" in the assignment channel of the key. This storage is self-held by means of an ANDcircuit 90. Upon application of the key-off inspection signal X by the key coder 11, the AND circuit 90 is disabled. Accordingly, whenever the key-off inspection signal X is supplied, the storage in the key-on temporary memory 48 is cleared. Thekey-off inspection signal X is applied to an AND circuit in FIG. 6, and it is selected only for the first process period (the part (f) of FIG. 3) with the aid of the signal H1. A key-off inspection signal X1 selected in synchronization with the firstprocess period is applied through an inverter 91 to the AND circuit 91, as a result of which the AND circuit 90 is disabled only for the first process period. During this period, the contents stored in all the channels in the key-on temporary memory 48are cleared.
In the case where a key code N.sub.1 -B.sub.3 (or AN.sub.1 -AB.sub.2) based on the depression of a new key which is not subjected to assignment is supplied, the aforementioned load signal LD is applied through the line 88 and the OR circuit 89 tothe key-on temporary memory 48, and a signal "1" is stored in the memory 48 in synchronization with the channel time to which the relevant key code N.sub.1 -B.sub.3 (or AN.sub.1 -AB.sub.2) has been assigned. If, in the case where an already assigned keyis depressed, the key code N.sub.1 -B.sub.3 of that key is supplied, an assigned key-on signal AKON is provided by an AND circuit (FIG. 6) in synchronization with that assignment channel and it is applied through a line 92 to an AND circuit 93. A secondprocess period synchronization signal YH2 is applied to the other input terminal of the AND circuit 93. Therefore, the assigned key-on signal AKON passes through the AND circuit 93 only for the second process period, and it is applied through an ORcircuit 89 to the key-on temporary memory 48, where it is stored. Accordingly, the storage in the key-on temporary memory 48 is cleared by the key-off inspection signal X once; however, as long as the key is depressed, a signal "1" is stored in thatkey's assignment channel before the next key-off inspection signal X is supplied. The second process period synchronization signal YH2 mentioned above is supplied by an AND circuit 108 in FIG. 4., and it is produced in accordance with the AND logic ofthe output of an OR circuit (FIG. 4) receiving the outputs of the sixteen stages in the shift register (FIG. 4) and the second process period H2 of the decoder 30 (FIG. 4). Accordingly, the signal YH2 is correctly in synchronization with the firstthrough sixteenth channel times in the second process period.
The key-off inspection signal X generation period is of the order of 5 ms. If the key code N.sub.1 -B.sub.3 of the key which was depressed is not supplied by the key coder 11 during one generation period of the signal X at all, it is determinedthat the key has been released. This determination is carried out by an AND circuit 95. That is, it can be determined as follows: Key depression is being effected for the channel for which a signal "1" is stored in the key-on temporary memory 48immmediately before the key-off inspection signal X is supplied, and key release has been effected for the channel for which a signal "0" is stored therein. Thus, the output of the key-on temporary memory 48 is applied through an inverter 94 to the ANDcircuit 95, thereby to disable the latter 95 during the channel time for which the key release is effected. A key-off inspection signal X1 having a 16-bit time width in synchronization with the first process period is applied to the AND circuit 95 froman AND circuit 107. Furthermore, the key-on signal KO outputted by the key-on memory 46 is also applied to the AND circuit 95 in order to detect whether or not a key has been depressed in the channel for which the memory content is "0" in the key-ontemporary memory 48. Therefore, only when the key which has been depressed is released, that is, key release is effected, the AND condition of the AND circuit 95 is satisfied in the assignment channel time of that key. The output "1" of this ANDcircuit 95 is a key-off signal KOF.
The key-off signal KOF is applied through an AND circuit 96 an OR circuit 97 to an inverter 98, thereby to disable the self-holding AND circuit 81 of the key-on memory 46. As a result, the key-on signal KO stored in the key-on memory 46 iscleared in correspondence to the channel for which the key-off signal KOF is provided. Accordingly, the key-on signal KO is stored in the key-on memory 46 only for the period during which a key is being depressed. Since the key code memory circuit 17is not cleared by the key-off signal KOF, the relevant channel assignment is maintained even after the key release, and the key code N.sub.1 *-B.sub.3 * concerning the key released is remains stored.
The key-off signal KOF is applied through an OR circuit 99 to the key-off memory 49. This key off memory 99 operates to stored a signal "1" in synchronization with the assignment channel time of a key which has been released among keys which arebeing assigned to the channels. A key-off memory signal KOFM outputted by the last state therein is self-held by means of an AND circuit 100 and the OR circuit 99. Applied to the other input terminal of the AND circuit 100 is the output of the ORcircuit 64 which are delivered through the line 88 and inverter 101. Therefore, if the load signal LD is provided during a channel time and a new assignment is effect, the storeage in that channel of the key-off memory 49 is cleared. The key-off memorysignal KOFM is applied through an inverter 102 to one input terminal of an AND circuit 103, to the other input terminal of which the key-off signal KOF is applied. When the key-off signal KOF is provided in a channel for the first time, the storage inthat channel of the key-off memory 49 is "0" . The output of the inverter 102 to which the signal KOFM is applied is "1" and therefore the output of the AND circuit 103 has "1". This output "1" of the AND circuit 103 is utilized in the circuit shown inFIG. 7 as a new key-off signal NKF representative of the fact that key release has effected The new key-off signal NKF is produced only once in the channel time to which the relevant key has been assigned, at the beginning of the key release.
The AND circuit, to which the key-off signal KOF is applied, is normally enabled; however, when "a memory function" is effected, it is enabled during the lower keyboard exclusive channel time. Upon operation of a switch (not shown) forperforming the memory function, a memory signal MM is provided by the key coder 11 and it is applied to one input terminal of an AND circuit 104, to the other input terminal of which the lower keyboard exclusive channel signal YLK is applied. The outputof the AND circuit 104 is applied through an inverter 105 to the AND circuit 96. Accordingly, where the "memory function" is performed, the AND circuit 96 is disabled during the lower keyboard exclusive channel times (cf. the part (c) of FIG. 3). Evenif the key-off signal KOF is produced in these channel times, the self-holding AND circuit 81 of the key-on memory 46 is not disabled. Accordingly, in practice, even if a key is released in the lower keyboard, the key-on signal of the key-on memory 46is not cleared, and it is handled as if the key in the lower keyboard were continuously depressed. Thus, the tone concerning the key is produced even after it is released. The above-described "memory function" is advantageous in improving the automaticperformance effect. Furthermore, since the embodiment is so designed that the lower keyboard exclusive channel can be used for automatic chords, automatic chords can be produced even after key release.
The output of the AND circuit 104 is applied also to an AND circuit 106. The key-on signal KO of the key-on memory 46 which has been held even after the key release thanks of the "memory function" is cleared in correlation to the output "1" ofthe AND circuit 106. A signal obtained by inverting the output of the key-on temporary memory with an inverter 94 and the output of the AND circuit 84 are applied to the remaining input terminal of the AND circuit 106. The output of the inverter 94 israised to "1" in a channel for which key release is effected. If this channel is the lower keyboard exclusive channel, then the output of the AND circuit 104 is also raised to "1". Therefore, the AND circuit 106 is disabled in the relevant channeltime. If, in this case, the AND circuit 84 produces the lower key-board new key-on signal LNK, the output of the AND circuit 106 is raised to "1". The output "1" of the AND circuit 106 is applied through the OR circuit 97 and the inverter 98 to the ANDcircuit 81 to disable the latter 81, as a result of which the storage of the relevant channel of the key-on memory 46 is cleared. Accordingly, the key-on signal KO held even after key release on account of the "memory function" is cleared when a key isnewly depressed in the lower keyboard (or when the lower keyboard new key-on signal LNK is provided).
(KEY-ON AGAIN)
In the case where, immediately after a key is released, and the same key is depressed again, a key-on again signal KAG is outputted from the AND circuit 44, and the assignment of the key is effected to a channel different from the channel towhich the key was assigned. The comparison output EQ from the key code comparison circuit 18 is applied through the line 42 to the AND circuit 44, and furthermore the key code detection signal KON representative of the supply of a key code N.sub.1-B.sub.3 (or AN.sub.1 -AB.sub.2) and the output signal of the key-off memory 49 are applied to the AND circuit 44. Accordingly, under the conditions that the key code N.sub.1 -B.sub.3 (or AN.sub.1 -AB.sub.2) being supplied now is equal (in keyboardalso) to a key code N.sub.1 *-B.sub.3 * assigned to a channel, and the storage of the key-off memory 49 in the channel to which that key code N.sub.1 *-K.sub.3 * has been assigned is "1" which has provided coincidence is released), a signal "1" isoutputted by the AND circuit 44. This output "1" of the AND circuit 44 is applied, as the key-on again signal KAG representative of the fact that a key released is depressed again immediately, to the OR circuit 110, and it is further applied through asAND circuit 111 to a delay flip-flop 113 where it is stored. The output of the delay flip-flop 112 is applied to the OR circuit 57, and it is utilized for generating the new key-on signal KON.
(KEY-ON SIGNALS KO.sub.1 and KO.sub.2 Generation
The key-on signal KO of each channel outputted in time division manner from the last, or 16th, stage of the key-on memory 46 is applied to AND circuits 113 and 114, which in turn output the first key-on signal KO.sub.1 and the second key-onsignal KO.sub.2, respectively, in response to the key-on signal KO. The first key-on signal KO.sub.1 is a signal whose level is switched to "1" and "0" respectively according to the depression and release of a key assigned to the channel, and it is thesame signal as the key-on signal KO in a normal keyboard performance. A signal from the attack system key-on signal generating circuit 20 is applied through a line 115 to the other input terminal of the AND circuit 113. The signal on the line 115 is at"1" When an ordinary performance operation is carried out by using the upper keyboard, the lower keyboard or the pedal keyboard. Therefore, the AND circuit 113 is maintained enabled at all times, and the key-on signal KO is outputted as the first key-onsignal KO.sub.1. Accordingly, in this case, the first key-on signal KO.sub.1 is generated exactly in accordance with the depression of the key (tone) assigned to the relevant channel. The output signal of a NAND circuit 116 of the attack system key-onsignal generating circuit 20 is supplied to the line 115. The automatic bass chord selection signal ABC is applied to one input terminal of the NAND circuit 116. In the case where an automatic bass chord performance is not selected, that is, in thecase of an ordinary keyboard performance, the signal ABC is at "0", and the NAND circuit 116 is disabled. Therefore, the signal on the line 115 is at "1" at all times.
Where an automatic bass chord performance is selected, the first key-on signal KO.sub.1 of a pedal keyboard tone is converted into a differential signal which is raised to "1" for a certain period in the beginning of the key depression. Since anautomatic chord is produced in the pedal keyboard's channel in case of an automatic bass chord performance, in practice the first key-on signal KO.sub.1 for an automatic bass becomes the differential signal. This can be achieved by applying the pedalkeyboard exclusive channel signal YPK to the NAND circuit 116. Thus, only when the automatic bass chord selection signal ABC is supplied by the key coder 11 and only in the pedal keyboard's exclusive channel time (the first channel time), the NANDcircuit 116 is enabled. Three-bit count data from a counter made up of an adder 117 comprising a 3-bit half adder and 16-stage/3-bit shift registers 118 are applied to the remaining three input terminals of the NAND circuit 116. This counter is sodesigned as to carry out integration count by feeding data, which is delayed by 16 channel times in the 16-stage shift registers 118, back to the adder 117, and to carry out counting operations for the channels in time division manner. A count pulse Tis applied through an AND circuit 119 to the counter 117. The counter pulse T is provided by the timing signal generating circuit 15 shown in FIG. 4.
Referring to FIG. 4, the one cycle finish signal Y48 outputted by the AND circuit 54 is applied to the count input terminal of a frequency-dividing counter 120. When all of the five bits of the output of the counter 120 are raised to "1", an ANDcircuit 121 is operated, as a result of which a count pulse T having a time width of 48 .mu.s is provided by means of an AND circuit 122 and an OR circuit 123. This count pulse T is obtained by subjecting the signal Y48 having a period of 48 .mu.s to1/32 frequency division, and therefore it has a period of about 1500 .mu.s (48.times.32). A test signal TEST applied to the OR circuit is raised to "1" in a direct current mode only when the circuit operation is checked, and accordingly is not relatedto the original circuit operation.
In the AND circuit in FIG. 6, the aforementioned count pulse T is selected only for the second process period, or 16 .mu.s, with the aid of the second process period synchronization signal YH2. Accordingly, when one count pulse T is produced,one count pulse is supplied at each channel time. A group of AND circuits 124 interposed between the adder 117 and the shift registers 118 are enabled by the key-on signal from the key-on memory 46. Accordingly, where no key has been depressed in arelevant channel, the content of the relevant channel of the shift register 118 has been cleared, and counting the count pulses is effected at the time of depressing a key. When seven count pulses T are supplied after depression of a key assigned to achannel is started, the 3-bit output of the shift register 118 has "1 1 1" ("7" in decimal notation) in that channel time. If the channel time is for the pedal keyboard exclusive channel, the signal YPK is raised also to "1". If in this case the signalABC is at "1", the NAND condition of the NAND circuit 116 is satisfied, and its output is switched to "0". When the output of the NAND circuit 116 is changed to "0", the output of the AND circuit 125 is lowered to "0", as a result of which, the ANDcircuit 119 is disabled. Accordingly, the count pulse T is blocked at the relevant channel time, and the memory content "1 1 1" of the shift register for the relevant channel is maintained unchanged.
The time interval which elapses from the time instant that depression of a key is started until the output of the NAND circuit 116 has "0" is about 10 ms (1.5 ms.times.7). For about 10 ms in the beginning of key depression, the output of theNAND circuit 116 in a channel time to which the key has been assigned is "1", and the AND circuit 113 is enabled. Accordingly, the key-on signal KO outputted by the key-on memory 46 is selected only for about 10 ms in the beginning of key depression,and it is outputted as the first key-on signal KO.sub.1. Thus, in the automatic bass chord performance, the first key-on signal KO.sub.1 for a tone (automatic bass) assigned to the pedal keyboard exclusive channel is provided only for about 10 ms. Thisshort first key-on signal KO.sub.1 is used for converting the amplitude envelope of an automatic bass tone (pedal keyboard tone) into an attack system envelope.
In the upper keyboard exclusive channel time, and the lower keyboard exclusive channel time, and in the pedal keyboard exclusive channel time where no automatic bass chord is effected, the output of the NAND circuit 116 is at "1" at all times. The first key-on signal KO.sub.1 is produced exactly in accordance with a key depression operation (similarly as in the key-on signal KO) in these channel times. This first key-on signal KO.sub.1 is used for giving a sustain system amplitude envelope toa musical tone.
The second key-on signal KO.sub.2 outputted by the AND circuit 114 is employed for converting the amplitude envelopes of the upper and lower keyboard tones into attack system envelopes. The term "attack system envelope" is intended to mean anenvelope waveform which is employed for producing a musical tone only for a short time period (about 10 ms for instance) in the beginning of key depression. The output signal of a NAND circuit 126 in the attack system key-on signal generating circuit 20is applied to the other input terminal of the AND circuit 114. This NAND circuit 126 is enabled only when the upper keyboard exclusive channel signal YUK or the lower keyboard exclusive channel signal YLK is applied through an OR circuit 127 thereto. Similarly as in the above-described NAND circuit 116, the output of the shift register 118 is applied to the remaining input terminals of the NAND circuit 126. When it passes about 10 ms after depression of a key in the lower keyboard is started, or inthe channel time to which the key has been assigned, the output of the shift register 118 has "1 1 1", as a result of which the NAND circuit 126 is operated, and its output is changed to "0". As a result, the AND circuit 114 is disabled in that channeltime. Accordingly, the second key-on signal KO.sub.2 is produced only for about 10 ms after depression of a key in the lower keyboard is started. With respect to the upper keyboard tone and the lower keyboard tone, selective use of the first and secondkey-on signals KO.sub.1 and KO.sub.2 is suitably effected in the digital tone generator section 16. The selective use of these signals KO.sub.1 and KO.sub.2 is controlled with the aid of an envelope control signal EC supplied from the key coder 11.
(Truncate Control)
The new key-off signal NKF outputted by the AND circuit 103 and the key-off memory signal KOFM outputted by the key-off memory 49 in FIG. 6 are applied to the truncate circuit 21 in FIG. 7. In the truncate circuit 21, the channel of a key whichwas released earliestly is detected separately in the upper keyboard exclusive channel and the lower keyboard exclusive channel, and a truncate channel designation signal TR is produced in synchronization with that channel time. A counter is made up ofa 4-bit adder 129 consisting of four half adders and a 16-stage/4-bit shift register 130. If, after keys assigned to the channels are released, other keys are released, the numbers of times of release of said other keys are counted in time divisionmanner separately according to the channels by the counter. Accordingly, it can be said that a key assigned to a channel having the maximum value in the shift register 130 is the key which was released earliestly.
When a key is released, the new key-off signal NKF is produced only once in synchronization with a channel time to which the key is assigned. Therefore, if the counter comprising the adder 129 and the shift register 130 counts the number of newkey-off signals NKF, the number of times of key release can be counted. In FIG. 7, the new key-off signal NKF is applied to AND circuits 131 and 132. A first process period upper keyboard exclusive channel signal YUKI and a first process period lowerkeyboard exclusive channel signal YLK1 are applied to the remaining input terminals of the AND circuits 131 and 132, respectively. The signal YUK1 is provided in synchronization with the lower keyboard exclusive channel time (the part (c) of FIG. 3) inthe first process period (the part (f) of FIG. 3). Accordingly, when the new key-off signal NKF is provided in the upper keyboard's channel time, the AND circuit 131 is operated. As a result, a signal "1" is inputted through an OR circuit 133 into adelay flip-flop 135. On the other hand, where the new key-off signal NKF is provided in the lower keyboard's channel time, the AND circuit 132 is operated. As a result, a signal "1" is inputted through an OR circuit 134 into a delay flip-flop 136. Thestorages in the delay flip-flops 135 and 136 are self-held through AND circuits 137 and 138, respectively. As the signal Y48 is applied to the AND circuits 137 and 138, the self-holding is released in the last channel time in the third process period(the part (h) of FIG. 3). Thus, when a depressed key is released in the uper keyboard or the lower keyboard, the new key-off signal NKF is inputted into the delay flip-flop 135 or 136 in the first process period, and the output of the relevant delayflip-flop 135 or 136 is raised to "1" in a DC mode for the second and third process periods. The outputs of the delay flip-flops 135 and 136 are applied to AND circuits 139 and 140. A second process period upper keyboard exclusive channel signal YUK2and a second process period lower keyboard exclusive channel signal YLK2 are applied to the AND circuits 139 and 140, respectively. Accordingly, when a key is released in the upper keyboard, the AND circuit 139 is enabled in its keyboard's exclusivechannel time in the second process period. Similarly, when a key is released in the lower keyboard, the AND circuit 140 is enabled in its keyboard's exclusive channel time in the second process period. The key-off memory signal KOFM is applied to theremaining input terminals of the AND circuits 139 and 140. As the key-off memory signal KOFM is raised to "1" in synchronization with a channel time for which key release has been done already, the AND circuit 139 or 140 outputs a signal "1" only inthese channel times. The outputs of the AND circuits 139 and 140 are applied through an OR circuit 141 to the least significant bit in the adder 129. The adder 129 operates to add "1" applied thereto from the OR circuit 141 to the preceding additionresult with respect to a relevant channel, which is stored in the shift register 130. The result of addition of the adder 129 is applied through a group of AND circuits 142, an OR circuit 143 and AND circuit 157 to the shift register 130, where it isstored. The key-off memory signal KOFM is applied to the other input terminal of each of the AND circuits 142, and when a depressed key is assigned to a relevant channel, the signal KOFM is switched to "0", as a result of which the shift register 130 iscleared.
The output of the shift register 130 is applied to one input side (A) of a comparator 144, to the other input side (B) of which the maximum value memory data of a maximum value memory 145 or 146. Each of the maximum value memories 145 and 146 ismade up of a 4-bit delay flip-flop. The maximum value memory 145 is for the upper keyboard, and its memory data is outputted through a group of AND circuits 147 in the upper keyboard exclusive channel time. The maximum value memory 146 is for the lowerkeyboard, and its memory data is outputted through a group of AND circuits 148 in the upper keyboard exclusive channel time. The outputs of the groups of AND circuits 147 and 148 are applied through a group of OR circuits 149 to the comparator 144. That is, the comparator 144 is used, in time division manner, commonly for the upper keyboard and the lower keyboard. When the output of the shift register 130 is greated than the memory data of the maximum value memory 145 or 146 (A>B), a signal "1"is applied to an output line 150 of the comparator 144 and it is applied to AND circuits 151 and 152, to which the first process period upper keyboard exclusive channel signal YUK1 and the first process period lower keyboard exclusive channel signal YLK1are applied, respectively. Accordingly, where the signal "1" on the line 150 is a comparison result concerning the upper keyboard, the AND circuit 151 is operated; and where it is a comparison result concerning the lower keyboard, the AND circuit 152 isoperated. The output "1" of the AND circuit 151 (152) controls the AND circuit group 153 (or 154) to clear the old storage in the maximum value memory 145 (or 146) and to input a new maximum value data supplied by the shift register 130 into the maximumvalue memory 145 (or 146).
Thus, the maximum value data, that is, the highest number of times of key release is stored in the maximum value memory 145 or 146 during the first process period, and it is self-held for the second and third process periods. At the last channeltime of the third process period, the one cycle finish signal Y48 is produced and it is applied to NOR circuits 155 and 156. As a result, the outputs of the NOR circuits 155 and 156 are changed to "0", and the self-holding AND circuits of the ANDcircuit groups 153 and 154 are disabled.
The comparator 144 provides a coincidence output when the data applied to the input side (A) coincides with the data applied to the input side (B). This coincidence output is applied, as the truncate channel designation signal TR, to the ANDcircuits 72 and 73 in FIG. 6. In other words, when the same data as the maximum value data stored in the maximum value memory 145 or 146 is outputted by the shift register 130, the truncate channel designation signal TR is provided is synchronizationwith the channel time.
The initial clear signal IC provided when the power switch is turned on, is applied to the NOR circuits 155 and 156 to clear the maximum value memories 145 and 146. The initial clear signal IC is applied to the OR circuit 99 in FIG. 6 to allowall the stages of the key-off memory 49 to store "1". Therefore, immediately after the power switch is turned on, the key-off memory signals KOFM for all the channels have "1". Furthermore, the initial clear signal IC is applied through an OR circuit143 (FIG. 7) to the least significant bit of the shift register 130, as a result of which the count value of the channels of the shift register 130 is changed to "0 0 0 1". This operation is effected in the case where a key was depressed but it has notbeen released yet, in order to prevent the production of the truncate channel designation signal for the channel to which the key beind depressed has been assigned. That is, in the beginning period after the power switch is turned on, the truncatechannel designation signal TR is provided for the channels to which no assignment has not been effected.
(5) Description of the Automatic Chord Key-on Signal Generating Circuit 22:
When an automatic bass chord performance is selected, a chord tone production timing signal CG is supplied by the key coder 11. This signal CG is applied to a differentiation circuit comprising delay flip-flops 158 and 159, an inverter 160 andan AND circuit 161 in the automatic chord key-on signal generating circuit 22 in FIG. 7, where it is shaped into a differentiation pulse having a time width of 48 .mu.s. This differentiation pulse from the AND circuit 161 is applied to the resetterminal of a 2-bit binary counter 162 for 1/4 frequency division, to reset the content of the counter 162 to "0 0". When the output of the counter 162 has "0", the output of a NAND circuit 163 is raised to "1", thereby to enable an AND circuit 164. The count pulse T is applied through the OR circuit 123 (FIG. 4) to the other input terminal of the AND circuit 164, and this count pulse T is selected by the AND circuit 164 with the generation timing of the one cycle finish signal Y48. The output ofthe AND circuit 164 is applied to the count input terminal of the counter 162. When three count pulses T are provided after the counter 162 has been reset by the chord tone production timing signal, the content of the counter 162 has "1 1". As aresult, the output of the NAND circuit 163 is switched to "0", and the AND circuit 164 is disabled. Accordingly, counting the count pulse T by the counter 162 is suspended. Thus, the output of the NAND circuit 163 is at "1" for about three periods ofcount pulse T after the generation of the chord tone production timing signal CG. This output "1" of the NAND circuit 163 is provided, as an automatic chord key-on signal KO.sub.3, through an AND circuit 165. Since the count pulse T has a period ofabout 1500 .mu.s, the pulse width of the key-on signal KO.sub.3 is about 4.5 ms (1.5 ms.times.3). The lower keyboard key depression memory signal LKM is applied to the other input terminal of the AND circuit 165. Therefore, when a key is depressed inthe lower keyboard or a key code N.sub.1 -B.sub.3 concerning a chord is periodically supplied by the key coder 11, the signal LKM is sustained at "1" to enable the AND circuit 165. This is because a chord tone is processed as a lower keyboard tone.
The lower keyboard key depression memory signal LKM can be obtained by selectively storing one, corresponding to the lower keyboard exclusive channel, of the key-on signals KO outputted in time division manner by the key-on memory 46 (FIG. 6). The lower keyboard exclusive channel signal YLK is applied to an AND circuit 167 (FIG. 7), which is enabled only at the lower keyboard exclusive channel time (the part (c) of FIG. 3). The key-on signal KO is applied to the other input terminal of theAND circuit 167, and only the key-on signals KO concerning the lower keyboard are selected by this AND circuit 167, and are applied through an OR circuit 168 to a delay flip-flop 169. The output of the delay flip-flop 169 is self-held by means of an ANDcircuit 170. The AND circuit 170 is disabled by the output "0" of a NOR circuit 171, to which the initial clear signal IC and a last channel signal C.sub.16 are applied. The last channel signal C.sub.16 is outputted by the AND circuit 25 in FIG. 4, andit is repeatedly provided in synchronization with the last channel time of the time division time slot train, that is, the sixteenth channel's time slot (the part (a) of FIG. 3). Therefore, at the sixteenth channel time at which the last channel signalC.sub.16 is produced, the AND circuit is disabled to release the self-holding of the delay flip-flop 169.
The output of the delay flip-flop 169 is applied to an AND circuit 172 which is enabled by the aforementioned last channel signal C.sub.16. Therefore, the storage in the delay flip-flop 169 is inputted through the AND circuit 172 and an ORcircuit 173 into a delay flip-flop 174, before its self-holding is released. The output of the delay flip-flop 174 is self-hold by means of the OR circuit 173 and an AND circuit 175. The AND circuit 175 is disabled by the output "0" of the NOR circuit171. Therefore, the self-holding of the delay flip-flop 174 is released every the sixteenth channel time at which the last channel signal C.sub.16 is provided. If a signal "1" is provided by the delay flip-flop 169 at the time slot of the sixteenthchannel, it is stored in the delay flip-flop 174 again, and the delay flip-flop 174 is self-held until the following last channel signal C.sub.16 is provided. Thus, if a key is depressed in the lower keyboard (if a tone is assigned to the lower keyboardexclusive channel), the output of the delay flip-flop 174 is raised to "1" in a DC mode. This output "1" of the delay flip-flop 174 is utilized as the lower keyboard key depression memory signal LKM.
(6) Description of the Automatic Arpeggio Circuit 23
The automatic arpeggio circuit 23 operates in accordance with the automatic arpeggio selection signal ARP delivered from the key coder 11, so that key codes N.sub.1 *-B.sub.3 (stored in the 2nd, 5th, 8th, 9th, 11th 12th and 15th stages of theshift register 26) corresponding to a plurality of keys depressed in a particular keyboard (for instance the lower keyboard) among the key codes N.sub.1 *-B.sub.3 * stored in the channels of the key code memory circuit 17 are selected in the order oftone pitches one at a time in accordance with the arpeggio tone production timing. The key code N.sub.1 *-B.sub.3 * thus selected is delivered, as tha automatic arpeggio key code AN.sub.1 -AB.sub.2, to the key code memory circuit 17 during the period(48 .mu.s) during which the automatic arpeggio selection signal ARP is provided, and it is stored in the arpeggio exclusive channel (the 14th channel) of the circuit 17. When all the stored key codes N.sub.1 *-B.sub.3 * concerning the lower keyboard areselected by the automatic arpeggio circuit 23 (when the tones of all the keys depressed in the lower keyboard are produced), the aforementioned stored key code N.sub.1 *-B.sub.3 * is carried out by the circuit 23 again. In this case, in order that thepitches of the arpeggio tones which are produced in accordance with the selected key codes N.sub.1 *-B.sub.3 * are increased (or decreased) by one octave when compared with those of the preceding tone production, the octave codes B.sub.1 *-B.sub.3 * ofthe key codes N.sub.1 *-B.sub.3 are changed to deliver the arpeggio key codes AN.sub.1 -AB.sub.2. By repeating the above-described operation, the control is effected in which arpeggio tones are repeatedly produced over a predetermined octave range oneat a time at predetermined time intervals in response to the depression of a plurality of keys in the lower keyboard. A further description of this automatic arpeggio circuit 23 will be omitted.
Referring back to FIG. 7, the initial clear signal IC is applied to the set terminal (S) of the counter 162. Therefore, when the power switch is turned on, the content of the counter 162 is set to "1 1" and the output of the NAND circuit 163 isswitched to "0", thereby to stop the count operation.
The detail fo the tone production assignment circuit 13 is as described above. As a result of the above-described assignment operation, the tone production of a key depressed in the upper keyboard is assigned to one of the 3rd, 4th, 6th, 7th,10th, 13th and 16th channels; the tone production of a key depressed in the lower keyboard or an automatic chord is assigned to one of the 2nd, 5th, 8th, 9th, 11th, 12th and 15th channels; the tone production of a key depressed in the pedal keyboard orof an automatic bass is assigned to the 1st channel; and the tone production of an automatic arpeggio is assigned to the 14th channel. The key codes N.sub.1 *-B.sub.3 * of keys assigned to the respective channels are outputted in time division manner bythe key code memory circuit 17 (FIG. 5) in synchronization with the respective channel times (the parts (a) through (e) of FIG. 3), and are applied to the data multiplex circuit 14. The first and second key-on signals KO.sub.1 and KO.sub.2 are providedin time division manner separately according to the respective channels, and are applied to the data multiplex circuit 14 from the control section 19 (FIG. 6).
(7) Description of the data Multiplex Circuit 14
In the data multiplex circuit 14 in FIG. 5, the key information such as the N.sub.1 *-B.sub.3 * and the key-on signals KO.sub.1 and KO.sub.2, supplied thereto in time division manner separately according to the channels from the tone productionassignment circuit 13 is multiplexed, and for this purpose a multiplexing control signal BO is used. Furthermore, in the data multiplex circuit 14, timing pulses Y.sub.30, Y.sub.31, Y.sub.33, Y.sub.34 and Y.sub.36 are employed for controlling themultiplexing of the control information, such as the evelope control signal EC, the damper signal DU, the automatic bass chord selection signal ABC and the slow rock selection signal SR supplied thereto from the key coder 11, and of the automatic chordkey-on signal KO.sub.3.
The multiplexing control signal BO, as indicated in the part (n) of FIG. 3, has a pulse width of 1 .mu.s and a period of 3 .mu.s.
As is apparent from the part (n) of FIG. 3, the signal BO occurs in synchronization with the 3rd, 6th, 9th, 12th, and 15 channel times in the first process period (H.sub.1), in synchronization with the 2nd, 5th, 8th, 11th and 14th channel timesin the second process period (H.sub.2), and in synchronization with the 1st, 4th, 7th, 10th, 13th and 16th channel times in the third process period (H.sub.3). This signal BO is provided by an OR circuit 199 in the timing signal generating circuit 15. An AND circuit 193 connected to the OR circuit 199 is enabled by the first process period signal H.sub.1. The outputs of the third, sixth, ninth, twelfth and fifteenth stages of the shift register 26 are applied through an OR circuit 194 to the otherinput terminal of the AND circuit 193. The second process period signal H.sub.2 is applied to an AND circuit 195 connected to the OR circuit 199. and the outputs of the second, fifth, eighth, eleventh and fourteenth stages of the shift register 26 areapplied through an OR circuit 196 to the AND circuit 195. Furthermore, the third process period signal H.sub.3 is applied to an AND circuit 197, and the outputs of the first, fourth, seventh, tenth, thirteenth and sixteenth stages of the shift register26 are applied through an OR circuit 198 to the AND circuit 197. The outputs of these AND circuits are applied to the OR circuit 199, as a result of which the multiplexing control signal BO is outputted by the OR circuit 199. Thus, as indicated in thepart (n) of FIG. 3, the multiplexing control signals BO are provided for all the channels in one process cycle.
In the data multiplex circuit 14, the pieces of key information and the pieces of control information concerning a channel are divided into three parts which are delivered out one at a time. If it is assumed that it takes one bit time (1 .mu.s)for delivering each part of the information, then it will take three bit times (3 .mu.s) for delivering the key information and control information concerning one channel. For this purpose, the multiplexing control signal BO generating period is 3 bittimes (3 .mu.s). In the data multiplex circuit 14, the signal BO is shifted successively by one bit time in the three bit times, so that it can be utilized in three different ways. More specifically, the signal BO is delayed successively by two delayflip-flops 201 and 206 (FIG. 5), thereby to provide a signal BO.sub.1 delayed by one bit time and a signal BO.sub.2 delayed by two bit times. With the aid of these three signals BO, BO.sub.1 and BO.sub.2, the key information of one channel is dividedand delivered successively. The generation timing of the three signals BO, BO.sub.1 and BO.sub.2 is shown enlarged in the parts (a), (b) and (c) of FIG. 8, respectively.
The original (not delayed) multiplexing control signal BO is applied to an AND circuit 200, and it is used for selecting the second key-on signal KO.sub.2 which is applied to the AND circuit 200 by the AND circuit 114 in FIG. 6. The signalBO.sub.1 delayed by one bit time is applied to AND circuits 202 through 205 from the delay flip-flop 201, and it is utilized to select the block code B.sub.1 *-B.sub.3 * and the first key-on signal KO. The signal BO.sub.2 delayed by two bit times isapplied to AND circuits 207 through 210, and it is employed to select the note code N.sub.1 *-N.sub.4 *. Thus, with the aid of these signals BO, BO.sub.1 and BO.sub.2, the pieces of key information KO.sub.2, B.sub.1 *-B.sub.3 *, KO.sub.1 and N.sub.1*-N.sub.4 concerning one and the same channel are selected. Therefore, after being delayed by one bit time by delay flip-flops 215, 216 and 217, the block code B.sub.1 *-B.sub.2 * outputted from the key code memory circuit 17 is applied to the ANDcircuit 202 through 204. After being delay by one bit time by a delay flip-flop 218, the first key-on signal KO.sub.1 from the AND circuit 113 in FIG. 6 is applied to the AND circuit 205. On the other hand, the note code N.sub.1 *-N.sub.4 * from thekey code memory circuit 17 is delayed by two bit times by delay flip-flop 219 through 222 and delay flip-flop 223 and 226 and is then applied to the AND circuit 207 through 210.
As a result, the key code N.sub.1 *-N.sub.4, B.sub.1 *-B.sub.3 outputted by the key code memory circuit 17 and the key-on signals KO.sub.1 and KO.sub.2 outputted by the AND circuits 113 and 114 during a channel time during which the multiplexingcontrol signal BO is produced, are selected in the form of three parts which are shifted successively by one bit time within three bit times. The pieces of key information N.sub.1 *-N.sub.4 *, B.sub.1 *-B.sub.3 *, KO.sub.1 and KO.sub.2 (9-bit data intotal) are applied to OR circuits 211 through 214, as a result of which a 4-bit data KC.sub.1 -KC.sub.4 is outputted by the channel processor 12 .Iadd.via parallel output transmission lines from the OR circuits 211 through 214 to the tone generator16.Iaddend.. More specifically, the second key-on signal KO.sub.2 selected by the AND circuit 200 with the aid of the multiplexing control signal BO is outputted as the data KC.sub.4 by the OR circuit 214, the block code B.sub.1 *-B.sub.3 * and firstkey-on signal KO.sub.1 selected by the AND circuits 202 through 204 and 205 are outputted as the data KC.sub.1 -KC.sub.4 by the OR circuits 211 through 214, and the note code N.sub.1 *-N.sub.4 * selected by the AND circuits 207 through 210 with the aidof the signal BO.sub.2 is outputted as the data KC.sub.1 -KC.sub.4 by the OR circuits 211 through 214. The states of the output data KC.sub.1 -KC.sub.4 of the channel processor 12 are as indicated in the part (d) of FIG. 8. The part (e) of FIG. 8indicates the channels of the key information N.sub.1 *-N.sub.4, B.sub.1 *-B.sub.3, KO.sub.1 and KO.sub.2 outputted in the form of data KC.sub.1 -KC.sub.4 by the channel processor 12, and its typical example is the data KC.sub.1 -KC.sub.4 concerning thethird channel. As is apparent from the above description, the time division multiplex is effected in the order of the second key-on signal KO.sub.2 (the first delivery timing), the block code B.sub.1 *-B.sub.3 * and first key-on signal KO.sub.1 (thesecond delivery timing), the note code N.sub.1 *-N.sub.4 * (the last delivery timing), in the typical example. The key information N.sub.1 *-B.sub.3 *, KO.sub.1 and KO.sub.2 outputted by the tone production assignment circuit section 13 when the delaymultiplexing control signals BO.sub.1 and BO.sub.2 are provided is not used in the data multiplex circuit 14. This key information N.sub.1 *-B.sub.3 *, KO.sub.1 and KO.sub.2 is utilized in the data circuit 14 when the multiplexing control signal BO isprovided in the relevant channel time (that is, it is multiplexed to be delivered out). For example, the key information N.sub.1 *-B.sub.3, KO.sub.1 and KO.sub.2 outputted by the tone production assignment circuit section 13 at the fourth and fifthchannel times in the first process period (H.sub.1) (cf. FIG. 3) is not utilized in the data multiplex circuit 14 as multiplex process concerning the third channel is effected in the data multiplex circuit 14 during those channel times, and in additionthe AND circuits 200, 202 through 205, and 207 through 210 are not so operated that the key information N.sub.1 *-B.sub.3 *, KO.sub. 1 and KO.sub.2 for the fourth and fifth channels is selected. However, the multiplexing control signal BO occurs at thefifth channel time of the second process period and at the fourth channel time of the third process period as indicated in the part (n) of FIG. 3, and in these cases time division multiplex process of the key information of the fourth and fifth channelsis effected. The part (0) of FIG. 3 indicates the time zones during which the time division process of the key information of the channels is carried out in the data multiplex circuit 14, and the numerals indicated therein designate channels where theprocess is effected. For convenience in description, in FIG. 8 the time division process time zones of from the sixth channel to the eleventh channel and from the seventh channel to the sixteenth channel are omitted; however, the states of the dataKC.sub.1 -KC.sub.4 in the time division process time zones thus omitted are similar to that concerning the third channel.
In one process cycle from the first process period to the third process period, one multiplexing control signal BO is provided for each channel time. Accordingly, in one process cycle (48 .mu.s), the time division multiplex process is carriedfor all the channels in the data multiplex circuit 14. Since three bit times (3 .mu.s) is required for processing one channel, 489 bit times (48 .mu.s) is required for processing sixteen channels. The time division process time zones of the channelsshown in the part (O) of FIG. 3 are the time zones during which the key information N.sub.1 *-B.sub.3 *, KO.sub.1 and KO.sub.2 of the keys or musical tones which are assigned to the channels are delivered from the channel processor 12 to the digital tonegenerator 16. These delivery time zones are completely different from the time division channel time of the tone production assignment circuit section 13, indicated in the part (a) of FIG. 3.
At the timing of delivering the second key-on signal KO.sub.2 as the data KC.sub.4, the data KC.sub.1 -KC.sub.3 are not used. Furthermore, for the pedal keyboard, the block code provided is only two bits (B.sub.1 *-B.sub.2 *, and the third bit(B.sub.3 *) is not provided (cf. the NAND circuit 126 in FIG. 6). Accordingly, in delivering the pieces of information assigned to the first channel which is the pedal keyboard's exclusive channel, the data KC.sub.1 -KC.sub.4 are not used at the firstdelivery timing, and furthermore the data KC.sub.3 (corresponding to the bit B.sub.3 *) is not used at the next delivery timing. For the automatic arpeggio, the third bit (B.sub.3 *) of its block code is not provided, and the first and second key-onsignals KC.sub.1 and KC.sub.2 are not used. Accordingly, in delivering the pieces of information which are assigned to the fourteenth channel which is the automatic arpeggio's exclusive channel, the data KC.sub.1 -KC.sub.4 are not used at the firsttiming, and the data KC.sub. 3 and KC.sub.4 are not used at the following timing.
By utilizing the timing which is not used for the time division multiplex delivery of the pieces of information of the channels, the time division multiplex delivery of the envelope control signal EC, the damper signal DU and other controlinformation is carried out.
The timing pulse Y.sub.30 is used to select the automatic chord key-on signal KO.sub.3 and the automatic bass chord selection signal ABC respectively with AND circuits 227 and 228 (FIG. 5). This timing pulse Y.sub.30 is outputted by an ANDcircuit 229 (in FIG. 4) at the thirtieth (30th) bit time from the first channel time in the first process period (that is, at the 14th channel time in the second process period (cf. the part (p) of FIG. 3). While the timing pulse Y.sub.30 occurs, theinitial timing for time-division-multiplexing the pieces of information of the 14th channel only for the automatic arpeggio occurs in the data multiplex circuit 14. However, since the second key-on signal KO.sub.2 is not used for the automatic arpeggioas was described, the time pulse Y.sub.30 is applied to an inverter 230, the output "0" of which is applied to an AND circuit 200 to disable the latter 200. Thus, the second key-on signal KO.sub.2 is not outputted from the AND circuit 200. Instead ofthis, AND circuits 227 and 228 are enabled by the timing pulse Y.sub.30, as a result of which the automatic chord key-on signal KO.sub.3 applied to the AND circuit 227 from an AND ciruit in FIG. 7 is selected and applied to the OR circuit 214, while theautomatic bass chord selection signal ABC applied to the AND circuit is selected and applied to the OR circuit 213. As a result, the signal ABC and the key-on signal KO.sub.3 are delivered, respectively as the data KC.sub.3 and the data KC.sub.4, at theinitial time (for the pulse Y.sub.30 generation timing) of the time division process time zone for the 14th channel (cf. the part (d) of FIG. 8).
The timing pulse Y.sub.31 is provided through an AND circuit 231 in FIG. 4 at the next channel time of the timing pulse Y.sub.30, or at the 15th channel time in the second process period (cf. the part (p) of FIG. 3), and it is applied to an ANDcircuit 232 in FIG. 5. The slow rock selection signal SR is applied to the other input terminal of the AND circuit 232. This signal SR is selected with the timing of the timing pulse Y.sub.31 and applied to the OR circuit 214, thus being outputted asthe data KC.sub.4. The timing pulse Y.sub.31 is provided at the second timing employed for delivering the data of the arpeggio exclusive channel. As was described before, in an ordinary delivery the first key-on signal KO.sub.1 is delivered to the lineof the data KC.sub.4 at said second timing. However, since the first key-on signal KO.sub.1 is not used for the automatic arpeggio, the timing pulse Y.sub.31 is applied through an inverter 233 to an AND circuit 205 (FIG. 5) thereby to disable the ANDcircuit 205 adapted to select the first key-on sigal KO.sub.1. Accordingly, at the generation timing of the timing pulse Y.sub.31, the slow rock selection signal SR instead of the first key-on signal KO.sub.1 is delivered as the data KC.sub.4. At thesecond delivery timing, the block code B.sub.1 *-B.sub.3 * is delivered as the data KC.sub.1 -KC.sub.3. However, in this connection, as the block code for automatic arpeggio is only two bits (AB.sub.1, and AB.sub.2), no signal is provided to the line ofthe data KC.sub.3. Accordingly, at the second delivery timing of the data of the arpeggio exclusive channel (14th channel), the block code B.sub.1 *, B.sub.2 * is delivered as the data KC.sub.1 and KC.sub.2 while the slow rock selection signal SR isdelivered as the data KC.sub.4.
The timing pulse Y.sub.33 is provided through an AND circuit 234 in FIG. 4 at the first channel time of the third process period (H.sub.3) (cf. the part (p) of FIG. 3). In this operation, the multiplexing control signal BO is also provided (thepart (h) of FIG. 3), and the first timing for delivering the data of the first channel, of the pedal keyboard's exclusive channel, occurs. However, since the second key-on signal KO.sub.2 will not be used for the pedal keyboard tone, it is unnecessaryto deliver the second key-on signal KO.sub.2 at this first timing. In view of this, the first timing in the time division process time zone concerning the pedal keyboard's exclusive channel is utilized for delivering a reference data. For this purpose,the timing pulse Y.sub.33 is applied to the OR circuits 211 through 214 to raise the levels of the data KC.sub.1 -KC.sub.4 to "1" (cf. the part (d) of FIG. 8). The data KC.sub.1 -KC.sub.4 whose contents are made to "1 1 1 1" as described above is theaforementioned reference data. This reference data "1 1 1 1" is utilized, as information indicating a reference timing for discriminating the location timing of various data which have been subjected to time division multiplex in the data multiplexcircuit 14, in the digital tone generator section 16.
As is apparent from Table 1 and Table 2 disclosed before, it is determined that the data "1 1 1 1" is not used for the note code N.sub.1 -N.sub.4 (N.sub.1 *-N.sub.4 *) (at least, it is not used for the storage operation of the key code memorycircuit 17), and that the data "1 1 1" is not used for the block code B.sub.1 -B.sub.3 (B.sub.1 *-B.sub.3 *). Therefore, the reference data "1 1 1 1" will never be mistaken for other key information and control information.
The timing pulse Y.sub.34 is produced one bit time later than the production of the timing pulse Y.sub.33 (cf. the part (p) of FIG. 3). That is, it is produced through an AND circuit in FIG. 4. This timing pulse Y.sub.34 is applied to an ANDcircuit 236 in FIG. 5, as a result of which the damper signal DU applied to the other input terminal of the AND circuit 236 is selected and applied to the OR circuit 213. The timing pulse Y.sub.34 is further applied through an inverter 237 to the ANDcircuit 204 to disable the latter 204. Therefore, the third bit B.sub.3 * of the block code is blocked, and therefore the damper signal DU is outputted as the data KC.sub.3. In this case, as the block code B.sub.1 *-B.sub.3 * applied to the ANDcircuits 202, 203 and 204 is of the pedal keyboard, the third bit data B.sub.3 * is unnecessary (cf. Table 2). Accordingly, at the second timing concerning the pedal keyboard's exclusive channel (1st channel), the data B.sub.1 *, B.sub.2 *, DU andKO.sub.1 are delivered as the data KC.sub.1 -KC.sub.4 as indicated in the part (d) of FIG. 8.
The timing pulse Y.sub.36 is outputted by an AND circuit 238 (FIG. 4) at the 4th channel time of the third process period (H.sub.3) as indicated in the part (p) of FIG. 3, and it is applied to an AND circuit 239 in FIG. 5, to the other inputterminal of which the envelope control signal EC is applied. The envelope control signal EC is selected with the timing of the timing signal Y.sub.36, and is delivered, as the data KC.sub.3, through the OR circuit 213. While the timing pulse Y.sub.36occurs, the multiplexing control signal BO occurs also (cf. FIG. 3), as a result of which the initial delivery timing of the data assigned to the 4th channel occurs. Accordingly, no key information to be delivered as the data KC.sub | | | |
