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Semiconductor package
D466485 Semiconductor package
Patent Drawings:Drawing: D466485-2    Drawing: D466485-3    Drawing: D466485-4    Drawing: D466485-5    
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(4 images)

Inventor: Maehara, et al.
Date Issued: December 3, 2002
Application: D/142,263
Filed: May 23, 2001
Inventors: Igarashi; Koji (Hanno, JP)
Maehara; Kenichi (Kawagoe, JP)
Assignee: Shindengen Electric Manufactuturing Co., Ltd. (Tokyo, JP)
Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney Or Agent: Antonelli, Terry, Stout & Kraus, LLP
U.S. Class: D13/182
Field Of Search: D13/182; D14/114; 174/52.1; 174/52.2; 174/52.4; 174/52.5; 174/16.3; 206/710; 206/719; 257/254; 257/659; 257/697; 257/730; 257/738; 324/755; 324/765; 361/752; 361/798; 361/850; 361/718; 361/730
International Class:
U.S Patent Documents: 3602846; 3846734; 4391408; 4441119; D288922; 4951122; 4979016; D317592; 5337216; 5387814; D357901; 5539250; 5646443; D401567; D401912; 5959842; 6018191; 6303982
Foreign Patent Documents:
Other References:









Abstract:
Claim: The ornamental design for a semiconductor package, as shown and described.
Description: FIG. 1 is a front, plan and right side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front, bottom and right side perspective view thereof;

FIG. 3 is a rear, plan and left side perspective view thereof;

FIG. 4 is a rear, bottom and left side perspective view thereof;

FIG. 5 is a front elevational view thereof;

FIG. 6 is a rear elevational view thereof;

FIG. 7 is a top plan view thereof;

FIG. 8 is a bottom plan view thereof;

FIG. 9 is a left side elevational view thereof; and,

FIG. 10 is a right side elevational view thereof.

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