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Substrate for a semiconductor element |
| D457146 |
Substrate for a semiconductor element
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| Patent Drawings: | |
| Inventor: |
Yamamoto, et al. |
| Date Issued: |
May 14, 2002 |
| Application: |
D/142,483 |
| Filed: |
May 29, 2001 |
| Inventors: |
Hashiguchi; Tadaharu (Yokohama, JP)
Yamamoto; Kazuhiro (Ninomiya-machi, JP)
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| Assignee: |
Kabushiki Kaisha Toshiba (Tokyo, JP) |
| Primary Examiner: |
Shooman; Ted |
| Assistant Examiner: |
Sikder; Selina |
| Attorney Or Agent: |
Banner & Witcoff, Ltd. |
| U.S. Class: |
D13/182 |
| Field Of Search: |
D13/182; 174/52.1; 174/52.4; 257/666; 257/678; 257/688; 257/690; 257/691; 257/692; 257/696; 257/697; 257/703; 257/777; 257/778; 257/779; 257/780; 361/679; 361/728; 361/748; 361/761 |
| International Class: |
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| U.S Patent Documents: |
4471158; 4602271; D319045; D319629; D319814; 5895967; D442150 |
| Foreign Patent Documents: |
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| Other References: |
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| Abstract: |
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| Claim: |
The ornamental design for a substrate for a semiconductor element, as shown and described. |
| Description: |
FIG. 1 is a right side elevational view of a substrate for a semiconductor element, showing our new design; the opposite side being an identical image thereof;
FIG. 2 is a top plan view thereof; the opposite side being an identical image thereof;
FIG. 3 is a front elevational view thereof; and,
FIG. 4 is a rear elevational view thereof.
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