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Temporary package for semiconductor dice |
| D401567 |
Temporary package for semiconductor dice
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| Patent Drawings: | |
| Inventor: |
Farnworth, et al. |
| Date Issued: |
November 24, 1998 |
| Application: |
D/070,005 |
| Filed: |
April 25, 1997 |
| Inventors: |
Akram; Salman (Boise, ID)
Farnworth; Warren M. (Nampa, ID)
Hembree; David R. (Boise, ID)
Wood; Alan G. (Boise, ID)
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| Assignee: |
Micron Technology, Inc. (Boise, ID) |
| Primary Examiner: |
Vinson; Brian N. |
| Assistant Examiner: |
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| Attorney Or Agent: |
Gratton; Stephen A. |
| U.S. Class: |
D13/182 |
| Field Of Search: |
D13/182; 324/755; 324/765; 437/209 |
| International Class: |
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| U.S Patent Documents: |
D394844; 5173451; 5302891; 5408190; 5440240; 5451165; 5495179; 5517125; 5519332; 5530376; 5541525; 5543725; 5581195; 5742169 |
| Foreign Patent Documents: |
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| Other References: |
Van Zant, Peter, Microchip Fabrication--A Practical Guide To Semiconductor Processing, Second Edition, 1990, pg. 493.. |
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| Abstract: |
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| Claim: |
The ornamental design for a temporary package for testing semiconductor dice, as shown and described. |
| Description: |
FIG. 1 is an enlarged top perspective view of a temporary package for semiconductor dice showing my new design;
FIG. 2 is a left side elevational view thereof;
FIG. 3 is a right side elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a front side elevational view thereof;
FIG. 6 is a bottom plan view thereof; and,
FIG. 7 is a rear side elevation view thereof.
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