Resources Contact Us Home
Food slicer in the storage position
D263840 Food slicer in the storage position
Patent Drawings:Drawing: D263840-2    Drawing: D263840-3    
« 1 »

(2 images)

Inventor: Rinaldi
Date Issued: April 13, 1982
Application: 06/099,325
Filed: December 3, 1979
Inventors: Rinaldi; Joseph A. (Bergen County, NJ)
Assignee: Rival Manufacturing Company (Kansas City, MO)
Primary Examiner: Caun; Peter M.
Assistant Examiner:
Attorney Or Agent: Lowe, Kokjer, Kircher, Wharton & Bowman
U.S. Class: D7/383
Field Of Search: D15/97; 83/703; 83/713; 83/718
International Class:
U.S Patent Documents: D113839; D239462; 1972250; 2573860
Foreign Patent Documents:
Other References:

Claim: The ornamental design for a food slicer in the storage position, as shown and described.
Description: FIG. 1 is a left side elevational view of the food slicer in the stored position showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front end elevational view thereof;

FIG. 4 is a rear end elevational view thereof;

FIG. 5 is a right side elevational view thereof; and

FIG. 6 is a bottom plan view thereof.

* * * * *
  Recently Added Patents
Voltage level shift circuits and methods
Vehicle having power supply apparatus
Signal activated molecular delivery
Fluorescent dyes, fluorescent dye kits, and methods of preparing labeled molecules
Scanning projection apparatus with tangential compensation
Methods and systems for distributing broadcast messages on various networks
Method for forming pattern
  Randomly Featured Patents
Absorbent article comprising an elastic laminate
Method of controlling plant nematodes
Protective tab structure for use in the fabrication of matrix addressed thin film transistor liquid crystal displays
Basic calcium aluminum hydroxide dicarboxylates, a process for their production and their use
Semiconductor laser and method for producing the same
In-vehicle speaker panel
System and method for automatically calibrating an alignment reference source
Writing driver circuit of phase-change memory
Circuit arrangement for registering false release signals for a restraint system
Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification