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System and method of providing a memory hierarchy
7930666 System and method of providing a memory hierarchy
Patent Drawings:Drawing: 7930666-10    Drawing: 7930666-11    Drawing: 7930666-12    Drawing: 7930666-13    Drawing: 7930666-14    Drawing: 7930666-15    Drawing: 7930666-16    Drawing: 7930666-17    Drawing: 7930666-18    Drawing: 7930666-19    
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Inventor: Schmit, et al.
Date Issued: April 19, 2011
Application: 11/609,875
Filed: December 12, 2006
Inventors: Schmit; Herman (Palo Alto, CA)
Pugh; Daniel J. (Los Gatos, CA)
Teig; Steven (Menlo Park, CA)
Assignee: Tabula, Inc. (Santa Clara, CA)
Primary Examiner: Rossoshek; Helen
Assistant Examiner:
Attorney Or Agent: Adeli & Tollen LLP
U.S. Class: 716/115; 703/14; 703/15; 716/102; 716/103; 716/104; 716/106; 716/107; 716/108; 716/116; 716/117; 716/136
Field Of Search: 716/3; 716/4; 716/5; 716/6; 716/16; 716/18; 703/14; 703/15; 326/38
International Class: G06F 17/50
U.S Patent Documents:
Foreign Patent Documents:
Other References: Schmit et al.; "Array mapping in behavioral synthesis"; Sep. 13-15, 1995; System Synthesis, 1995., Proceedings of the Eighth InternationalSymposium on; pp. 90-95. cited by examiner.
Ramachandran et al.; "An algorithm for array variable clustering" ; Feb. 28-Mar. 3, 1994; European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event inASIC Design, Proceedings; pp. 262-266. cited by examiner.
Ditmar et al.; "Array Synthesis in Systemc Hardware Compilation "; Publication Year: 2007; Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on; , pp. 23-28. cited by examiner.
Kim et al.; "Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design"; Publication Year: 2005; Design Automation Conference, 2005. Proceedings. 42nd, pp. 105-110. cited by examiner.
Seo et al.: "Memory allocation and mapping in high-level synthesis--an integrated approach"; Publication Year: 2003; Very Large Scale Integration (VLSI) Systems, IEEE Transactions on; vol. 11 , Issue: 5 pp. 928-938. cited by examiner.
Ahmad et al.; "Post-processor for data path synthesis using multiport memories "; Publication Year: 1991; Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on; pp. 276-279. cited by examiner.
Ouaiss et al.: "Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers "; Publication Year: 2001; Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings; pp. 650-657. cited by examiner.
Schmit et al.; Synthesis of application-specific memory designs; Publication Year: 1997; Very Large Scale Integration (VLSI) Systems, IEEE Transactions on; vol. 5 , Issue: 1; pp. 101-111. cited by examiner.
U.S. Appl. No. 12/058,662, filed Mar. 28, 2008, Caldwell, Andrew, et al. cited by other.
U.S. Appl. No. 11/371,214, filed Mar. 8, 2006, Schmit, Herman, et al. cited by other.
U.S. Appl. No. 11/371,191, filed Mar. 8, 2006, Schmit, Herman, et al. cited by other.
U.S. Appl. No. 11/371,194, filed Mar. 8, 2006, Redgrave, Jason, et al. cited by other.
U.S. Appl. No. 11/371,352, filed Mar. 8, 2006, Schmit, Herman, et al. cited by other.
U.S. Appl. No. 11/371,198, filed Mar. 8, 2006, Schmit, Herman, et al. cited by other.
U.S. Appl. No. 11/609,883, filed Dec. 12, 2006, Schmit, Herman, et al. cited by other.
Notice of Allowance of U.S. Appl. No. 11/081,883, Jul. 9, 2007, (mailing date), Hutchings, Brad, et al., now issued as 7,298,169. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/081,883, Mar. 13, 2007, (mailing date), Hutchings, Brad, et al., now issued as 7,298,169. cited by other.
Non-Final Office Action of U.S. Appl. 11/081,883, Nov. 3, 2006, (mailing date), Hutchings, Brad, et al., now issued as 7,298,169. cited by other.
Final Office Action of U.S. Appl. No. 11/081,850, May 28, 2008, (mailing date), Hutchings, Brad. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/081,850, Sep. 10, 2007, (mailing date), Hutchings, Brad. cited by other.
Notice of Allowance of U.S. Appl. No. 11/081,867, Jul. 11, 2007, (mailing date), Schmit, Herman, et al., now issued as U.S. Patent 7,301,368. cited by other.
Final Office Action of U.S. Appl. No. 11/081,867, Apr. 13, 2007, (mailing date), Schmit, Herman, et al., now issued as U.S. Patent 7,301,368. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/081,867, Oct. 24, 2006, (mailing date), Schmit, Herman, et al., now issued as U.S. Patent 7,301,368. cited by other.
Notice of Allowance of U.S. Appl. No. 11/081,809, Feb. 23, 2007, (mailing date), Schmit, Herman, et al., now issued U.S. Patent 7,242,216. cited by other.
Notice of Allowance of U.S. Appl. No. 11/081,809, Oct. 26, 2006, (mailing date), Schmit, Herman, et al., now issued U.S. Patent 7,242,216. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/757,982, Feb. 20, 2008, (mailing date), Schmit, Herman, et al. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/371,352, Sep. 17, 2008, (mailing date), Schmit, Herman, et al. cited by other.
".sctn.3 Programmable Logic Devices," Digital System Design, 2001 Month N/A, slides 3.1-3.28. cited by other.
"Design for Low Power in Actel Antifuse FPGAs", Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8. cited by other.
"The Effect of SRAM Table Sharing and Cluster Size on FPGA Area", NPL Date Unknown, pp. 1-10, Dec. 12, 2006. cited by other.
"The Xilinx Virtex Series FPGA," Jan. 22, 2001, slides 1-22. cited by other.
"Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture," ISCA '04, Jun. 19-23, 2004, ACM, Munchen, Oberbayern, Germany. cited by other.
Agrawal, O., et al., "An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions," FPGA 99, Feb. 1999, pp. 17-26, ACM, Monterey, CA. cited by other.
Ahmed, E., et al., "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," FPGA 2000, Feb. 2000, ACM, Monterey, CA. cited by other.
Altera Corp., "6. DSP Blocks in Stratix II Devices," SII52006-1.0, Feb. 2004, pp. 1-32. cited by other.
Altera, "Stratix II DSP Performance," White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA. cited by other.
Andraka Consulting Group, Inc., "Multiplication in FPGAs," http://www.andraka.com/multipli.htm, Jan. 25, 2006, pp. 1-7. cited by other.
Backus, J., "Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs," Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, No. 8, ACM. cited by other.
Barker, R., "QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set," A Technology Application Whitepaper, Jan. 26 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Brand, D., et al., "Minimization of AND-EXOR Expressions Using Rewrite Rules," IEEE Transactions on Computers, May 1993, pp. 568-576, IEEE. cited by other.
Butts, M., "Future Directions of Dynamically Reprogrammable Systems," IEEE 1995 Custom Integrated Circuits Conference, May 1995, pp. 487-494, IEEE. cited by other.
Camposano, R., "The Growing Semiconductor Zoo: ASICs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia," Aug. 29 2003, pp. 1-74, Synopsys, Inc. cited by other.
Caspi, E., et al., "A Streaming Multi-Threaded Model," MSP-3, Dec. 2, 2001, pp. 1-23. cited by other.
Caspi, E., et al., "Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial," Aug. 25, 2000, pp. 1-31, Version 1.0. cited by other.
Chiricescu, S., et al., "Morphable Multipliers," FPL 2002, LNCS 2438, Sep. 2002, pp. 647-656, Springer-Verlag Berlin Heidelberg. cited by other.
Ciemat, J.V., et al., "Annealing Placement by Thermodynamic Combinatorial Optimization," ACM Transactions on Design Automation of Electronic Systems, Jul. 2004, pp. 310-332, vol. 9, No. 3, ACM, New York, NY. cited by other.
Compton, K., et al., "An Introduction to Reconfigurable Computing," IEEE Computer, Apr. 2000. cited by other.
Compton, K., et al., "Reconfigurable Computing: A Survey of Systems and Software," ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, NY. cited by other.
Cong, J., et al., "A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA," pp. 1-22, Dec. 12, 2006. cited by other.
Cong, J., et al., "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc. cited by other.
Coudert, O., "Chapter 13: Doing Two-Level Logic Minimization 100 Times Faster," Proceedings of the 6.sup.th annual ACM-SIAM symposium on Discrete algorithms, Jan. 1995, pp. 112-121. cited by other.
Damiani, M., et al., "The Disjunctive Decomposition of Logic Functions," Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1997, pp. 78-82, San Jose, CA. cited by other.
Davare, A., et al., "The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications," DAC '04, Jun. 7-11, 2004, ACM, San Diego, CA. cited by other.
Dehon, A., "Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization)," Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134. citedby other.
Dehon, A., "DPGA Utilization and Application," Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays FPGA, Feb. 11-13, 1996, Monterey, CA. cited by other.
Dehon, A., "Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density," Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54. cited by other.
Dehon, A., "Reconfigurable Architectures for General-Purpose Computing," A.I. Technical Report No. 1586, Oct. 1996, pp. i-353. cited by other.
Dehon, A., "The Density Advantage of Configurable Computing," Apr. 2000, pp. 41-49, IEEE. cited by other.
Dehon, A., "Transit Note #121: Notes on Programmable Interconnect," M.I.T. Transit Project, Feb. 1995, pp. 1-13. cited by other.
Dehon, A., et al., "Design Patterns for Reconfigurable Computing," Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 2004. cited by other.
Dehon, A., et al., "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21.sup.st Century," FCCM '94-IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1994, Napa Valley, CA. cited by other.
Dehon, A., et al., "Reconfigurable Computing: What, Why, and Implications for Design Automation," DAC 1999, Jun. 1999, ACM, New Orleans, Louisiana. cited by other.
Enzler, R., et al., "Virtualizing Hardware with Multi-Context Reconfigurable Arrays," Lecture Notes in Computer Science, Sep. 2003, pp. 151-160. cited by other.
Gayasen, A., et al., "Reducing Leakage Energy in FPGAs Using Region-Constrained Placement," FPGA '04, Feb. 22-24, 2004, pp. 51-58, ACM, Monterey, CA. cited by other.
George, V., "Low Energy Field-Programmable Gate Array," A Dissertation Submitted in Partial Satisfaction o the Requirements for the Degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the Graduate Divisionof the University of CA, Berkeley, Fall 2000 Month N/A, pp. 1-190. cited by other.
Giraud-Carrier, C., "A Reconfigurable Data Flow Machine for Implementing Functional Programming Languages", SIGPLAN Notices, Sep. 1994, vol. 29 (9): 22-28. cited by other.
Goldstein, S.C., et al., "PipeRench: A Coprocessor for Streaming Multimedia Acceleration", In International Symposium on Computer Architecture (ISCA), pp. 28-39, May 1999. cited by other.
Goldstein, S.C., et al., "PipeRench: A Reconfigurable Architecture and Compiler," Apr. 2000, pp. 70-77, IEEE. cited by other.
Hauck, S., et al., "High-Performance Carry Chains for FPGAs," FPGA 98, Feb. 1998, pp. 223-233, ACM, Monterey, CA. cited by other.
Hauck, S., et al., "Montage: An FPGA for Synchronous and Asynchronous Circuits," Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, 1993 Month N/A, Springer-Verlag, Berlin. cited by other.
Hauck, S., et al., "Totem: Domain-Specific Reconfigurable Logic," IEEE Transactions on VLSI Systems, 2006 Month N/A, pp. 1-25. cited by other.
Heidari, G., et al., "Introducing a Paradigm Shift in the Design and Implementation of Wireless Devices," A Wireless Devices Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-10, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Hofstee, H.P., "Cell Broadband Engine Architecture from 20,000 Feet," Aug. 24, 2005, pp. 1-6. cited by other.
Huang, A.S., "Tao: An Architecturally Balanced Reconfigurable Hardware Processor," Submitted to the Dept. of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degrees of Bachelor of Science in ElectricalScience and Engineering and Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, May 23, 1997, pp. 1-86, 107-109. cited by other.
IBM, "Cell Broadband Engine Architecture, Version 1.0," Aug. 8, 2005, pp. 1-319. cited by other.
IBM, "SPU Application Binary Interface Specification, Version 1.3," CBEA JSRE Series, Aug. 1, 2005, pp. iv-26. cited by other.
IBM, "SPU Assembly Language Specification, Version 1.2," CBEA JSRE Series, Aug. 1, 2005, pp. iii-22. cited by other.
IBM, "SPU C/C++ Language Extensions, Version 2.0" CBEA JSRE Series, Aug. 1, 2005, pp. iv-84. cited by other.
IBM, "Synergistic Processor Unit Instruction Set Architecture, Version 1.0," Aug. 1, 2005, pp. 1-257. cited by other.
Kaviani, A., et al., "Computational Field Programmable Architecture," Custom Integrated Circuits Conference, 1998, Proceedings of the IEEE 1998, May 11-14, 1998. cited by other.
Kaviani, A., et al., "Hybrid FPGA Architecture," Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays, Feb. 11-13, 1996, pp. 3-9, Monterey, CA. cited by other.
Keutzer, K., "Overview of *configurable* architectures," Feb. 28, 2002, slides 1-29. cited by other.
Kocan, F., et al., "Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays," FPL 2004, Aug./Sep. 2004, pp. 289-300, Springer-Verlag, Berlin Heidelberg. cited by other.
Kravets, V.N, et al., "Generalized Symmetries in Boolean Functions," Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2000, San Jose, CA. cited by other.
Lehn, D.I., et al., "Evaluation of Rapid Context Switching on a CSRC Device," Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Jun. 24-27, 2002. cited by other.
Lemieux, G., et al., "Generating Highly-Routable Sparse Crossbars for PLDs," FPGA 2000, Feb. 2000, ACM, Monterey, CA. cited by other.
Lemieux, G., et al., "Using Sparse Crossbars within LUT Clusters," FPGA 2001, Feb. 11-13, 2001, ACM, Monterey, CA. cited by other.
Lertora, F., et al., "Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-On-Chip," 13.sup.th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005) 2005, Apr. 18-20,2005. cited by other.
Lewis, D., et al., "The Stratix-II Routing and Logic Architecture," Proceedings of the 2005 ACM/SIGDA 13.sup.th International Symposium on Field-Programmable Gate Arrays, pp. 1-22, Feb. 20-22, 2005, Monterey, CA. cited by other.
Ling, A., "The Search for the Optimal FPGA Logic Block," 2001 Month N/A, ACM. cited by other.
M2000, "FIexEOS Embedded FPGA Cores," 2003 Month N/A, M2000. cited by other.
Markovskiy, Y., et al., "Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine," FPGA '02, Feb. 24-26, 2002, ACM, Monterey, CA. cited by other.
Master, P., "The Next Big Leap in Reconfigurable Systems," A Technology Vision Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-8, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Mathstar, Inc., "MathStar FPOA Architecture: A New Approach to High Throughput, Scalable, and Reprogrammable Design," Technology Overview, 2003 Month N/A, MathStar, Inc. cited by other.
Mirsky, E., et al., "MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1996. cited by other.
Mirsky, E., et al., "MATRIX: A Reconfigurable Computing Device with Configurable Instruction Distribution and Deployable Resources (Extended Abstract)," Hot Chips Symposium 1997, Aug. 1997. cited by other.
Mishchenko, A., "Fast Computation of Symmetries in Boolean Functions," Computer-Aided Design of Integrated Circuits and Systems, Nov. 2003. cited by other.
Mishchenko, A., et al., "A New Enhanced Constructive Decomposition and Mapping Algorithm," DAC 2003, Jun. 2-6, 2003, pp. 143-148, ACM, Anaheim, CA. cited by other.
Morris, K., "Lattice Launches XP: Non-Volatility at the Forefront of FPGA," FPGA and Programmable Logic Journal, Mar. 1 2005, pp. 1-5, Techfocus Media, Inc. cited by other.
Morris, K., "Rationalizing Reconfigurability: The Importance of Being Programmable," FPGA and Structured ASIC Journal, Sep. 27, 2005. cited by other.
Nelson, B.E., "Reconfigurable Computing: An Introduction and Overview," Sep. 23, 1998, pp. 1-43. cited by other.
Niedzielski, D., "An Overview of Reconfigurable Computing," NPL Date Unknown, Dec. 12, 2006. cited by other.
Ochotta, E.S., et al., "A Novel Predictable Segmented FPGA Routing Architecture," FPGA 98, Feb. 1998, pp. 3-11, ACM, Monterey, CA. cited by other.
Ohkura, J., et al., "Dataflow in the Adaptive Computing Machine (ACM)," A Technology Application Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-9, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Parhami, B., "Part IV: Low-Diameter Architectures," ECE 2548: Advanced Computer Architecture: Parallel Processing, UCSB, Spring 2005 Month N/A, slides 1-93, Behrooz Parhami, Santa Barbara, CA. cited by other.
Pedram, M. "IEEE Circuits and Systems Society Distinguished Lecturer Program," NPL Date Unknown, Dec. 12, 2006. cited by other.
Perissakis, S., et al., "Embedded DRAM for a Reconfigurable Array," Proceedings of the 1999 Symposium on VLSI Circuits, Jun. 1999, slides 1-24. cited by other.
Perissakis, S., et al., "Embedded DRAM for a Reconfigurable Array," Proceedings of the 1999 Symposium on VLSI Circuits, Jun. 1999. cited by other.
Perkowski, M.A., "A New Representation of Strongly Unspecified Switching Functions and its Application to Multi-Level and/or/EXOR Synthesis," Proc. Of the 2.sup.nd Workshop on Applications of Reed-Muller Expansion in Circuit Design, Aug. 27-29,1995, pp. 143-151, Chiba City, Japan. cited by other.
Plunkett, B., "In Search of the SDR Holy Grail," A Technology Application Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-7, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Plunkett, B., et al., "Adapt2400 ACM Architecture Overview," A Technology Whitepaper, 2004 Month N/A, pp. 1-9, QuickSilver Technology, Inc. cited by other.
Quicklogic Corp., "Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM", Eclipse II Family Data Sheet, Nov. 2005, pp. 1-92, QuickLogic Corporation, US. cited by other.
Quicksilver Technology, Inc., "Adapt2000 ACM System Platform," Apr. 2004, pp. 1-39, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Quicksilver Technology, Inc., "InSpire SDK Tool Set," Product Brief, 2004 Month N/A, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Quicksilver Technology, Inc., "QS2412 Adaptive Computing Machine," Product Brief, 2004 Month N/A, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Rahman, A., et al., "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2003, pp. 44-54, vol. 11, No. 1, IEEE. cited by other.
Rose, J., "Hard vs. Soft: The Central Question of Pre-Fabricated Silicon," 34.sup.th International Symposium on Multiple-Valued Logic (ISMVL '04), May 2004, pp. 2-5. cited by other.
Sambhwani, S., et al., "Implementing W-CDMA Transceiver Structure on an Adaptive Computing Platform," A Technology Application Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-12, QuickSilver Technology, Inc., San Jose, CA. cited by other.
Scalera, S.M., et al., "A Mathematical Benefit Analysis of Context Switching Reconfigurable Computing," Proceedings of the 5.sup.th Reconfigurable Architectures Workshop (RAW), Mar. 30, 1998, vol. 1388 of Lecture Notes in Computer Science, pp.73-78. cited by other.
Schaumont, P., et al., "A Quick Safari Through the Reconfiguration Jungle," 38.sup.th Design Automation Conference, Jun. 2001, pp. 172-177, Las Vegas, Nevada. cited by other.
Schmit, H., "Extra-Dimensional Island-Style FPGAs," Field Programmable Logic and Application (FPL 2003), Sep. 2003, pp. 406-415. cited by other.
Schmit, H., "Extra-dimensional Island-Style FPGAs," Field Programmable Logic and Application (FPL 2003), Sep. 2003, slides 1-26. cited by other.
Schmit, H., "Incremental Reconfiguration for Pipelined Applications," Proceedings of the 5.sup.th IEEE Symposium on FPGA-Based Custom Computing Machines, Apr. 16-18 1997. cited by other.
Schmit, H., et al., "FPGA Switch Block Layout and Evaluation," FPGA '02, Feb. 24-26, 2002, ACM, Monterey, CA. cited by other.
Schmit, H., et al., "PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology," Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, May 12-15, 2002, pp. 63-66. cited by other.
Schmit, H., et al., "Queue Machines: Hardware Compilation in Hardware," Proceedings of the 10.sup.th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 22-24, 2002. cited by other.
Scholl, C., "Multi-output Functional Decomposition with Exploitation of Don't Cares," May 19-21, 1997. cited by other.
Sharma, A., et al., "Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques," Proceedings of the IEEE Conference on Field-Programmable Technology 2005, Dec. 11-14, 2005. cited by other.
Sheeran, M., "Generating Fast Multipliers Using Clever Circuits." NPL Date Unknown Dec. 12, 2006. cited by other.
Singh, A., et al., "Interconnect Pipelining in a Throughput-Intensive FPGA Architecture," FPGA 2001, Feb. 11-13, 2001, pp. 153-160, ACM, Monterey, CA. cited by other.
Singh, A., et al., "PITIA: An FPGA for Throughput-Intensive Applications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jun. 2003, pp. 354-363, vol. 11, No. 3, IEEE. cited by other.
Slade, A.L., et al., "Reconfigurable Computing Application Frameworks," 11.sup.th Annual IEEE Symposium on Field-Programmable Custom Computer Machines, Apr. 9-11, 2003. cited by other.
Snider, G., "Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware," FPGA '02, Feb. 24-26, 2002, pp. 177-186, ACM, Monterey, CA. cited by other.
Stankovic, R.S., et al., "Remarks on the Number of Logic Networks with Same Complexity Derived from Spectral Transform Decision Diagrams," Proceedings Int. TICS Workshop on Spectral Methods and Multi-Rate Signal Processing, SMMSP '02, Sep. 7-8,2002, pp. 163-170, Toulouse, France. cited by other.
Tau, E., et al., "A First Generation DPGA Implementation," Proceedings of the Third Canadian Workshop on Field-Programmable Devices, May 1995, pp. 138-143. cited by other.
Tau, E., et al., "Transit Note #114: A First Generation DPGA Implementation," M.I.T. Transit Project, Jan. 1995, pp. 1-8. cited by other.
Teifel, J., et al., "Highly Pipelined Asynchronous FPGAs," Proceedings of the 2004 ACM/SIGDA 12.sup.th International Symposium on Field Programmable Gate Arrays, Feb. 22-24, 2004, ACM, Monterey, CA. cited by other.
Tessier, R., et al., "Balancing Logic Utilization and Area Efficiency in FPGAs," Proceedings of the Roadmap to Reconfigurable Computing, 10.sup.th International Workshop on Field Programmable Logic and Applications, Aug. 27-30, 2000, pp. 535-544.cited by other.
Tom, M., et al., "Clustering of Large Designs for Channel-Width Constrained FPGAs," University of British Columbia, Department of Electrical and Computer Engineering, Jun. 2005, slides 1-39, Vancouver, British Columbia, Canada. cited by other.
Tom, M., et al., "Logic Block Clustering of Large Designs for Channel-Width Constrained FPGAs" DAC 2005, Jun. 13-17, 2005, pp. 726-731, ACM, Anaheim, CA. cited by other.
Tsu, W., et al., "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 69-78. cited by other.
Wawrzynek, J., "EECS150-Digital Design: Lecture 5--Field Programmable Gate Arrays (FPGAs)," Feb. 4, 2002, slides 1-20. cited by other.
Weaver, N., et al., "The SFRA: A Corner-Turn FPGA Architecture," FPGA '04, Feb. 22-24, 2004, ACM, Monterey, CA. cited by other.
Wegener, I., "The Complexity of Boolean Functions," Wiley-Teubner Series in Computer Science, 1987 Month N/A, John Wiley & Sons Ltd. and B.G. Teubner, Stuttgart, New York. cited by other.
Wilton, S.J.E., "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays," FPGA 97, Feb. 1997, pp. 10-16, ACM, Monterey, CA. cited by other.
XILINX, Inc., "Virtex-4 Family Overview," Advance Product Specification, Sep. 10, 2004, pp. 21-30, v1.1, Xilinx, Inc. cited by other.
Xing, S., et al., "FPGA Adders: Performance Evaluation and Optimal Design," IEEE Design & Test of Computers, Jan.-Mar. 1998, pp. 24-29, IEEE. cited by other.
Zilic, Z. et al., "Using BDDs to Design ULMs for FPGAs," Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays (FPGA '96), Feb. 11-13, 1996, pp. 1-10, Monterey, CA. cited by other.
Zuchowski, P.S., "A Hybrid ASIC and FPGA Architecture," 2002 Month N/A, IEEE. cited by other.
U.S. Appl. No. 12/729,227, filed Mar. 22, 2010, Schmit, Herman, et al. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/081,883, Jun. 13, 2007, Hutchings, Brad, et al., now issued U.S. Patent 7,298,169. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/926,100, Jun. 1, 2010, Hutchings, Brad, et al. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/081,850, Jun. 10, 2010, Hutchings, Brad. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/081,867, Oct. 16, 2007, Schmit, Herman, et al., now issued U.S. Patent 7,301,368. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/926,092, Jul. 2, 2009, Schmit, Herman, et al., now issued U.S. Patent 7,652,499. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/081,809, Jan. 27, 2006, Schmit, Herman, et al., now issued U.S. Patent 7,242,216. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/757,982, Mar. 3, 2009, Schmit, Herman, et al. now issued U.S. Patent 7,564,261. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/371,214, Apr. 15, 2010, Schmit, Herman, et al. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/371,352, Oct. 28, 2009, Schmit, Herman, et al., now issued U.S. Patent 7,694,083. cited by other.
Updated portions of prosecution history for U.S. Appl. No. 11/609,883, Nov. 13, 2008, Schmit, Herman, et al., now issued U.S. Patent 7,587,697. cited by other.
Final Office Action of U.S. Appl. No. 11/926,100, Oct. 8, 2009, (mailing date), Hutchings, Brad, et al. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/926,100, Dec. 31, 2008, (mailing date), Hutchings, Brad, et al. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/081,850, Nov. 3, 2009, (mailing date), Hutchings, Brad. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/081,850, Feb. 17, 2009, (mailing date), Hutchings, Brad. cited by other.
Notice of Allowance of U.S. Appl. No. 11/926,092, Aug. 28, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/926,092, Dec. 15, 2008, (mailing date), Schmit, Herman, et al. cited by other.
Notice of Allowance of U.S. Appl. No. 11/757,982, Mar. 11, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Final Office Action of U.S. Appl. No. 11/757,982, Oct. 10, 2008, (mailing date), Schmit, Herman, et al. cited by other.
Final Office Action of U.S. Appl. No. 11/371,214, Sep. 3, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/371,214, Mar. 16, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Mandal, C., et al., "Use of Multi-port Memories in Programmable Structures for Architectural Synthesis", Proceedings of 8.sup.th Annual IEEE International Innovative Systems in Silicon, Oct. 9-11, 1996, pp. 341-351. cited by other.
Ouaiss, Iyad., et al., "Hierarchical Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers", Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Mar. 13-16, 2001, pp. 650-657. cited by other.
Soviani, Cristian, et al., "Optimizing Sequential Cycles through Shannon Decomposition and Retiming", Design, Automation, and Test in Europe, Mar. 10, 2006, pp. 1085-1090. cited by other.
Non-Final Office Action of U.S. Appl. No. 11/371,214, Sep. 16, 2008, (mailing date), Schmit, Herman, et al. cited by other.
Notice of Allowance of U.S. Appl. No. 11/371,352, Nov. 16, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Final Office Action of U.S. Appl. No. 11/371,352, Apr. 28, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Notice of Allowance of U.S. Appl. No. 11/609,883, Jan. 23, 2009, (mailing date), Schmit, Herman, et al. cited by other.
Notice of Allowance of U.S. Appl. No. 11/609,883, Aug. 21, 2008, (mailing date), Schmit, Herman, et al. cited by other.









Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.
Claim: What is claimed is:

1. A computer-implemented method of implementing a user integrated circuit (IC) design in a physical IC that has a memory comprising a single physical port, said methodcomprising: mapping memory accesses in the user design to the memory by using a plurality of logical ports for the memory that has a particular port hierarchy with at least a first logical port that has a higher priority in the particular port hierarchythan a second logical port with a lower priority, wherein the plurality of logical ports for the memory are emulated in a user design clock cycle by accessing the single physical port of the memory a plurality of times in the user design clock cycle; and resolving conflicts resulting from mapping a first memory access and a second memory access in the user design to a particular user design clock cycle by assigning the first memory access to the higher-priority first logical port of the memory whileassigning the second memory access to the lower-priority second logical port of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping andresolving are performed by a design automation tool implemented on a computer.

2. The computer-implemented method of claim 1, wherein said first and second logical ports each access a same memory address.

3. The computer-implemented method of claim 2, wherein said accesses of the same memory address by said first and second logical ports comprise: said second logical port writing a first memory value to said same memory address; and said firstlogical port reading a second memory value from said same memory address, wherein said second memory value is a memory value that was stored in said same memory address prior to said second logical port writing to said same memory address.

4. The computer-implemented method of claim 2, wherein said accesses of the same memory address by said first and second logical ports comprise: said first logical port writing a first memory value to said same memory address; and said secondlogical port reading a second memory value from said same memory address, wherein said second memory value is equal to said first memory value.

5. The computer-implemented method of claim 1, wherein said memory accesses are mapped to a plurality of sequential accesses to said single physical memory port within the particular user design clock cycle.

6. The computer-implemented method of claim 1, wherein said IC comprises a plurality of reconfigurable circuits that reconfigure once per subcycle of the user design clock cycle and said memory is accessed once per subcycle through said singlephysical port.

7. The computer-implemented method of claim 1, wherein the first memory access is an access to the single physical port in a first subcycle of the particular user design clock cycle while the second memory access is an access to the singlephysical port in a second subcycle of the particular user design clock cycle that is after the first subcycle.

8. A computer-implemented method of implementing a user integrated circuit (IC) design in an IC that has a memory comprising a plurality of physical ports, said method comprising: mapping memory accesses in the user design to the memory byusing a plurality of logical ports for the memory that has a particular port hierarchy with at least a first logical port that has a higher priority in the particular port hierarchy than a second logical port with a lower priority, wherein said pluralityof logical ports for the memory are M logical ports that are emulated in a user design clock cycle by accessing N physical ports of the memory a plurality of times in the user design clock cycle, wherein M and N are integers greater than one and whereinM>N, wherein at least one of the N physical ports is accessed more than once in the user design clock cycle in order to emulate accesses by two or more of the M logical ports; and resolving conflicts resulting from mapping a first memory access and asecond memory access in the user design to a particular user design clock cycle by assigning the first memory access to the higher-priority first logical port of the memory while assigning the second memory access to the lower-priority second logicalport of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are implemented on a computer.

9. The computer-implemented method of claim 8, wherein a plurality of times in emulating the logical ports further comprises accessing each of a plurality of said N physical ports the user design clock cycle.

10. A computer-implemented method of accessing memory in an integrated circuit (IC), said method comprising: mapping memory accesses in a user design to a memory in the IC by using a plurality of ports for the memory, the plurality of portshaving a particular port hierarchy with at least a first port that has a higher priority in the port hierarchy than a second port with a lower priority, wherein the plurality of ports for the memory are a plurality of logical ports that are emulated in auser design clock cycle by accessing a single physical port of the memory a plurality of times in the user design clock cycle; and resolving conflicts resulting from mapping a first memory access in the user design to a particular user design clockcycle and a second memory access in the user design to the particular user design clock cycle by assigning the first memory access to the higher-priority first port of the memory while assigning the second memory access to the lower-priority second portof the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are implemented on a computer.

11. The computer-implemented method of claim 10, wherein said first and second memory ports each access a same memory address.

12. The computer-implemented method of claim 11, wherein said first and second memory accesses comprise: said second memory port writing a first memory value to said same memory address; and said first memory port reading a second memory valuefrom said same memory address, wherein said second memory value is a memory value that was stored in said same memory address prior to said second memory port writing to said same memory address.

13. The computer-implemented method of claim 11, wherein said first and second memory accesses comprise: said first memory port writing a first memory value to said same memory address; and said second memory port reading a second memory valuefrom said same memory address, wherein said second memory value is equal to said first memory value.

14. The computer-implemented method of claim 10, wherein said memory accesses are mapped to a plurality of sequential accesses to said single physical port within the user design clock cycle.

15. The computer-implemented method of claim 14, wherein said IC comprises a plurality of reconfigurable circuits that reconfigure once per subcycle of the user design clock cycle and said memory is accessed once per subcycle through saidsingle physical port.

16. A computer-implemented method of accessing memory in an integrated circuit (IC), said method comprising: mapping memory accesses in a user design to a memory in the IC by using a plurality of ports for the memory that have a particular porthierarchy with at least a first port that has a higher priority in the port hierarchy than a second port with a lower priority, wherein said plurality of ports for the memory are M logical ports that are emulated in a user design clock cycle by accessingN physical ports of the memory a plurality of times in the user design clock cycle, wherein M and N are integers greater than one and wherein M>N, wherein accesses to two or more of the M logical ports are emulated by two or more accesses to one ofthe N physical ports in the user design clock cycle; and resolving conflicts from mapping a first memory access in the user design to a particular user design clock cycle and a second memory access in the user design to the particular user design clockcycle by assigning the first memory access to the higher-priority first port of the memory while assigning the second memory access to the lower-priority second port of the memory, said assignments of the first and second memory accesses setting thefirst memory access to occur prior to the second memory access, wherein said mapping and resolving are implemented on a computer.

17. The computer-implemented method of claim 16, wherein the first memory access is an access to a particular physical port in a first subcycle, while the second memory access is an access to the particular physical port in a second subcyclethat is after the first subcycle in the particular user design clock cycle.

18. The computer implemented method of claim 16, wherein emulating the M logical ports further comprises accessing each of a plurality of said N physical ports a plurality of times in the particular user design clock cycle.
Description:
 
 
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