Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Lateral junction field effect transistor and method of manufacturing the same
7671388 Lateral junction field effect transistor and method of manufacturing the same
Patent Drawings:Drawing: 7671388-10    Drawing: 7671388-11    Drawing: 7671388-12    Drawing: 7671388-13    Drawing: 7671388-14    Drawing: 7671388-15    Drawing: 7671388-16    Drawing: 7671388-17    Drawing: 7671388-18    Drawing: 7671388-19    
« 1 2 3 4 5 »

(42 images)

Inventor: Fujikawa, et al.
Date Issued: March 2, 2010
Application: 12/552,212
Filed: September 1, 2009
Inventors: Fujikawa; Kazuhiro (Osaka, JP)
Harada; Shin (Osaka, JP)
Hirotsu; Kenichi (Osaka, JP)
Hatsukawa; Satoshi (Osaka, JP)
Hoshino; Takashi (Osaka, JP)
Matsunami; Hiroyuki (Kyoto, JP)
Kimoto; Tsunenobu (Kyoto, JP)
Assignee: Sumitomo Electric Industries, Ltd. (Osaka, JP)
Primary Examiner: Ha; Nathan W
Assistant Examiner:
Attorney Or Agent: Fish & Richardson P.C.
U.S. Class: 257/270
Field Of Search: 257/270; 257/271; 257/285; 257/E29.312
International Class: H01L 29/78
U.S Patent Documents:
Foreign Patent Documents: 0 053 854; 0 735 589; 2 355 584; 63131579; 02005533; 2001274414
Other References: RA. Muggli, "Double gate bipolar compatible n-channel junction FET," IBM Technical Disclousre Bulletin, vol. 24, No. 2, pp. 997-998 (Jul.1981). cited by other.
T. Fujihira, "Theory of semiconductor superjunction devices", Jpn. J. Appl. Phys. 36:6254-6262 (1997). cited by other.
N. Kaminski et al., "Punch-through behaviour of wide bandgap materials (with example in 6H-SiC) and its benefit to JFETS", Materials Science Forum (264-268):1073-1076 (1998). cited by other.









Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
Claim: The invention claimed is:

1. A lateral junction field effect transistor comprising: a first semiconductor layer located on a semiconductor substrate, and doped with impurities (p) of a firstconductivity type; a second semiconductor layer located on said first semiconductor layer, and doped with impurities (p) of the first conductivity type; a third semiconductor layer located on said first semiconductor layer, neighboring to said secondsemiconductor layer, and doped with impurities (n) of a second conductivity type; a fourth semiconductor layer located on said first semiconductor layer, neighboring to said third semiconductor layer, and doped with impurities (p) of the firstconductivity type; source/drain region layers arranged in said second, third and fourth semiconductor layers, spaced from each other by a predetermined distance, and doped with impurities (n) of the second conductivity type more heavily than said thirdsemiconductor layer; a first gate electrode layer arranged in said second semiconductor layer between said source/drain region layers, having a side surface on its one side extending on said third semiconductor layer, and doped with impurities (p) ofthe first conductivity type more heavily than said third semiconductor layer; and a second gate electrode layer of the first conductivity type arranged in said fourth semiconductor layer between said source/drain region layers, having a side surface onits one side extending on said third semiconductor layer, having substantially the same impurity concentration as said first gate electrode layer, and having the same potential as said first gate electrode layer.

2. The lateral junction field effect transistor according to claim 1, wherein said second, third and fourth semiconductor layers substantially have the same impurity concentration and the same layer thickness.

3. The lateral junction field effect transistor according to claim 1, wherein a distance between surfaces of said first and second gate electrode layers nearest to each other is smaller than double a distance of a depletion layer extended by adiffused potential in a junction between said third semiconductor layer and said first gate electrode layer.

4. A lateral junction field effect transistor comprising: a first semiconductor layer located on a semiconductor substrate, and doped with impurities (p) of a first conductivity type; a second semiconductor layer located on said firstsemiconductor layer, and doped with impurities (p) of the first conductivity type; a third semiconductor layer located on said first semiconductor layer, neighboring to said second semiconductor layer, and doped with impurities (n) of a secondconductivity type; a fourth semiconductor layer located on said first semiconductor layer, neighboring to said third semiconductor layer, and doped with impurities (p) of the first conductivity type; a fifth semiconductor layer located on said firstsemiconductor layer, neighboring to said fourth semiconductor layer, and doped with impurities (n) of the second conductivity type; a sixth semiconductor layer located on said first semiconductor layer, neighboring to said fifth semiconductor layer, anddoped with impurities (p) of the first conductivity type; source/drain region layers arranged in said second, third, fourth, fifth and sixth semiconductor layers, spaced from each other by a predetermined distance, and doped with impurities (n) of thesecond conductivity type more heavily than said third and fifth semiconductor layers; a first gate electrode layer arranged in said second semiconductor layer between said source/drain region layers, having a side surface on its one side extending onsaid third semiconductor layer, and doped with impurities (p) of the first conductivity type more heavily than said third semiconductor layer; a second gate electrode layer of the first conductivity type (p) arranged in said fourth semiconductor layerbetween said source/drain region layers, having side surfaces on its opposite sides extending on said third and fifth semiconductor layers, respectively, having substantially the same impurity concentration as said first gate electrode layer, and havingthe same potential as said first gate electrode layer; and a third gate electrode layer arranged in said sixth semiconductor layer between said source/drain region layers, having a side surface on its one side extending on said fifth semiconductorlayer, having substantially the same impurity concentration as said first gate electrode layer, and having the same potential as said first gate electrode layer.

5. The lateral junction field effect transistor according to claim 4, wherein said second, third, fourth, fifth and sixth semiconductor layers substantially have the same impurity concentration and the same layer thickness.

6. The lateral junction field effect transistor according to claim 4, wherein a distance between surfaces of said first and second gate electrode layers nearest to each other is smaller than double a distance of a depletion layer extended by adiffused potential in a junction between said third semiconductor layer and said first gate electrode layer, and a distance between surfaces of said second and third gate electrode layers nearest to each other is smaller than double a distance of adepletion layer extended by a diffused potential in a junction between said third semiconductor layer and said first gate electrode layer.

7. The lateral junction field effect transistor according to claim 4, wherein one or more unit transistor structure(s) being substantially the same as the structure having said fourth semiconductor layer, said fifth semiconductor layer and saidsecond gate electrode layer are arranged between said fifth and sixth semiconductor layers.
Description:
 
 
  Recently Added Patents
Touch-sensitive device and communication device
Scalable architecture for rank order filtering
Cryptographically generated addresses using backward key chain for secure route optimization in mobile internet protocol
Decontamination apparatus and method
Proton conducting electrolytes with cross-linked copolymer additives for use in fuel cells
Herbicide composition having improved effectiveness, method of preparation and use
Method for providing interactive site map
  Randomly Featured Patents
Window border generation in a bitmapped graphics workstation
Resin composition, thermoplastic resin laminate, and production methods thereof
Brassiere
Lithographic patterning for sub-90nm with a multi-layered carbon-based hardmask
Personal cooling or warming system using closed loop fluid flow
Derivatives from cervinomycin based antibiotics
Analgesic and tranquilizing benzoylpropyl-spiro[dihydrobenzofuran]piperidines and pyrrolidines
Method and machine for the production of hinged-lid packs for groups of cigarettes or the like
Vehicle seat apparatus having load detecting device
Mobile aircraft hangar