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Integrated circuit dielectric formation
6140222 Integrated circuit dielectric formation
Patent Drawings:Drawing: 6140222-3    
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Inventor: Bollinger, et al.
Date Issued: October 31, 2000
Application: 08/506,253
Filed: July 21, 1995
Inventors: Bollinger; Cheryl Anne (Kutztown, PA)
Fieber; Catherine Ann (Emmaus, PA)
Steiner; Kurt George (Bethlehem, PA)
Assignee: Lucent Technologies Inc. (Murray Hill, NJ)
Primary Examiner: Fourson; George
Assistant Examiner:
Attorney Or Agent: Francos; William S.Rehberg; John T.
U.S. Class: 257/E23.167; 438/623; 438/624; 438/626; 438/627; 438/783
Field Of Search: ; ; 257/760; 257/637; 257/642; 257/644; 437/235; 437/236; 437/238; 437/240; 437/978; 148/DIG.81; 148/DIG.118; 438/623; 438/624; 438/626; 438/627; 438/783; 438/FOR; 355/; 438/FOR; 400/
International Class:
U.S Patent Documents: 4795722; 4845054; 4952524; 4999317; 5317192
Foreign Patent Documents: 0141496; O 249 173; 0488546; 5555538; 5632732; 5728335; 199243; 1135044; 2144940; 3-36727; 3036727; 3194932; 4076919; 2251722; WO87/02828
Other References: Ghandhi, S., "V.L.S.I. Fabrication Priciples: Silicon and Gallium Arsenide", John Wiley and Sons, pp. 517-519, 1983..
Ghandhi, S., VLSI Fabrication Principles: Silicon & Gallium Arsenide, 1983, John Wiley & Sons, pp. 424-426..
Wolf, S., Silicon Processing for the VLSI Era : vol. 2 Process Integration, Lattice Press, 1990, pp. 194-195, 198-199, 229-230, 233-235..
Wolf, S., Silicon Processing for the VLSI Era: vol. 2 Process Integration, Lattice Press 1990, p. 236..
"In Situ Planarization of Dielectric Surfaces Using Boron Oxide," 1989 IEEE, VMIC Conference, Jun. 12-13, 1989, J. Marks et al., pp. 89-95..
"An Improved Interlevel Dielectric Process for Submicron Double-Level Metal Products," IEEE, VMIC Conference, Jun. 12-13, 1989, S.L.Pennington et al., pp. 355-359..
O. Spindler, B. Neureither--In Situ Planarization of Intermetal Dielectrics: Process Steps, Degree of Planarization and Film Properties--Thin Solid Films, 175 (1989) Aug., No. 1, Lausanne, CH, pp. 67-72..
P.K. Sinha and J.A. Smythe--Moisture and Phosphorous Sensitivity of Sacrificial Spin-On-Glass Dielectric Planarization Process--Journal of the Electrochemical Society, 138 (1991) Mar., No. 3, Manchester, NH, US--pp. 854-856..
J. Kalpathy Cramer and S.P. Murarka--Sodium Passivation Dependence on Phosphorus Concentration in Tetraethylorthosilicate Plasma-enhanced Chemical Vapor Deposited Phosphosilicate Glasses--J. Appl. Phys. 73 (5), Mar. 1, 1993--pp. 2458-2461..

Abstract: An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped dielectric. The doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.
Claim: What is claimed is:

1. A method of integrated circuit fabrication, comprising:

forming a first dielectric over runners which overlie a substrate, said first dielectric containing more than four percent and up to six percent phosphorous by weight;

forming a second dielectric layer;

etching back said second dielectric layer to expose at least one portion of said first dielectric layer; said runners remaining covered; and

forming a third dielectric layer over said second dielectric layer containing more than four percent and up to six percent phosphorous by weight.

2. A method as recited in claim 1, wherein said first and said third dielectric layers are silicon-dioxide.

3. A method as recited in claim 1, wherein said second dielectric layer is spin-on-glass.

4. A method as recited in claim 2, wherein said first and third dielectric layers have a thickness in the range of 4000-7000 .ANG..

This invention relates to integrated circuits and methods for their manufacture. More particularly, it relates to dielectrics employed in integrated circuits to provide isolation between electrical conductors.


The use of spin-on glasses, including polysiloxanes, polysilicates and silsesquioxanes, is becoming increasingly prevalent in integrated circuit manufacture. Spin-on glasses are easily applied, and may be conveniently planarized with anoptimized etch chemistry. Further, spin-on glasses fill small gaps better than many other dielectrics. However, the use of spin-on glass presents a variety of problems in integrated circuit manufacture.


Applicants have discovered that dielectrics which include spin-on glass that is partially etched back are vulnerable to mobile alkaline ion contamination. Consequently, applicants' process or semiconductor integrated circuit fabrication includesforming a first dielectric layer over a substrate; forming a second layer from the group consisting of spin-on glass and ozone TEOS; performing a process step which tends to introduce mobile ion contamination; and forming a third dielectric layer overthe etched second layer. Both the first and third dielectric layers have phosphorous doping. The doped first and third layers help prevent mobile alkaline ion contamination of the underlying substrate. Illustratively, the process which tends tointroduce mobile ion contamination may be an etching back of the second layer.


The FIGURE is a cross-sectional view of a partially fabricated integrated circuit which is helpful in understanding the present invention.


In the FIGURE, reference numeral 11 designates a substrate which may be silicon or silicon dioxide. In general, the term substrate refers to any material having 30 a surface upon which subsequent materials, layers, or structures may be formed. Reference numeral 11 may also represent a field oxide, a thinox region, or alternating field oxide and thinox regions (although not explicitly illustrated as such). Reference numerals 13, 15, and 17 designate topographical features upon substrate 11. Reference numerals 13, 15, and 17 may, for example, be MOS transistor gates or runners. Reference numeral 19 designates a dielectric which surrounds and covers features 13, 15, and 17. Reference numerals 21 and 23 designate topographical features suchas conductive runners which may, typically, be made from aluminum, an aluminum alloy, or polysilicon or another conductive material.

Reference numerals 25, 27, and 29, taken together, designate a triple-layer dielectric which serves to encapsulate runners 21 and 23.

Reference numeral 25 is, illustratively, a silicon-dioxide-type dielectric having between 2% and 6% phosphorous by weight. Illustratively, dielectric 25 may be made from TEOS, or silane precursors. Trimethylphosphite (TMP) or phosphine(PH.sub.3) may be used as phosphorous dopant sources in the formation of dielectric 25. Dielectric 25 may also be a low temperature oxide. Typically, the thickness of dielectric 25 is 4000-7000 .ANG..

Dielectric 27 is a spin-on glass material, either a polysiloxane, polysilicate, or a silsesquioxane or ozone TEOS. Dielectric 27 may be applied by conventional techniques and then etched back to form a relatively planar upper surface 28. Uppersurface 28 is frequently approximately level or even with the upper surface 26 of layer 25. An etchback step is necessary not only for planarization purposes, but also to remove the spin-on glass from the vicinity of dielectric surfaces such as 26through which vias may be later opened. (If vias are opened through spin-on glass, moisture may subsequently enter the via and degrade the spin-on glass.) During the plasma etchback, sodium contamination of the upper surfaces 28 of dielectric 27 andupper surface 26 of dielectric 25 frequently occurs. In conventional processing, sodium contamination from plasma etching is frequently removed from the upper oxide surfaces by performing a short wet cleaning procedure in solutions such as 8:1 ethyleneglycol:buffered hydrofluoric acid, or 100:1 water and hydrofluoric acid. However, typical wet cleaning procedures (which may be quite suitable for silane or TEOS-based dielectrics) tend to rapidly attack spin-on glass and thus tend to destroy thealready-achieved planarization.

Consequently, after spin-on glass 27 is applied and etched back, the wet clean process mentioned above is preferably not performed. Instead, dielectric layer 29 is immediately formed on top of spin-on glass 27. Dielectric 29 may be similar todielectric 25. That is, dielectric 25 contains between 2% and 6% phosphorous by weight and may be made from TEOS, silane, or may be a low temperature oxide.

Typically, the thickness of dielectric 29 is 4000-7000 .ANG..

Illustratively, dielectrics 29 and 25 may be formed in an Applied Materials Precision 5000 CVD system. A process chemistry utilizing TEOS, oxygen, and TMP as a phosphorous source may be employed. Wafer temperature is maintained at C., well below the critical temperature of C. for aluminum metalization. The plasma CVD reactor is operated at 2.0 to 9.0 Torr, with 200-1000 watts of RF power at 13.56 MHz.

Applicants have found that doping either the top or the bottom layer (i.e., layer 29 or 25) alone is not effective in preventing alkaline ion motion under the influence of electric fields. Both layers 29 and 25 are preferably doped. Thephosphorous in layers 29 and 25, it is hypothesized, ties up or getters the mobile alkaline ions, thus preventing degradation of the ultimately formed integrated circuits.

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