| Patent Number |
Title Of Patent |
Date Issued |
| RE36952 |
One time programmable fully-testable programmable logic device with zero power and anti-fuse cel |
November 14, 2000 |
| There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the |
| RE36821 |
Wordline driver circuit having a directly gated pull-down device |
August 15, 2000 |
| The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The drivin |
| RE35825 |
Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having |
June 16, 1998 |
| A method for maintaining optimum biasing voltage and standby current levels in a dynamic random access memory array, in which row-to-column shorts have been repaired by redirecting the addresses of shorted rows and columns to spare rows and columns. The method partly consists of placing |
| RE35750 |
Wordline driver circuit having an automatic precharge circuit |
March 24, 1998 |
| The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of th |
| 6597054 |
Reduced pitch laser redundancy fuse bank structure |
July 22, 2003 |
| A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added |
| 6529426 |
Circuit and method for varying a period of an internal control signal during a test mode |
March 4, 2003 |
| The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control signal to stress the DRAM during a |
| 6208568 |
Circuit for cancelling and replacing redundant elements |
March 27, 2001 |
| In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynam |
| 6201740 |
Cache memories using DRAM cells with high-speed data path |
March 13, 2001 |
| A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array |
| 6104645 |
High speed global row redundancy system |
August 15, 2000 |
| A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming ad |
| 6097647 |
Efficient method for obtaining usable parts from a partially good memory integrated circuit |
August 1, 2000 |
| An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inope |
| 6044433 |
DRAM cache |
March 28, 2000 |
| A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array |
| 5999480 |
Dynamic random-access memory having a hierarchical data path |
December 7, 1999 |
| A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit |
| 5991214 |
Circuit and method for varying a period of an internal control signal during a test mode |
November 23, 1999 |
| The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control signal to stress the DRAM during a |
| 5970008 |
Efficient method for obtaining usable parts from a partially good memory integrated circuit |
October 19, 1999 |
| An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inope |
| 5953739 |
Synchronous DRAM cache using write signal to determine single or burst write |
September 14, 1999 |
| A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array |
| 5933372 |
Data path for high speed high bandwidth DRAM |
August 3, 1999 |
| A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array |
| 5912579 |
Circuit for cancelling and replacing redundant elements |
June 15, 1999 |
| In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynam |
| 5905295 |
Reduced pitch laser redundancy fuse bank structure |
May 18, 1999 |
| A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added |
| 5901105 |
Dynamic random access memory having decoding circuitry for partial memory blocks |
May 4, 1999 |
| A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit |
| 5850368 |
Burst EDO memory address counter |
December 15, 1998 |
| A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combinati |
| 5844833 |
DRAM with open digit lines and array edge reference sensing |
December 1, 1998 |
| A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a refe |
| 5838620 |
Circuit for cancelling and replacing redundant elements |
November 17, 1998 |
| In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynam |
| 5831918 |
Circuit and method for varying a period of an internal control signal during a test mode |
November 3, 1998 |
| The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control signal to stress the DRAM during a |
| 5812488 |
Synchronous burst extended data out dram |
September 22, 1998 |
| An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates addi |
| 5802010 |
Burst EDO memory device |
September 1, 1998 |
| An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address |
| 5801996 |
Data path for high speed high bandwidth DRAM |
September 1, 1998 |
| A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array |
| 5774412 |
Local word line phase driver |
June 30, 1998 |
| A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage whic |
| 5761145 |
Efficient method for obtaining usable parts from a partially good memory integrated circuit |
June 2, 1998 |
| An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inope |
| 5747869 |
Reduced pitch laser redundancy fuse bank structure |
May 5, 1998 |
| A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added |
| 5726931 |
DRAM with open digit lines and array edge reference sensing |
March 10, 1998 |
| A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a refe |
| 5696732 |
Burst EDO memory device |
December 9, 1997 |
| An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address |
| 5677884 |
Circuit for cancelling and replacing redundant elements |
October 14, 1997 |
| In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynam |
| 5675549 |
Burst EDO memory device address counter |
October 7, 1997 |
| A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combinati |
| 5668773 |
Synchronous burst extended data out DRAM |
September 16, 1997 |
| An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates addi |
| 5666323 |
Synchronous NAND DRAM architecture |
September 9, 1997 |
| An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual b |
| 5661695 |
Burst EDO memory device |
August 26, 1997 |
| An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address |
| 5636172 |
Reduced pitch laser redundancy fuse bank structure |
June 3, 1997 |
| A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added |
| 5608668 |
Dram wtih open digit lines and array edge reference sensing |
March 4, 1997 |
| A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a refe |
| 5586080 |
Local word line phase driver |
December 17, 1996 |
| A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage whic |
| 5552739 |
Integrated circuit power supply having piecewise linearity |
September 3, 1996 |
| A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an |
| 5544124 |
Optimization circuitry and control for a synchronous memory device with programmable latency per |
August 6, 1996 |
| A method and apparatus for optimizing the speed path of a memory access operation in a synchronous depending upon the present latency period for the synchronous DRAM. The improved memory device compensates the time between row address latching and column address latching (tRCD) by de |
| 5528539 |
High speed global row redundancy system |
June 18, 1996 |
| A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming ad |
| 5526320 |
Burst EDO memory device |
June 11, 1996 |
| An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address |
| 5488583 |
Memory integrated circuits having on-chip topology logic driver, and methods for testing and pro |
January 30, 1996 |
| A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circu |
| 5465232 |
Sense circuit for tracking charge transfer through access transistors in a dynamic random access |
November 7, 1995 |
| A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs a model access transistor to |
| 5384500 |
Programmable logic device macrocell with an exclusive feedback and an exclusive external input l |
January 24, 1995 |
| A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O |
| 5325331 |
Improved device for sensing information store in a dynamic memory |
June 28, 1994 |
| To enhance the speed at which dynamic random access memories are refreshed, each sensing amplifier is provided with a clamping transistor. The clamping transistor is connected to a preselected voltage source. The clamping transistor prevents the voltage on the low-going bit line from |
| 5315177 |
One time programmable fully-testable programmable logic device with zero power and anti-fuse cel |
May 24, 1994 |
| There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the |
| 5311481 |
Wordline driver circuit having a directly gated pull-down device |
May 10, 1994 |
| The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The drivin |
| 5311478 |
Integrated circuit memory with asymmetric row access topology |
May 10, 1994 |
| A DRAM or VRAM integrated circuit memory of the divided bit line design includes a first bit line pair divided into a first pair of bit line halves and a second pair of bit line halves, and second bit line pair divided into a third pair of bit line halves and a fourth pair of bit line |
