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Paul Zagar Patents |
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Inventor: Zagar; Paul
Address: Boise, ID
No. of patents: 2
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 5587671 |
Semiconductor device having an output buffer which reduces signal degradation due to leakage of |
December 24, 1996 |
| To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump to continuously boost the input of an NMOS output circuit so long as the output circuit is providing a logic high output signal. The NMOS output circuit ha |
| 5513148 |
Synchronous NAND DRAM architecture |
April 30, 1996 |
| An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual b |
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