| Patent Number |
Title Of Patent |
Date Issued |
| 7462549 |
Shallow trench isolation process and structure with minimized strained silicon consumption |
December 9, 2008 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a co |
| 7422961 |
Method of forming isolation regions for integrated circuits |
September 9, 2008 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low |
| 7417250 |
Strained-silicon device with different silicon thicknesses |
August 26, 2008 |
| A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, |
| 7351638 |
Scanning laser thermal annealing |
April 1, 2008 |
| A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the mo |
| 7312125 |
Fully depleted strained semiconductor on insulator transistor and method of making the same |
December 25, 2007 |
| An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide la |
| 7306997 |
Strained fully depleted silicon on insulator semiconductor device and manufacturing method there |
December 11, 2007 |
| A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around t |
| 7238588 |
Silicon buffered shallow trench isolation |
July 3, 2007 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is formed in a selecti |
| 7221025 |
Semiconductor on insulator substrate and devices formed therefrom |
May 22, 2007 |
| A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diam |
| 7217608 |
CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
May 15, 2007 |
| Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility |
| 7211489 |
Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anne |
May 1, 2007 |
| The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel |
| 7176531 |
CMOS gates formed by integrating metals having different work functions and having a high-k gate |
February 13, 2007 |
| According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositin |
| 7170084 |
Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and m |
January 30, 2007 |
| An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source |
| 7138302 |
Method of fabricating an integrated circuit channel region |
November 21, 2006 |
| An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the |
| 7105421 |
Silicon on insulator field effect transistor with heterojunction gate |
September 12, 2006 |
| A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and |
| 7091097 |
End-of-range defect minimization in semiconductor device |
August 15, 2006 |
| A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-c |
| 7078299 |
Formation of finFET using a sidewall epitaxial layer |
July 18, 2006 |
| A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming |
| 7071065 |
Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabric |
July 4, 2006 |
| A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions ar |
| 7071051 |
Method for forming a thin, high quality buffer layer in a field effect transistor and related st |
July 4, 2006 |
| According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride prec |
| 7033893 |
CMOS devices with balanced drive currents based on SiGe |
April 25, 2006 |
| CMOS devices with balanced drive currents are formed with a PMOS transistor based on SiGe and a deposited high-k gate dielectric. Embodiments including forming a composite substrate comprising a layer of strained Si on a layer of SiGe, forming isolation regions defining a PMOS region |
| 7033869 |
Strained silicon semiconductor on insulator MOSFET |
April 25, 2006 |
| An SOI substrate comprises a layer of strained silicon sandwiched between a dielectric layer and a layer of strained silicon. The substrate may be used to form a strained silicon SOI MOSFET having a gate electrode that extends through the silicon germanium layer to a channel region forme |
| 7015078 |
Silicon on insulator substrate having improved thermal conductivity and method of its formation |
March 21, 2006 |
| A silicon on insulator (SOI) substrate includes a layer of silicon carbide beneath an insulating layer on which semiconductor devices are formed. The silicon carbide layer has a high thermal conductivity and provides beneficial dissipation of thermal energy generated by the devices. The |
| 7012007 |
Strained silicon MOSFET having improved thermal conductivity and method for its fabrication |
March 14, 2006 |
| A strained silicon MOSFET employs a high thermal conductivity insulating material in the trench isolations to dissipate thermal energy generated in the MOSFET and to avoid self-heating caused by the poor thermal conductivity of an underlying silicon germanium layer. The high thermal |
| 7005302 |
Semiconductor on insulator substrate and devices formed therefrom |
February 28, 2006 |
| A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diam |
| 6984569 |
Shallow trench isolation (STI) region with high-K liner and method of formation |
January 10, 2006 |
| A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K mater |
| 6979635 |
Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation |
December 27, 2005 |
| Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon |
| 6962857 |
Shallow trench isolation process using oxide deposition and anneal |
November 8, 2005 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which redu |
| 6955969 |
Method of growing as a channel region to reduce source/drain junction capacitance |
October 18, 2005 |
| A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, deposit |
| 6951220 |
Method of decontaminating equipment |
October 4, 2005 |
| A method of performing decontamination of a chamber for use in an IC fabrication system includes providing wet oxygen or a mixture comprising hydrochloric gas and oxygen in the chamber and raising the temperature in the chamber from a first lower temperature to a second higher temperatur |
| 6943087 |
Semiconductor on insulator MOSFET having strained silicon channel |
September 13, 2005 |
| Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the du |
| 6936516 |
Replacement gate strained silicon finFET process |
August 30, 2005 |
| An exemplary embodiment relates to a method of FinFET formation. The method can include providing a sacrificial fin structure, removing the sacrificial fin structure, and providing a strained silicon layer at the location of the removed sacrificial gate structure. The FinFET can include |
| 6936506 |
Strained-silicon devices with different silicon thicknesses |
August 30, 2005 |
| A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, |
| 6929992 |
Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold v |
August 16, 2005 |
| The threshold voltage shift exhibited by strained silicon NMOS devices is compensated with respect to the threshold voltages of PMOS devices formed on the same substrate by increasing the work function of the NMOS gates. The NMOS gate work function exceeds the PMOS gate work function so |
| 6924182 |
Strained silicon MOSFET having reduced leakage and method of its formation |
August 2, 2005 |
| The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantatio |
| 6921709 |
Front side seal to prevent germanium outgassing |
July 26, 2005 |
| A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping throug |
| 6905923 |
Offset spacer process for forming N-type transistors |
June 14, 2005 |
| A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion |
| 6902991 |
Semiconductor device having a thick strained silicon layer and method of its formation |
June 7, 2005 |
| A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This |
| 6902977 |
Method for forming polysilicon gate on high-k dielectric and related structure |
June 7, 2005 |
| According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a high-k dielectric layer over the substrate. The high-k dielectric layer may be, for example, hafnium oxide or zirconium oxide. The method further comprises f |
| 6902966 |
Low-temperature post-dopant activation process |
June 7, 2005 |
| A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants w |
| 6900143 |
Strained silicon MOSFETs having improved thermal dissipation |
May 31, 2005 |
| The thermal conductivity of strained silicon MOSFETs and strained silicon SOI MOSFETs is improved by providing a silicon germanium carbide thermal dissipation layer beneath a silicon germanium layer on which strained silicon is grown. The silicon germanium carbide thermal dissipation lay |
| 6897122 |
Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolati |
May 24, 2005 |
| The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relax |
| 6893929 |
Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends |
May 17, 2005 |
| The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type o |
| 6878592 |
Selective epitaxy to improve silicidation |
April 12, 2005 |
| A transistor architecture utilizes a raised source and drain region to reduce the adverse affects of germanium on silicide regions. Epitaxial growth can form a silicide region above the source and drain. The protocol can utilize any number of silicidation processes. The protocol allows |
| 6872613 |
Method for integrating metals having different work functions to form CMOS gates having a high-k |
March 29, 2005 |
| According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositin |
| 6867428 |
Strained silicon NMOS having silicon source/drain extensions and method for its fabrication |
March 15, 2005 |
| An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are impla |
| 6867080 |
Polysilicon tilting to prevent geometry effects during laser thermal annealing |
March 15, 2005 |
| A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to "fill in" the spaces between |
| 6858503 |
Depletion to avoid cross contamination |
February 22, 2005 |
| A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabricat |
| 6855982 |
Self aligned double gate transistor having a strained channel region and process therefor |
February 15, 2005 |
| A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germ |
| 6852600 |
Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
February 8, 2005 |
| A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon geranium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and th |
| 6849527 |
Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and meth |
February 1, 2005 |
| The mobility enhancement of a strained silicon layer is augmented through incorporation of carbon into a strained silicon lattice to which strain is also imparted by an underlying silicon germanium layer. The presence of the relatively small carbon atoms effectively increases the spacing |
| 6825115 |
Post silicide laser thermal annealing to avoid dopant deactivation |
November 30, 2004 |
| Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming |
