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William S. F. Wu Patents |
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Inventor: Wu; William S. F.
Address: Cupertino, CA
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6112016 |
Method and apparatus for sharing a signal line between agents |
August 29, 2000 |
| Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute |
| 5822767 |
Method and apparartus for sharing a signal line between agents |
October 13, 1998 |
| Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute |
| 5651137 |
Scalable cache attributes for an input/output bus |
July 22, 1997 |
| Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute |
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