| Patent Number |
Title Of Patent |
Date Issued |
| 7414280 |
Systems and methods for memory structure comprising embedded flash memory |
August 19, 2008 |
| A memory structure that combines multiple embedded flash memory. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. In one aspect, the flash memory cells are stacked on top of the flash memory cells and the flash memory cells share |
| 7411836 |
Method of operating non-volatile memory |
August 12, 2008 |
| A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain reg |
| 7372732 |
Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell |
May 13, 2008 |
| A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels corresponds to a different binary state and has a voltage threshold distribution. A const |
| 7342264 |
Memory cell and method for manufacturing the same |
March 11, 2008 |
| The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin |
| 7292478 |
Non-volatile memory including charge-trapping layer, and operation and fabrication of the same |
November 6, 2007 |
| A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the |
| 7266014 |
Method of operating non-volatile memory device |
September 4, 2007 |
| A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a |
| 7251167 |
Method for programming multi-level nitride read-only memory cells |
July 31, 2007 |
| A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low V.sub.t value. A data region that is to be programmed to a highest V.sub.t value is programmed first. Remaining data regions in the n |
| 7242052 |
Non-volatile memory |
July 10, 2007 |
| A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked st |
| 7218554 |
Method of refreshing charge-trapping non-volatile memory using band-to-band tunneling hot hole ( |
May 15, 2007 |
| A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple write/erase cycles causing hard-to-erase electrons in the charge-trapping layer, to eliminate the |
| 7209390 |
Operation scheme for spectrum shift in charge trapping non-volatile memory |
April 24, 2007 |
| A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distri |
| 7209385 |
Array structure for assisted-charge memory devices |
April 24, 2007 |
| An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The |
| 7206227 |
Architecture for assisted-charge memory array |
April 17, 2007 |
| An Assisted Charge (AC) Memory cell includes a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The |
| 7206225 |
Method of dynamically controlling program verify levels in multilevel memory cells |
April 17, 2007 |
| Pre-program verify levels for a multilevel read-only memory cell are generated dynamically. A determination takes into account a program verify level, an over-program budget, and a second-bit effect budget to generate pre-program verify levels. The generated pre-program verify levels |
| 7190614 |
Operation scheme for programming charge trapping non-volatile memory |
March 13, 2007 |
| A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage to the control ga |
| 7151692 |
Operation scheme for programming charge trapping non-volatile memory |
December 19, 2006 |
| A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage to the control ga |
| 7145809 |
Method for programming multi-level cell |
December 5, 2006 |
| A method for programming a multi-level cell (MLC) is disclosed. First, a memory cell with a first storage position and a second storage position is provided. An erasing step is performed to increase the threshold voltages of the storage positions. Then, a judging step is preformed to |
| 7139200 |
Method of identifying logical information in a programming and erasing cell by on-side reading s |
November 21, 2006 |
| A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by in |
| 7085168 |
Programming method for controlling memory threshold voltage distribution |
August 1, 2006 |
| A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of the memory cells to be programmed, a programming voltage pulse is given to the first sides o |
| 7085165 |
Method and apparatus for reducing read disturb in non-volatile memory |
August 1, 2006 |
| A memory cell with a charge-trapping structure stores multiple bits. A biasing arrangement is applied to one part of the charge-trapping structure of the memory cell to store a high threshold state, and a biasing arrangement is applied to another part of the charge-trapping structure |
| 7054192 |
Method of controlling threshold voltage of NROM cell |
May 30, 2006 |
| A method of two-sided asymmetric programming with a one-sided read for a Nitride Read Only Memory (NROM) cell with different quantity of stored charges uses the different interaction of the two bits to control the operation window of the threshold voltage. Due to the increase of the |
| 7038928 |
Method of determining optimal voltages for operating two-side non-volatile memory and the operat |
May 2, 2006 |
| A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I.sub.1-Vg curve of the first side and an I.sub.2-Vg curve of the second side |
| 6952038 |
3D polysilicon ROM and method of fabrication thereof |
October 4, 2005 |
| A 3D polysilicon ROM including an isolated SiO.sub.2 layer on a silicon substrate, and an N+ polysilicon layer on the isolated SiO.sub.2 layer. The N+ polysilicon layer is further defined by a plurality of parallel, separate word lines. A first oxide layer fills the space between the wor |
| 6937511 |
Circuit and method for programming charge storage memory cells |
August 30, 2005 |
| A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash, having a source and a drain in a substrate, a charge storage element and a control gate. The method includes applying source voltage, inducing a body effect that |
| 6903410 |
Electrically erasable programmable read only memory cell and programming method thereof |
June 7, 2005 |
| An electrically erasable programmable read only memory cell has a stacking layer, a gate conductive layer, a first source/drain region, a second source/drain region, a first pocket implant doping region, and a second pocket implant doping region. The stacking layer is disposed over a |
| 6890819 |
Methods for forming PN junction, one-time programmable read-only memory and fabricating processe |
May 10, 2005 |
| A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous sil |
| 5344139 |
Racket shaft mounting device |
September 6, 1994 |
| A racket shaft mounting device includes a head frame to hold a network of catgut, and a tubular shaft having a front end connected to the head frame by a connecting device and a rear end terminated to a hand grip, wherein the head frame has two opposite ends fitted one into the other; th |
| 5322280 |
Racket handle |
June 21, 1994 |
| A racket handle is provided which includes a handle member and a rod member forming a lower section of the racket frame. The handle member includes an outer pipe member and an inner pipe member defining a longitudinally extending closed annulus. The rod member is insertable within a bore |
| 5312115 |
Racket |
May 17, 1994 |
| A racket including a head and a handle joined by a racket throat, the head consisting of a network of catgut stretched in an oval open frame, and at least one protective covering covered on the oval open frame, each protective covering having pairs of opposite string holes arranged along |
| 5310180 |
Racket frame |
May 10, 1994 |
| A racket frame which includes an oval frame connected to a handle through a throat for hanging a network of catgut therein. The oval frame includes at least one groove around an endless inner wall thereof to hold at least one catcut mounting frame. Each catgut mounting frame has a plural |
