| Patent Number |
Title Of Patent |
Date Issued |
| 7417250 |
Strained-silicon device with different silicon thicknesses |
August 26, 2008 |
| A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, |
| 7335568 |
Method of forming doped regions in the bulk substrate of an SOI substrate to control the operati |
February 26, 2008 |
| In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate |
| 7253045 |
Selective P-channel V.sub.T adjustment in SiGe system for leakage optimization |
August 7, 2007 |
| A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to about 2.2. A semico |
| 7180136 |
Biased, triple-well fully depleted SOI structure |
February 20, 2007 |
| In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the bulk substrate being doped with a first type of dopant material and a first well formed in the |
| 7129142 |
Method of forming doped regions in the bulk substrate of an SOI substrate to control the operati |
October 31, 2006 |
| In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate |
| 6979878 |
Isolation structure having implanted silicon atoms at the top corner of the isolation trench fil |
December 27, 2005 |
| A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of |
| 6936506 |
Strained-silicon devices with different silicon thicknesses |
August 30, 2005 |
| A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, |
| 6919236 |
Biased, triple-well fully depleted SOI structure, and various methods of making and operating sa |
July 19, 2005 |
| In one example, a method of forming a transistor above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material is disclosed. The method comprises performing a first i |
| 6884702 |
Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in |
April 26, 2005 |
| In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric reg |
| 6876037 |
Fully-depleted SOI device |
April 5, 2005 |
| The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the d |
| 6822260 |
Linewidth measurement structure with embedded scatterometry structure |
November 23, 2004 |
| A method of manufacturing a semiconductor device includes depositing a layer over a substrate and etching the layer to form a grating structure, a cross bridge test structure and a line width measurement structure. The grating structure includes a plurality of parallel lines and one of t |
| 6812506 |
Polysilicon linewidth measurement structure with embedded transistor |
November 2, 2004 |
| A semiconductor device includes a grating structure having a plurality of parallel lines, and at least one of the multiple parallel lines is a gate electrode line of a transistor, which includes source/drain regions proximate to the gate electrode line, and vias extending to the gate |
| 6801096 |
Ring oscillator with embedded scatterometry grate array |
October 5, 2004 |
| A MOS ring oscillator includes a number of serially connected inverter stages with each stage comprising a MOS transistor pair. At least one of the transistors also comprises a scatterometry grate array, which is used during manufacturing of the ring oscillator to obtain scatterometry |
| 6780686 |
Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regi |
August 24, 2004 |
| The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk s |
| 6764908 |
Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized |
July 20, 2004 |
| A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the t |
| 6737332 |
Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making |
May 18, 2004 |
| The present invention is generally directed to a semiconductor device formed over a multiple thickness buried oxide layer, and various methods of making same. In one illustrative embodiment, the device comprises a bulk substrate, a multiple thickness buried oxide layer formed above the |
| 6727534 |
Electrically programmed MOS transistor source/drain series resistance |
April 27, 2004 |
| High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positio |
| 6727136 |
Formation of ultra-shallow depth source/drain extensions for MOS transistors |
April 27, 2004 |
| A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semicon |
| 6707106 |
Semiconductor device with tensile strain silicon introduced by compressive material in a buried |
March 16, 2004 |
| A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material is formed on a SOI semiconductor substrate to induce stra |
| 6689671 |
Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semico |
February 10, 2004 |
| A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain; (b) forming a device structure in the semicon |
| 6661057 |
Tri-level segmented control transistor and fabrication method |
December 9, 2003 |
| A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. Afte |
| 6589847 |
Tilted counter-doped implant to sharpen halo profile |
July 8, 2003 |
| The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and |
| 6580122 |
Transistor device having an enhanced width dimension and a method of making same |
June 17, 2003 |
| The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining |
| 6566696 |
Self-aligned VT implant |
May 20, 2003 |
| Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has |
| 6552776 |
Photolithographic system including light filter that compensates for lens error |
April 22, 2003 |
| A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error |
| 6433400 |
Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolatio |
August 13, 2002 |
| A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of |
| 6417539 |
High density memory cell assembly and methods |
July 9, 2002 |
| A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielect |
| 6410409 |
Implanted barrier layer for retarding upward diffusion of substrate dopant |
June 25, 2002 |
| Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of t |
| 6406964 |
Method of controlling junction recesses in a semiconductor device |
June 18, 2002 |
| The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by |
| 6380055 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer |
April 30, 2002 |
| A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilico |
| 6372588 |
Method of making an IGFET using solid phase diffusion to dope the gate, source and drain |
April 16, 2002 |
| A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device |
| 6372587 |
Angled halo implant tailoring using implant mask |
April 16, 2002 |
| A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask |
| 6346426 |
Method and apparatus for characterizing semiconductor device performance variations based on ind |
February 12, 2002 |
| A method for characterizing semiconductor device performance variations includes processing a wafer in a processing line to form a feature on the wafer; measuring a physical critical dimension of the feature in a first metrology tool to generate a first critical dimension measurement; |
| 6323519 |
Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabri |
November 27, 2001 |
| A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. A conformal oxide having thickness between about 1 |
| 6316302 |
Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PM |
November 13, 2001 |
| A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate |
| 6300205 |
Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo |
October 9, 2001 |
| One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first |
| 6274415 |
Self-aligned Vt implant |
August 14, 2001 |
| Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has |
| 6261936 |
Poly gate CD passivation for metrology control |
July 17, 2001 |
| Various methods of fabricating gate structures, such as gates and gate stacks are provided. In one aspect, a method of fabricating a gate electrode on a substrate is provided that includes depositing a polycrystalline silicon film on the substrate and etching the polycrystalline film |
| 6259142 |
Multiple split gate semiconductor device and fabrication method |
July 10, 2001 |
| A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another |
| 6258680 |
Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
July 10, 2001 |
| A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers t |
| 6258646 |
CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS |
July 10, 2001 |
| A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher ac |
| 6245649 |
Method for forming a retrograde impurity profile |
June 12, 2001 |
| A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 .ANG. to about 150 .ANG. on the surface of a semiconducting substrate. Thereafter, an ion implantatio |
| 6242330 |
Process for breaking silicide stringers extending between silicide areas of different active reg |
June 5, 2001 |
| A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over |
| 6225188 |
Self aligned method for differential oxidation rate at shallow trench isolation edge |
May 1, 2001 |
| A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantatio |
| 6225151 |
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion |
May 1, 2001 |
| A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be |
| 6204148 |
Method of making a semiconductor device having a grown polysilicon layer |
March 20, 2001 |
| A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first lay |
| 6201278 |
Trench transistor with insulative spacers |
March 13, 2001 |
| An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacer |
| 6197645 |
Method of making an IGFET with elevated source/drain regions in close proximity to gate with slo |
March 6, 2001 |
| An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and |
| 6188107 |
High performance transistor fabricated on a dielectric film and method of making same |
February 13, 2001 |
| The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon a |
| 6187620 |
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions p |
February 13, 2001 |
| A method is provided for forming an integrated circuit having junctions of n-channel transistors dissimilar to junctions of p-channel transistors. First and second gate conductors are formed upon a gate dielectric on a semiconductor substrate. Spacers are formed on sidewalls of the first |
