| Patent Number |
Title Of Patent |
Date Issued |
| 7256499 |
Ultra low dielectric constant integrated circuit system |
August 14, 2007 |
| An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in |
| 7208418 |
Sealing sidewall pores in low-k dielectrics |
April 24, 2007 |
| Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k |
| 7001840 |
Interconnect with multiple layers of conductive material with grain boundary between the layers |
February 21, 2006 |
| An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of t |
| 6756300 |
Method for forming dual damascene interconnect structure |
June 29, 2004 |
| For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material dispo |
| 6649034 |
Electro-chemical metal alloying for semiconductor manufacturing |
November 18, 2003 |
| The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A p |
| 6609946 |
Method and system for polishing a semiconductor wafer |
August 26, 2003 |
| The present invention provides a method and system for polishing a wafer surface. The method and system comprises determining whether a thickness of the wafer surface is uniform while the wafer surface is being polished, and adjusting the polishing process while the wafer surface is bein |
| 6583051 |
Method of manufacturing an amorphized barrier layer for integrated circuit interconnects |
June 24, 2003 |
| A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited |
| 6566248 |
Graphoepitaxial conductor cores in integrated circuit interconnects |
May 20, 2003 |
| A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrie |
| 6541286 |
Imaging of integrated circuit interconnects |
April 1, 2003 |
| A method is provided for X-ray imaging and analyzing grain boundaries, nodules or extrusions, voids, and separations or delaminations in conductive layers under dielectric capping layers in integrated circuit interconnects. |
| 6504251 |
Heat/cold amorphized barrier layer for integrated circuit interconnects |
January 7, 2003 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening. An amorphized layer is formed by |
| 6501177 |
Atomic layer barrier layer for integrated circuit interconnects |
December 31, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening and has a first amorphized atomic |
| 6455413 |
Pre-fill CMP and electroplating method for integrated circuits |
September 24, 2002 |
| A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrie |
| 6425991 |
Plating system with secondary ring anode for a semiconductor wafer |
July 30, 2002 |
| An electroplating system is provided for seed layer covered semiconductor wafers. A plating chamber is provided with an inert primary anode connectible to a positive voltage source and a semiconductor wafer connector connectible to a negative voltage source. The plating chamber furth |
| 6413390 |
Plating system with remote secondary anode for semiconductor manufacturing |
July 2, 2002 |
| The present invention provides an electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A consumable |
| 6402909 |
Plating system with shielded secondary anode for semiconductor manufacturing |
June 11, 2002 |
| An electroplating system is provided for semiconductor wafers which include a plating chamber having a consumable shielded secondary anode shielded by an inert anode from a semiconductor wafer connector. For a copper plating system the plating chamber has a consumable copper shielded ano |
| 6348732 |
Amorphized barrier layer for integrated circuit interconnects |
February 19, 2002 |
| An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is de |
