| Patent Number |
Title Of Patent |
Date Issued |
| 7432164 |
Semiconductor device comprising a transistor having a counter-doped channel region and method fo |
October 7, 2008 |
| A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type |
| 7297588 |
Electronic device comprising a gate electrode including a metal-containing layer having one or m |
November 20, 2007 |
| One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be us |
| 7091568 |
Electronic device including dielectric layer, and a process for forming the electronic device |
August 15, 2006 |
| A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer |
| 7029980 |
Method of manufacturing SOI template layer |
April 18, 2006 |
| A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the |
| 7015153 |
Method for forming a layer using a purging gas in a semiconductor process |
March 21, 2006 |
| A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the |
| 6972224 |
Method for fabricating dual-metal gate device |
December 6, 2005 |
| A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO.sub.2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial |
| 6894353 |
Capped dual metal gate transistors for CMOS process and method for making the same |
May 17, 2005 |
| A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment first gate (120) includes a first metal layer (110) of titanium nitride on a gate dielectric (108), a secon |
| 6818493 |
Selective metal oxide removal performed in a reaction chamber in the absence of RF activation |
November 16, 2004 |
| A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfaci |
| 6717226 |
Transistor with layered high-K gate dielectric and method therefor |
April 6, 2004 |
| A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the |
| 6432779 |
Selective removal of a metal oxide dielectric |
August 13, 2002 |
| A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate |
| 6423632 |
Semiconductor device and a process for forming the same |
July 23, 2002 |
| A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion lies be |
| 6383873 |
Process for forming a structure |
May 7, 2002 |
| A finished structure (100) includes a semiconductive region (102), a first oxide layer (106), a second oxide layer (108), and a conductive layer (110). The first oxide layer (106) lies between the semiconductive region (102) and the second oxide layer (108); and the second oxide layer (1 |
| 6376349 |
Process for forming a semiconductor device and a conductive structure |
April 23, 2002 |
| Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetr |
| 6362071 |
Method for forming a semiconductor device with an opening in a dielectric layer |
March 26, 2002 |
| In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bo |
| 6297173 |
Process for forming a semiconductor device |
October 2, 2001 |
| A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface laye |
| 6255204 |
Method for forming a semiconductor device |
July 3, 2001 |
| A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-conta |
| 6136682 |
Method for forming a conductive structure having a composite or amorphous barrier layer |
October 24, 2000 |
| A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorph |
| 6084279 |
Semiconductor device having a metal containing layer overlying a gate dielectric |
July 4, 2000 |
| Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials ar |
| 6063698 |
Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrat |
May 16, 2000 |
| A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned |
| 6027961 |
CMOS semiconductor devices and method of formation |
February 22, 2000 |
| In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). |
| 6020024 |
Method for forming high dielectric constant metal oxides |
February 1, 2000 |
| A method for forming a metal gate (20) structure begins by providing a semiconductor substrate (12). The semiconductor substrate (12) is cleaned to reduce trap sites. A nitrided layer (14) having a thickness of less than approximately 20 Angstroms is formed over the substrate (12). This |
| 5972804 |
Process for forming a semiconductor device |
October 26, 1999 |
| A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface laye |
| 5885870 |
Method for forming a semiconductor device having a nitrided oxide dielectric layer |
March 23, 1999 |
| In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrat |
| 5830802 |
Process for reducing halogen concentration in a material layer during semiconductor device fabri |
November 3, 1998 |
| A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). |
| 5726087 |
Method of formation of semiconductor gate dielectric |
March 10, 1998 |
| A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of one of either nitrogen or fluorine. A thermal oxide layer |
| 5712208 |
Methods of formation of semiconductor composite gate dielectric having multiple incorporated ato |
January 27, 1998 |
| A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is |
| 5707889 |
Process for forming field isolation |
January 13, 1998 |
| An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likel |
| 5580815 |
Process for forming field isolation and a structure over a semiconductor substrate |
December 3, 1996 |
| An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likel |
| 5571734 |
Method for forming a fluorinated nitrogen containing dielectric |
November 5, 1996 |
| This disclosure reveals a manufacturable and controllable method to fabricate a dielectric which increases the device current drive. A nitrogen-containing ambient is used to oxidize a surface of a substrate (10) to form a nitrogen-containing dielectric (12). Then a fluorine-containin |
| 5552332 |
Process for fabricating a MOSFET device having reduced reverse short channel effects |
September 3, 1996 |
| A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric |
| 5543635 |
Thin film transistor and method of formation |
August 6, 1996 |
| An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) |
| 5539216 |
Monolithic semiconductor body with convex structure |
July 23, 1996 |
| A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic |
| 5510278 |
Method for forming a thin film transistor |
April 23, 1996 |
| An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) |
| 5464792 |
Process to incorporate nitrogen at an interface of a dielectric layer in a semiconductor device |
November 7, 1995 |
| Nitrogen is piled-up at a top interface of a gate dielectric layer by a process of the present invention. A gate dielectric layer (14) is formed on a substrate (12). A buffer layer (16), such as polysilicon, is formed on the dielectric layer. A nitrogen source layer (18), such as oxynitr |
| 5407870 |
Process for fabricating a semiconductor device having a high reliability dielectric material |
April 18, 1995 |
| A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon di |
| 5371035 |
Method for forming electrical isolation in an integrated circuit device |
December 6, 1994 |
| A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the si |
| 5352615 |
Denuding a semiconductor substrate |
October 4, 1994 |
| A semiconductor substrate is denuded using a reducing gas mixture including carbon monoxide and carbon dioxide. Use of the reducing gas mixture allows very low oxygen partial pressure to be achieved in a furnace tube during the step of denuding. Oxygen partial pressure lower than 1E-9 at |
| 5300187 |
Method of removing contaminants |
April 5, 1994 |
| Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants presen |
| 5208189 |
Process for plugging defects in a dielectric layer of a semiconductor device |
May 4, 1993 |
| Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a |
| 4987102 |
Process for forming high purity thin films |
January 22, 1991 |
| A method is described for the formation of high purity thin films on a semiconductor substrate. In the preferred embodiment of the invention a thin film is formed on a semiconductor substrate in a plasma enhanced chemical vapor deposition system. Energized silicon ions are obtained by |
| 4927780 |
Encapsulation method for localized oxidation of silicon |
May 22, 1990 |
| An improved LOCOS isolation process is disclosed wherein an oxidizable layer is conformably dieposited to overlie a silicon nitride oxidation mask. In accordance with one embodiment of the invention, a composite layer comprising a buffer layer and an oxidation resistant material is p |
| 4914046 |
Polycrystalline silicon device electrode and method |
April 3, 1990 |
| A polycrystalline silicon electrode and method for its fabrication are disclosed. The electrode includes a barrier layer formed by the implantation of carbon, nitrogen, or oxygen ions between two layers of polycrystalline silicon. The lower layer of polycrystalline silicon is lightly |
| 4897364 |
Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer |
January 30, 1990 |
| An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitride mask with the polysilicon p |
| 4822753 |
Method for making a w/tin contact |
April 18, 1989 |
| A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate an |
| 4819040 |
Epitaxial CMOS by oxygen implantation |
April 4, 1989 |
| A technique for selectively implanting regions of semiconductor crystals with oxygen to increase their yield strength. This intentional, selective oxygen pinning technique is especially useful in causing underlying, originally oxygen-free silicon to be more resistant to plastic deformati |
| 4740483 |
Selective LPCVD tungsten deposition by nitridation of a dielectric |
April 26, 1988 |
| A process for selective deposition of a refractory metal such as tungsten at high temperatures and low pressure via chemical vapor deposition during semiconductor device manufacturing is provided. A dielectric layer is nitrided by chemical deposition of a nitrogen bearing gas prior to LP |
| 4605947 |
Titanium nitride MOS device gate electrode and method of producing |
August 12, 1986 |
| An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to impro |
| 4570328 |
Method of producing titanium nitride MOS device gate electrode |
February 18, 1986 |
| An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to impro |
| 4548654 |
Surface denuding of silicon wafer |
October 22, 1985 |
| A process is disclosed for preparing silicon wafers having a high quality, high lifetime surface layer and a bulk region characterized by a low lifetime and by a high density of precipitated oxygen gettering sites. A wafer having a relatively high concentration of interstitial oxygen is |
