| Patent Number |
Title Of Patent |
Date Issued |
| 7372872 |
System and method for monitoring upstream and downstream transmissions in cable modern system |
May 13, 2008 |
| A network monitor includes means for monitoring downstream traffic from a cable modem termination system (CMTS) to a cable modem (CM), means for monitoring upstream traffic from the CM to the CMTS, and means for identifying a data format used by the CMTS and the CM for bi-directional |
| 5070514 |
Method and apparatus for clearing data path in half duplex modem receiver while maintaining dyna |
December 3, 1991 |
| A DSP receiver for a fast turnaround modem, particularly suited for a half duplex fast turnaround modem which prevents destruction of communication channel related adaptive equalizer parameters upon loss of carrier. Upon detection of carrier loss, after sufficient time has been allowed f |
| 5040194 |
Method and apparatus for providing for automatic gain control of incoming signals in a modem |
August 13, 1991 |
| An improved circuit for providing automatic gain control (AGC) for incoming phase shift keyed (PSK) and quadrature amplitude modulated (QAM) signals. An absolute value circuit (193) and a comparator (195) provide a first error signal (197). An integrater (200,202) smoothes the first erro |
| 5040192 |
Method and apparatus for optimally autocorrelating an FSK signal |
August 13, 1991 |
| An autocorrelator for FSK signals. An FSK signal, incoming on a telephone line is filtered by a bandpass filter (13) and sampled by an A/D converter (14). A sample clock (15) provides a fixed sampling frequency, FS. A first interpolating filter (20B) provides selectable delays which are |
| 5018166 |
Method and apparatus for baud timing recovery |
May 21, 1991 |
| A data communications receiver for use in a modem. A fixed sample clock and a dominated tap tracking algorithm lock the local baud timing in the receiver to the baud timing in a remote transmitter. An interpolating filter provides a plurality of discrete delays. A filter control circuit |
| 5001729 |
High speed half duplex modem with fast turnaround protocol |
March 19, 1991 |
| A phase locked loop circuit which eliminates the phase difference between an incoming reference signal and a sampling signal by sampling the incoming reference signal to produce a sampled signal. The sign of the sampled signal at two sample points is compared to determine in which qu |
| 4910474 |
Method and apparatus for generating phase and amplitude modulated signals |
March 20, 1990 |
| An improved circuit for generating phase and amplitude modulated signals in a modem. A first circuit (161) generates a first signal (163) using a 1200 Hz carrier (160) and an input data stream (162). This signal (163) is generated at the rate of 7200 samples per second. The first signal |
| 4894847 |
High speed half duplex modem with fast turnaround protocol |
January 16, 1990 |
| A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an impr |
| 4868864 |
Autocorrelating 2400 bps handshake sequence detector |
September 19, 1989 |
| An improved V.22 bis 2400 bits per second (bps) handshake sequence detector. An incoming phase keyed (PSK) handshake sequence is autocorrelated using a frequency shift keyed (FSK) receiver (101). The autocorrelated signal is then filtered by a low pass filter (106). The autocorrelate |
| 4849703 |
Method and apparatus for generating a data sampling clock locked to a baud clock contained in a |
July 18, 1989 |
| An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide |
