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Miwa Tanaka Patents |
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Inventor: Tanaka; Miwa
Address: Yokohama, JP
No. of patents: 2
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6187632 |
Anneal technique for reducing amount of electronic trap in gate oxide film of transistor |
February 13, 2001 |
| A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passi |
| 6100579 |
Insulating film for use in semiconductor device |
August 8, 2000 |
| In manufacturing a CVD film (interlayer insulating film or passivation film) using material gases containing a gas having Si--H combination, the amount of Si--H combination in the CVD film (12, 31, 32, 33, 34, 47, 48, 49, 57, 59) is set to 0.6.times.10.sup.21 cm.sup.-3 or less to thereby |
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