| Patent Number |
Title Of Patent |
Date Issued |
| 7432558 |
Formation of semiconductor devices to achieve <100> channel orientation |
October 7, 2008 |
| A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a <100> orientation. A first gate may be formed on the |
| 7384725 |
System and method for fabricating contact holes |
June 10, 2008 |
| A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a pl |
| 7351638 |
Scanning laser thermal annealing |
April 1, 2008 |
| A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the mo |
| 7313769 |
Optimizing an integrated circuit layout by taking into consideration layout interactions as well |
December 25, 2007 |
| A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representatio |
| 7276328 |
Lithography mask utilizing asymmetric light source |
October 2, 2007 |
| A method of reflective lithography includes directing an asymmetric radiation (light) beam onto a reticle of a reflective lithography system. The asymmetry in the shape of the radiation beam may be used to compensate for a non-zero (non-normal) angle of incidence of the incident radi |
| 7269804 |
System and method for integrated circuit device design and manufacture using optical rule checki |
September 11, 2007 |
| A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process |
| 7211489 |
Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anne |
May 1, 2007 |
| The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel |
| 7194725 |
System and method for design rule creation and selection |
March 20, 2007 |
| A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability an |
| 7183223 |
Methods for forming small contacts |
February 27, 2007 |
| Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the |
| 7169711 |
Method of using carbon spacers for critical dimension (CD) reduction |
January 30, 2007 |
| A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposi |
| 7122455 |
Patterning with rigid organic under-layer |
October 17, 2006 |
| For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimensio |
| 7091097 |
End-of-range defect minimization in semiconductor device |
August 15, 2006 |
| A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-c |
| 7091068 |
Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices |
August 15, 2006 |
| A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An a |
| 7084071 |
Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon |
August 1, 2006 |
| A method of producing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate and providing an amorphous carbon layer over the polysilicon material layer. The amorphous carbon layer comprises at least one undoped amorphous carbon layer and |
| 7052961 |
Method for forming wordlines having irregular spacing in a memory array |
May 30, 2006 |
| According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory |
| 7029959 |
Source and drain protection and stringer-free gate formation in semiconductor devices |
April 18, 2006 |
| A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the or |
| 7029958 |
Self aligned damascene gate |
April 18, 2006 |
| A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose |
| 7015124 |
Use of amorphous carbon for gate patterning |
March 21, 2006 |
| A method of producing an integrated circuit includes providing a mask definition structure above a layer of conductive material and providing a mask above the layer of conductive material and in contact with at least a portion of the mask definition structure. The mask definition structu |
| 7014966 |
Method and apparatus for elimination of bubbles in immersion medium in immersion lithography sys |
March 21, 2006 |
| A method of operating an immersion lithography system, including steps of immersing at least a portion of a wafer to be exposed in an immersion medium, wherein the immersion medium comprises at least one bubble; directing an ultrasonic wave through at least a portion of the immersion |
| 6972576 |
Electrical critical dimension measurement and defect detection for reticle fabrication |
December 6, 2005 |
| A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The s |
| 6931618 |
Feed forward process control using scatterometry for reticle fabrication |
August 16, 2005 |
| A system for selectively generating and feeding forward reticle fabrication data is provided. The system includes components for fabricating a reticle and a control system operatively connected to the fabricating components, where the control system can control the operation of the fabri |
| 6902966 |
Low-temperature post-dopant activation process |
June 7, 2005 |
| A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants w |
| 6875664 |
Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and AR |
April 5, 2005 |
| A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region |
| 6872647 |
Method for forming multiple fins in a semiconductor device |
March 29, 2005 |
| A method of forming multiple fins in a semiconductor device includes forming a structure having an upper surface and side surfaces on the semiconductor device. The semiconductor device includes a conductive layer located below the structure. The method also includes forming spacers a |
| 6869734 |
EUV reflective mask having a carbon film and a method of making such a mask |
March 22, 2005 |
| An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of les |
| 6867080 |
Polysilicon tilting to prevent geometry effects during laser thermal annealing |
March 15, 2005 |
| A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to "fill in" the spaces between |
| 6864164 |
Finfet gate formation using reverse trim of dummy gate |
March 8, 2005 |
| A method of forming a gate electrode for a fin field effect transistor (FinFET) includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a carbon layer over the oxide layer and forming a trench in the oxide layer and the carbon la |
| 6855627 |
Method of using amorphous carbon to prevent resist poisoning |
February 15, 2005 |
| An exemplary embodiment relates to a method of using an amorphous carbon layer to prevent photoresist poisoning. The method includes doping a first amorphous carbon layer located above a substrate, providing an oxide layer above the first amorphous carbon layer where the oxide layer has |
| 6855582 |
FinFET gate formation using reverse trim and oxide polish |
February 15, 2005 |
| A method of forming a gate electrode for a fin field effect transistor (FinFET) is provided. The method includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a trench in the oxide layer, the trench crossing over the fin, and fi |
| 6852455 |
Amorphous carbon absorber/shifter film for attenuated phase shift mask |
February 8, 2005 |
| An exemplary embodiment relates to a phase shifting mask including a glass substrate layer and an amorphous carbon absorber layer located above the glass substrate layer. The amorphous carbon absorber layer includes apertures through which light passes unaltered to the glass substrate |
| 6825115 |
Post silicide laser thermal annealing to avoid dopant deactivation |
November 30, 2004 |
| Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming |
| 6812106 |
Reduced dopant deactivation of source/drain extensions using laser thermal annealing |
November 2, 2004 |
| Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions |
| 6808591 |
Model based metal overetch control |
October 26, 2004 |
| A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch cha |
| 6790782 |
Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resis |
September 14, 2004 |
| The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently i |
| 6787854 |
Method for forming a fin in a finFET device |
September 7, 2004 |
| A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the |
| 6787476 |
Etch stop layer for etching FinFET gate over a large topography |
September 7, 2004 |
| A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third lay |
| 6787439 |
Method using planarizing gate material to improve gate critical dimension in semiconductor devic |
September 7, 2004 |
| A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. |
| 6780789 |
Laser thermal oxidation to form ultra-thin gate oxide |
August 24, 2004 |
| Ultra-thin gate oxides are formed by exposing the upper surface of a substrate to a pulsed laser light beam in an atmosphere containing oxygen. Embodiments include exposing a silicon substrate to a pulsed laser light beam at a radiant fluence of 0.1 to 0.8 joules/cm.sup.2 for 1 to 10 |
| 6771356 |
Scatterometry of grating structures to monitor wafer stress |
August 3, 2004 |
| A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The |
| 6758612 |
System and method for developer endpoint detection by reflectometry or scatterometry |
July 6, 2004 |
| A system for regulating (e.g., terminating) a development process is provided. The system includes one or more light sources, each light source directing light to one or more patterns and/or gratings on a wafer. Light reflected from the patterns and/or gratings is collected by a measurin |
| 6746944 |
Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing |
June 8, 2004 |
| Semiconductor devices with reduced NiSi/Si interface contact resistance are fabricated by forming preamorphized regions in a substrate at a depth overlapping the subsequently formed NiSi/Si interface, ion implanting impurities to form deep source/drain implants overlapping the preamo |
| 6743689 |
Method of fabrication SOI devices with accurately defined monocrystalline source/drain extension |
June 1, 2004 |
| Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implan |
| 6706571 |
Method for forming multiple structures in a semiconductor device |
March 16, 2004 |
| A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form th |
| 6684172 |
Sensor to predict void free films using various grating structures and characterize fill perform |
January 27, 2004 |
| One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitorin |
| 6680250 |
Formation of deep amorphous region to separate junction from end-of-range defects |
January 20, 2004 |
| A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate ext |
| 6673684 |
Use of diamond as a hard mask material |
January 6, 2004 |
| A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at le |
| 6664154 |
Method of using amorphous carbon film as a sacrificial layer in replacement gate integration pro |
December 16, 2003 |
| An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric layer over the patterned amorphou |
| 6656749 |
In-situ monitoring during laser thermal annealing |
December 2, 2003 |
| A method of manufacturing a semiconductor device includes thermal annealing source/drain regions with a laser, measuring a depth of the source/drain regions, and adjusting a parameter of the laser used in the thermal annealing process. After the laser is adjusted, the source/drain region |
| 6654659 |
Quartz crystal monitor wafer for lithography and etch process monitoring |
November 25, 2003 |
| One aspect of the present invention relates to a feedback-driven, closed loop system/method for obtaining consistently formed semiconductor structures. The system/method involves controlling the progression of a lithography process such as a deposition or etching process. The system |
| 6645797 |
Method for forming fins in a FinFET device using sacrificial carbon layer |
November 11, 2003 |
| A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The meth |
