| Patent Number |
Title Of Patent |
Date Issued |
| 7369446 |
Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a no |
May 6, 2008 |
| An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between |
| 7336540 |
Indirect measurement of negative margin voltages in endurance testing of EEPROM cells |
February 26, 2008 |
| An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating |
| 7307898 |
Method and apparatus for implementing walkout of device junctions |
December 11, 2007 |
| A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is con |
| 7257046 |
Memory data access scheme |
August 14, 2007 |
| A bitline selection network is composed of a plurality of bitlines and a plurality of global bitlines. The bitlines are grouped into bytes with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline |
| 7180795 |
Method of sensing an EEPROM reference cell |
February 20, 2007 |
| An array of memory cells having a predetermined group of storage cells, arranged in a row, also have an arrangement of one or more reference cells fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the |
| 7102950 |
Fuse data storage system using core memory |
September 5, 2006 |
| Fuse data used to configure ancillary circuits used with a non-volatile serial memory core are stored in locations within the memory core. As a first opcode or word is sent on a serial bus to the memory, a logic circuit intercepts the word and generates read fuse enable pulses that f |
| 7099202 |
Y-mux splitting scheme |
August 29, 2006 |
| A multiplexer circuit in a memory organized into page-portions has a plurality of bit-select multiplexers configured to couple a plurality of page-portion global bitlines to a sense amplifier input. A plurality of column address lines organized into data bytes comprises each page-por |
| 6856557 |
Signal integrity checking circuit |
February 15, 2005 |
| A signal integrity checking circuit for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage |
| 6815992 |
Circuit for testing and fine tuning integrated circuit (switch control circuit) |
November 9, 2004 |
| A switch controlling circuit for the testing and fine-tuning of integrated circuits comprising of a series of flip-flops chain together in a serial manner. The contents of the flip-flop are shift in from the input of the first flip-flop in the chain. The output of each flip-flop connects |
| 6097657 |
Method for reading out the contents of a serial memory |
August 1, 2000 |
| A serial memory device includes a Y decoder and sensing circuitry which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the targe |
| 6038185 |
Method and apparatus for a serial access memory |
March 14, 2000 |
| A serial memory device includes a Y decoder and sensing circuitry which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the targe |
| 5204838 |
High speed readout circuit |
April 20, 1993 |
| The high speed readout circuit has an amplifier unit and an operating point setting unit and reads data from a memory sense line at high speed. The circuit further includes a unit for setting an operating point of the amplifier unit by short-circuiting the input and output terminals of t |
