| Patent Number |
Title Of Patent |
Date Issued |
| 7405151 |
Method for forming a semiconductor device |
July 29, 2008 |
| A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 .ANG.. A copper l |
| 7396767 |
Semiconductor structure including silicide regions and method of making same |
July 8, 2008 |
| A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against t |
| 7354856 |
Method for forming dual damascene structures with tapered via portions and improved performance |
April 8, 2008 |
| The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above t |
| 7338903 |
Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer |
March 4, 2008 |
| A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employ |
| 7312531 |
Semiconductor device and fabrication method thereof |
December 25, 2007 |
| Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer ov |
| 7282450 |
Sidewall coverage for copper damascene filling |
October 16, 2007 |
| A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in |
| 7268065 |
Methods of manufacturing metal-silicide features |
September 11, 2007 |
| A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive laye |
| 7265038 |
Method for forming a multi-layer seed layer for improved Cu ECP |
September 4, 2007 |
| A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a |
| 7259463 |
Damascene interconnect structure with cap layer |
August 21, 2007 |
| A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the cond |
| 7256137 |
Method of forming contact plug on silicide structure |
August 14, 2007 |
| A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer |
| 7253501 |
High performance metallization cap layer |
August 7, 2007 |
| A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An in |
| 7250683 |
Method to solve via poisoning for porous low-k dielectric |
July 31, 2007 |
| A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection |
| 7247915 |
Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology |
July 24, 2007 |
| A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-lay |
| 7235482 |
Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomi |
June 26, 2007 |
| An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrat. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH.sub.3).sub.2}.sub.4 avoids hal |
| 7226860 |
Method and apparatus for fabricating metal layer |
June 5, 2007 |
| A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatmen |
| 7215024 |
Barrier-less integration with copper alloy |
May 8, 2007 |
| A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising |
| 7205234 |
Method of forming metal silicide |
April 17, 2007 |
| A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin |
| 7202162 |
Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure an |
April 10, 2007 |
| A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type openi |
| 7193327 |
Barrier structure for semiconductor devices |
March 20, 2007 |
| An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a si |
| 7182849 |
ECP polymer additives and method for reducing overburden and defects |
February 27, 2007 |
| Electrochemical plating polymer additives and method which reduces metal overburden in an electroplated metal while optimizing gap fill capability are disclosed. The polymer additives are provided in an electrochemical plating bath solution and may include low cationic charge density |
| 7179759 |
Barrier layer and fabrication method thereof |
February 20, 2007 |
| A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the b |
| 7105439 |
Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology |
September 12, 2006 |
| A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-lay |
| 7091600 |
Prevention of post CMP defects in CU/FSG process |
August 15, 2006 |
| A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the |
| 7078810 |
Semiconductor device and fabrication method thereof |
July 18, 2006 |
| A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 .ANG.. A copper layer is formed |
| 7071095 |
Barrier metal re-distribution process for resistivity reduction |
July 4, 2006 |
| A novel process for re-distributing a barrier layer deposited on a single damascene, dual damascene or other contact opening structure. The process includes providing a substrate having a contact opening structure and a metal barrier layer deposited in the contact opening structure, |
| 7030023 |
Method for simultaneous degas and baking in copper damascene process |
April 18, 2006 |
| A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via |
| 7015126 |
Method of forming silicided gate structure |
March 21, 2006 |
| A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and |
| 6995471 |
Self-passivated copper interconnect structure |
February 7, 2006 |
| An embodiment for a method for forming a self-passivated copper interconnect structure. An insulating layer is formed over a semiconductor structure. An opening is formed in the insulating layer. Next, we form a fill layer comprised of Cu and Ti over insulating layer. In a nitridatio |
| 6967155 |
Adhesion of copper and etch stop layer for copper alloy |
November 22, 2005 |
| A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is |
| 6949472 |
Method for high kinetic energy plasma barrier deposition |
September 27, 2005 |
| A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conducti |
| 6884736 |
Method of forming contact plug on silicide structure |
April 26, 2005 |
| A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop l |
| 6878615 |
Method to solve via poisoning for porous low-k dielectric |
April 12, 2005 |
| A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection |
| 6875692 |
Copper electromigration inhibition by copper alloy formation |
April 5, 2005 |
| A method of forming a copper structure, comprising the following steps. A substrate is provided. A patterned dielectric layer is formed over the substrate with the patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A Sn |
| 6864143 |
Eliminate bridging between gate and source/drain in cobalt salicidation |
March 8, 2005 |
| A new method is provided for the formation of salicided layers for a gate electrode structure. A gate electrode structure is formed, a first layer of gate spacers containing oxide is formed on the sidewalls of the gate structure. A second layer of gate spacers is deposited over the first |
| 6849543 |
Cobalt silicide formation method employing wet chemical silicon substrate oxidation |
February 1, 2005 |
| A method for forming a cobalt silicide layer employs a sequential treatment of a silicon substrate with a hydrofluoric acid material followed by a wet chemical oxidant material. A cobalt material layer is then formed upon the sequentially treated silicon substrate and the silicon substra |
| 6849173 |
Technique to enhance the yield of copper interconnections |
February 1, 2005 |
| A method of forming an oxide free copper interconnect, comprising the following steps. A substrate is provided and a patterned dielectric layer is formed over the substrate. The patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed |
| 6825520 |
Capacitor with a roughened silicide layer |
November 30, 2004 |
| A process for creating a storage node electrode, for a DRAM cell, exhibiting increased surface area resulting from the formation of an agglomerated metal silicide layer, on the top surface of the storage node electrode, has been developed. The process features creating a polysilicon, |
| 6815336 |
Planarization of copper damascene using reverse current electroplating and chemical mechanical p |
November 9, 2004 |
| Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet |
| 6806192 |
Method of barrier-less integration with copper alloy |
October 19, 2004 |
| A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising |
| 6797144 |
Method for reducing surface defects in an electrodeposition process |
September 28, 2004 |
| A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carryi |
| 6759750 |
Method for integrating low-K materials in semiconductor fabrication |
July 6, 2004 |
| A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openin |
| 6737352 |
Method of preventing particle generation in plasma cleaning |
May 18, 2004 |
| A method to prevent particle generation from sputtering clean is disclosed, the method comprises of forming a dielectric layer on a substrate, forming a nitrogen-containing dielectric layer on the dielectric layer, forming a plurality of contact holes in the dielectric layer and the |
| 6736701 |
Eliminate broken line damage of copper after CMP |
May 18, 2004 |
| A new method is provided for the post-deposition treatment of copper lines. A damascene copper line pattern whereby a TaN barrier layer and a seed layer have been provided is polished. Under the first embodiment of the invention, the deposited copper is polished (Cu CMP), the surface of |
| 6723639 |
Prevention of post CMP defects in Cu/FSG process |
April 20, 2004 |
| A common problem associated with damascene structures made of copper inlaid in FSG (flourinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the sur |
| 6716753 |
Method for forming a self-passivated copper interconnect structure |
April 6, 2004 |
| An embodiment for a method for forming a self-passivated copper interconnect structure. An insulating layer is formed over a semiconductor structure. An opening is formed in the insulating layer. Next, we form a fill layer comprised of Cu and Ti over insulating layer. In a nitridation |
| 6686280 |
Sidewall coverage for copper damascene filling |
February 3, 2004 |
| A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in th |
| 6620725 |
Reduction of Cu line damage by two-step CMP |
September 16, 2003 |
| A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A so |
| 6610592 |
Method for integrating low-K materials in semiconductor fabrication |
August 26, 2003 |
| A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openin |
| 6576543 |
Method for selectively depositing diffusion barriers |
June 10, 2003 |
| A method is provided for selectively depositing a silicided metal diffusion barrier layer in a semiconductor structure to reduce an electrical contact resistance with respect to an underlying copper layer while maintaining a copper diffusion resistance along the semiconductor feature sid |
| 6562725 |
Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon car |
May 13, 2003 |
| Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a |
