| Patent Number |
Title Of Patent |
Date Issued |
| 7376151 |
Recording and producing an MPEG information signal on/from a record carrier |
May 20, 2008 |
| A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital |
| 6724978 |
Recording and reproducing an MPEG information signal on/from a record carrier |
April 20, 2004 |
| During recording of an MPEG information signal on a record carrier, transport packets (P.sub.k) are stored in signal blocks in a track on the record carrier. x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, where x and y |
| 6556590 |
Apparatus and methods for transmitting an MPEG-information signal and a method for reproducing t |
April 29, 2003 |
| A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR |
| 6490406 |
Recording and reproducing an MPEG information signal on/from a record carrier |
December 3, 2002 |
| During recording of an MPEG information signal on a record carrier, transport packets (P.sub.k) are stored in signal blocks in a track on the record carrier. x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, where x and y |
| 6081526 |
Apparatus and methods for transmitting an MPEG information signal, and a method for reproducing |
June 27, 2000 |
| A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR |
| 5757434 |
Motion-compensated predictive encoder in which groups of pictures are each encoded with substant |
May 26, 1998 |
| A device comprising an MPEG encoder (2) is provided with a preanalyser (8) which encodes each picture with a fixed step size (Q.sub.2). The preanalyser is coupled to a computing circuit (9) which computes, for each type of (I, P, B) picture, a target value (T) for the number of bits for |
| 5606371 |
Video signal coding with proportionally integrating quantization control |
February 25, 1997 |
| A device for encoding a video signal comprises a picture transformer (22), a quantizer (23) and a variable-length encoder (24), as well as distribution device (6) for distributing a global target value (T) for the number of bits per picture or group of pictures in local target values |
| 5596581 |
Recording and reproducing an MPEG information signal using tagged timing information |
January 21, 1997 |
| A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR |
| 5579183 |
Recording and reproducing an MPEG information signal on/from a record carrier |
November 26, 1996 |
| During recording of an MPEG information signal on a record carrier (40), transport packets (P.sub.k) are stored in signal blocks in a track (1) on the record carrier (40). x transport packets of the MPEG information signal are stored in the second block sections (SB) of y signal blocks, |
| 5566174 |
MPEG information signal conversion system |
October 15, 1996 |
| A method of transmitting timing critical data via an asynchronous channel. The timing critical data can be an MPEG transport stream of packets. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The pack |
| 5416644 |
Device for processing an interlaced frame signal for display on a television display when the si |
May 16, 1995 |
| Device for splitting an interlaced television frame into a vertical low-frequency spatial signal and a vertical high-frequency motion auxiliary signal. In a forward play mode the two signals are added together. In a reverse play mode, in which the frames are supplied in the reverse o |
| 5339398 |
Memory architecture and method of data organization optimized for hashing |
August 16, 1994 |
| A hashing data storage and retrieval arrangement whose storage capacity is unaffected by collisions. A first memory serves as a hash index table, for storing pointers at each address location corresponding to a hash value generated by hashing a key data word. Each pointer is the address |
| 5239377 |
Device for splitting a digital interlaced television signal into components |
August 24, 1993 |
| Device for splitting a digital interlaced television signal into components in which interlaced frames are applied to a vertical low-pass filter (6). To prevent motion artefacts in the spatial signal thus obtained, the interlaced frame is also applied to a vertical high-pass filter (8). |
| 5058137 |
Lempel-Ziv decoder |
October 15, 1991 |
| A decoder for data encoded in a form combining a prefix which is a previously coded sub-string and a next data element in the data stream. The decoder includes memories for storing code words and data separately. Upon receipt of a code word the decoder stores the previously received |
| 4864529 |
Fast multiplier architecture |
September 5, 1989 |
| A digital multiplier circuit which implements a modified multiplier algorithm in binary form and can be implemented as a very large scale integrated circuit. The modified algorithm replaces the large summation required in a typical shift-and-add digital multiplier with the sum of sma |
| 4862402 |
Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized har |
August 29, 1989 |
| A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parall |
| 4782458 |
Architecture for power of two coefficient FIR filter |
November 1, 1988 |
| An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficie |
