| Patent Number |
Title Of Patent |
Date Issued |
| 7345914 |
Use of flash memory blocks outside of the main flash memory array |
March 18, 2008 |
| A method, device, and system are disclosed. In one embodiment, the device comprises an array of flash memory blocks to store information in a multiple bit per cell mode, one or more flash memory blocks external to the array to store information in a single bit per cell mode, and a me |
| 7191295 |
Sensing word groups in a memory |
March 13, 2007 |
| In one embodiment of the present invention, a method includes sensing a first burst length of data equal to half of a sense width of a plurality of sense amplifiers of a memory, and sensing a second burst length of data equal to the half of the sense width during a latency while sensing |
| 6920539 |
Method and system to retrieve information |
July 19, 2005 |
| Briefly, in accordance with an embodiment of the invention, a method and system to retrieve information from a memory is provided. The method may include transferring information from the memory in response to at least two synchronous burst read requests using pipelining. |
| 6678810 |
MFENCE and LFENCE micro-architectural implementation method and system |
January 13, 2004 |
| A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocat |
| 6651151 |
MFENCE and LFENCE micro-architectural implementation method and system |
November 18, 2003 |
| A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocat |
| 6526499 |
Method and apparatus for load buffers |
February 25, 2003 |
| The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is |
| 6216215 |
Method and apparatus for senior loads |
April 10, 2001 |
| The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is |
