| Patent Number |
Title Of Patent |
Date Issued |
| 7405438 |
Capacitor constructions and semiconductor structures |
July 29, 2008 |
| The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the se |
| 7355232 |
Memory devices with dual-sided capacitors |
April 8, 2008 |
| A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, |
| 7344755 |
Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD react |
March 18, 2008 |
| The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by |
| 7342273 |
Applying epitaxial silicon in disposable spacer flow |
March 11, 2008 |
| A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as activ |
| 7321148 |
Capacitor constructions and rugged silicon-containing surfaces |
January 22, 2008 |
| The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40.degree. C. higher than the first temp |
| 7317220 |
Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth |
January 8, 2008 |
| A semiconductor assembly providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices is disclosed. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly ha |
| 7279398 |
Microfeature workpiece processing apparatus and methods for controlling deposition of materials |
October 9, 2007 |
| The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure with |
| 7268382 |
DRAM cells |
September 11, 2007 |
| The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the se |
| 7258892 |
Methods and systems for controlling temperature during microfeature workpiece processing, e.g., |
August 21, 2007 |
| The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method th |
| 7247581 |
Methods for treating pluralities of discrete semiconductor substrates |
July 24, 2007 |
| The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remo |
| 7244648 |
Methods of forming semiconductor constructions |
July 17, 2007 |
| The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrif |
| 7238613 |
Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
July 3, 2007 |
| Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of amorphous silicon. |
| 7235138 |
Microfeature workpiece processing apparatus and methods for batch deposition of materials on mic |
June 26, 2007 |
| The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. |
| 7220312 |
Methods for treating semiconductor substrates |
May 22, 2007 |
| The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remo |
| 7199017 |
Methods of forming semiconductor circuitry |
April 3, 2007 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 7183208 |
Methods for treating pluralities of discrete semiconductor substrates |
February 27, 2007 |
| The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remo |
| 7176109 |
Method for forming raised structures by controlled selective epitaxial growth of facet using spa |
February 13, 2007 |
| Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline s |
| 7148118 |
Methods of forming metal nitride, and methods of forming capacitor constructions |
December 12, 2006 |
| The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed |
| 7119369 |
FET having epitaxial silicon growth |
October 10, 2006 |
| A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on t |
| 7112544 |
Method of atomic layer deposition on plural semiconductor substrates simultaneously |
September 26, 2006 |
| The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remo |
| 7101756 |
Methods for enhancing capacitors having roughened features to increase charge-storage capacity |
September 5, 2006 |
| Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the |
| 7101435 |
Methods for epitaxial silicon growth |
September 5, 2006 |
| Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial si |
| 7090815 |
Nanometer engineering of metal-support catalysts |
August 15, 2006 |
| A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and f |
| 7071056 |
Method of forming a dual-sided capacitor |
July 4, 2006 |
| A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, |
| 7056806 |
Microfeature workpiece processing apparatus and methods for controlling deposition of materials |
June 6, 2006 |
| The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure with |
| 7049231 |
Methods of forming capacitors |
May 23, 2006 |
| In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor |
| 7037775 |
Applying epitaxial silicon in disposable spacer flow |
May 2, 2006 |
| A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as activ |
| 7034353 |
Methods for enhancing capacitors having roughened features to increase charge-storage capacity |
April 25, 2006 |
| Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the |
| 7023039 |
Capacitor structures with dual-sided electrode |
April 4, 2006 |
| The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity |
| 7012294 |
Semiconductor constructions |
March 14, 2006 |
| The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrif |
| 6979631 |
Methods of forming semiconductor circuitry |
December 27, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6977407 |
Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth |
December 20, 2005 |
| A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptiv |
| 6972223 |
Use of atomic oxygen process for improved barrier layer |
December 6, 2005 |
| A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. Th |
| 6967134 |
Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructio |
November 22, 2005 |
| The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrif |
| 6967132 |
Methods of forming semiconductor circuitry |
November 22, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6951636 |
Nanometer engineering of metal-support catalysts |
October 4, 2005 |
| A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and f |
| 6949427 |
Methods of forming a capacitor structure |
September 27, 2005 |
| The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity |
| 6943078 |
Method and structure for reducing leakage current in capacitors |
September 13, 2005 |
| A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with |
| 6930015 |
Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
August 16, 2005 |
| Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of amorphous silicon. |
| 6919638 |
Method, structure and process flow to reduce line-line capacitance with low-K material |
July 19, 2005 |
| An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as |
| 6916723 |
Methods of forming rugged semiconductor-containing surfaces |
July 12, 2005 |
| The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the se |
| 6911367 |
Methods of forming semiconductive materials having flattened surfaces; methods of forming isolat |
June 28, 2005 |
| The invention includes methods of forming epitaxially-grown semiconductive material having a flattened surface, and methods of incorporating such material into trenched regions and elevated/source drain regions. A method of forming epitaxially-grown semiconductive material having a flatt |
| 6894310 |
Semiconductor constructions comprising monocrystalline silicon together with semiconductive mate |
May 17, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6890818 |
Methods of forming semiconductor capacitors and memory devices |
May 10, 2005 |
| Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion bar |
| 6888186 |
Reduction of damage in semiconductor container capacitors |
May 3, 2005 |
| Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion bar |
| 6881682 |
Method and structure for reducing leakage current in capacitors |
April 19, 2005 |
| A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with |
| 6881652 |
Method to fabricate an intrinsic polycrystalline silicon film |
April 19, 2005 |
| A thin film transistor using an intrinsic polycrystalline silicon film, the thin film transistor fabricated by forming an insulation layer on a substrate, forming a first amorphous silicon layer on the insulation layer, forming silicon nucleation sites on the first amorphous silicon |
| 6870210 |
Dual-sided capacitor |
March 22, 2005 |
| A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, |
| 6861326 |
Methods of forming semiconductor circuitry |
March 1, 2005 |
| The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least part |
| 6858493 |
Method of forming a dual-sided capacitor |
February 22, 2005 |
| A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, |
