| Patent Number |
Title Of Patent |
Date Issued |
| 7213127 |
System for producing addresses for a digital signal processor |
May 1, 2007 |
| A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated |
| 7143072 |
Method and a system for calculating the values of the neurons of a neural network |
November 28, 2006 |
| A neural network having layers of neurons divided into sublayers of neurons. The values of target neurons in one layer are calculated from sublayers of source neurons in a second underlying layer. It is therefore always possible to use for this calculation the same group of weights to |
| 7031696 |
Timekeeper with automatic time setting and time setting method for same |
April 18, 2006 |
| A timekeeper equipped with a radio reception device capable of decoding Radio Data System (RDS) information and including a time base, a display for displaying time data supplied by the time base, and an adjustment control for correcting the time data. The radio reception device includes |
| 6407587 |
Adiabatic logic circuit |
June 18, 2002 |
| An adiabatic logic circuit includes bidirectional transfer members to which input variables of the circuit are applied and which are connected between a first circuit terminal connected to a clock generator whose clock signal also powers the circuit and a second circuit terminal forming |
| 6366504 |
Random access memory |
April 2, 2002 |
| A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective |
| 6323710 |
D-type master-slave flip-flop |
November 27, 2001 |
| A D-type master-slave flip-flop includes a master unit receiving an input variable and producing two first intermediate variables, a transfer unit including at least two logic gates and a clock connection connected to one input of each of the gates, which are adapted to supply two second |
| 6275928 |
Microprocessor instruction pipeline having inhibit logic at each stage |
August 14, 2001 |
| The disclosure relates to microprocessors and, more particularly, to a system for organizing and a method for the sequencing of the circuits of a microprocessor. The instruction registers are connected in chains and an inhibiting device is associated with each instruction register. Each |
| 6023739 |
System for information processing comprising plurality of processors where interconnection nodes |
February 8, 2000 |
| In this device, each processor (P1 to P3) is associated with at least one dressable space (R1 to R3), whereas all the processors and all the addressable spaces are in communication by way of a common communication bus (BC).Between all the processors and each addressable space is connecte |
| 5845311 |
Hierarchical ROMs that are selectively accessed by microprocessor instructions containing codes |
December 1, 1998 |
| The invention relates to computer systems containing at least one microprocessor associated with at least one memory in which are recorded instructions of a program and/or data to be processed according to the instructions.The memory is divided up into N=2 modules, one of which has a gre |
| 5832469 |
Electronic system organized as a matrix network of functional cells |
November 3, 1998 |
| In this network (R) all the cells have identical construction. Each cell is assigned a code word which defines its function which it is to provide for within the network. With a view to the configuring of the cells (Cx,y), means (1) iteratively cause the translation into each of the cell |
| 5748522 |
Memory element of the master-slave flip-flop type, constructed by CMOS technology |
May 5, 1998 |
| A memory element includes a master flip-flop (1) intended to control a slave flip-flop (2) via a transfer variable (A). The slave flip-flop (2) consists of a first gate (2a) controlled by the transfer variable (A), a clock signal (CK) and a true output variable (Q), so as to deliver a |
| 5686856 |
Multiplexer of logic variables |
November 11, 1997 |
| It comprises first (3) and second (4) transmission logic gates each fed with one input variable. The first gate (3) applies a first elementary logic function (NAND) to one of the input variables and to a multiplexer control logic variable (S). The second gate applies, on the one hand, a |
| 5508636 |
Electronic system organised as an array of cells |
April 16, 1996 |
| The invention concerns a programmable integrated electronic system including an array of identical cells (53). Each cell includes functional components (530) capable, when they are correctly connected, of executing a given function, and programmable connecting means (a to h) for on the |
| 4385291 |
Electronic diary watch |
May 24, 1983 |
| The data input device permits the selection of a symbol amongst a set of N symbols, e.g. for memorizing a message. A data input device permitting selection of a particular symbol from amongst a set of N symbols includes a display subdivided into K distinct display zones and K selecting |
| 4369440 |
Data input device |
January 18, 1983 |
| A device is provided for the rapid and easy introduction of data into an apparatus, e.g., for setting a digital watch. A binary decision device continuously tests the state of a plurality of finger responsive sensors A, B, C and D and produces control signals for a operational unit. The |
| 4365243 |
Interface device for the entry of data into an instrument of small volume responsive to body mov |
December 21, 1982 |
| The invention concerns an interface device for the entry of data into an trument of small volume such as a timepiece and comprises a static touch responsive sensor formed by a plurality of juxtaposed electrodes. An electronic logic circuit on the one hand receives signals emitted by the |
| 4242676 |
Interactive device for data input into an instrument of small dimensions |
December 30, 1980 |
| The device according to the invention comprises a sensor formed by a plurality of capacitive or resistive electrodes. The user searches the symbol to be selected by displacing his finger on the sensor while looking at a control display unit. Any position of the finger on the sensor cause |
| 4230957 |
Logic JK flip-flop structure |
October 28, 1980 |
| A logic JK flip-flop structure is disclosed which may have a dynamic, semi-dynamic or static behavior as far as the clock signal is concerned. The structure of the invention is particularly simple in design and has a minimum number of transistors although it is insensitive to parasitic |
| 4227097 |
Logic D flip-flop structure |
October 7, 1980 |
| A logic D flip-flop structure is disclosed which may have a dynamic, semi-dynamic or static behaviour as far as the clock signal is concerned. The structure of the invention is particularly simple in design and has a minimum number of transistors although it is insensitive to parasitic |
| 4199751 |
Device for the input of alphanumerical data for apparatus of small size |
April 22, 1980 |
| A device for the input of alphanumerical data for apparatus of small size. The device comprises a keyboard formed of zones and members for the introduction of data, a monitoring display having luminous segments and electronic memorizing and decoding means, with the introduction zones |
| 4106279 |
Wrist watch incorporating a thermoelectric generator |
August 15, 1978 |
| An electric wrist watch including a case containing a timekeeping module, an electrical storage device, and a display device. The case also includes a thermoelectric generator in contact with two heat exchangers. The two heat exchangers are arranged such that they are at least temporaril |
| 4057741 |
Logic circuit for bistable D-dynamic flip-flops |
November 8, 1977 |
| A logic circuit for dynamic D-flip-flop includes five n-channel MOS transistors and five p-channel MOS transistors. When used as a shift register stage, it works correctly without any additional delay element or capacitor. With two more MOS-transistors, the logic circuit works correc |
