| Patent Number |
Title Of Patent |
Date Issued |
| 7430151 |
Memory with clocked sense amplifier |
September 30, 2008 |
| In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memory array during |
| 7345344 |
Embedded substrate interconnect for underside contact to source and drain regions |
March 18, 2008 |
| A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a firs |
| 6998952 |
Inductive device including bond wires |
February 14, 2006 |
| An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends b |
| 6862208 |
Memory device with sense amplifier and self-timed latch |
March 1, 2005 |
| A memory device (201) includes a plurality of memory cells (203), bit lines, word lines, a sense amplifier (314), and a self-timed latch (215). The sense amplifier (314), responsive to a sense enable signal, is for sensing and amplifying a voltage on the bit lines corresponding to a |
| 6838721 |
Integrated circuit with a transitor over an interconnect layer |
January 4, 2005 |
| An integrated circuit (101) includes electrical circuitry (105) formed on a substrate (103). An interconnect layer (109, 117) is formed over the electrical circuitry (105). In one example, a plurality of magneto-resistive random access memory cells (MRAM) (161, 171) is implemented ab |
| 6326811 |
Output buffer and method therefor |
December 4, 2001 |
| An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224, 226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a |
| 6169420 |
Output buffer |
January 2, 2001 |
| An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a |
| 5760626 |
BICMOS latch circuit for latching differential signals |
June 2, 1998 |
| A data value is passed from a bus (50) to a receiver (40) without a propagation delay. A data latch (10) stores the data value while the data value is being generated by the bus (50). The data latch (10) then holds the data value and provides the data value to the receiver (40) after the |
| 5726944 |
Voltage regulator for regulating an output voltage from a charge pump and method therefor |
March 10, 1998 |
| An SRAM memory cell (10) is provided a boosted voltage by a charge pump (56) to reduce the soft error rate within the SRAM (10) and to improve bit cell stability. A voltage regulator (58) is coupled to the charge pump (56) to regulate the operation of the charge pump (56) and its outputt |
| 5721509 |
Charge pump having reduced threshold voltage losses |
February 24, 1998 |
| A charge pump (40) is implemented with several stages (30), including a control stage (50), in a manner integral with a ring-oscillator loop. The charge pump (40) is more efficient for producing voltage VBB to supply to a substrate well implementing circuitry such as a DRAM or SRAM (61), |
| 5572467 |
Address comparison in an inteagrated circuit memory having shared read global data lines |
November 5, 1996 |
| A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address |
| 5502676 |
Integrated circuit memory with column redundancy having shared read global data lines |
March 26, 1996 |
| An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors |
| 5323360 |
Localized ATD summation for a memory |
June 21, 1994 |
| A memory (110) having sections of memory cells used ATD to generate the required timing signals, includes ATD generators (189), first summation circuits (180-183), and local summation circuits 185-187. An ATD pulse is generated by the ATD generators (189) when an address signal transitio |
| 5315179 |
BICMOS level converter circuit |
May 24, 1994 |
| A BICMOS level converter (60) for use at lower power supply voltages includes an input buffer (20) for receiving an ECL level input signal and providing level shifted buffered signals referenced to V.sub.SS, a differential amplifier (61), a clamping circuit (71 and 72) for preventing |
| 5313120 |
Address buffer with ATD generation |
May 17, 1994 |
| An address buffer (20) provides an ATD pulse in response to an address signal transitioning from one logic state to another. The address buffer (20) includes a differential amplifier (22), an emitter-follower transistor (35), and two P-channel transistors (36 and 37). A first current |
| 5309039 |
Power supply dependent input buffer |
May 3, 1994 |
| A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced to a positive power supply volta |
| 5303190 |
Static random access memory resistant to soft error |
April 12, 1994 |
| A static random access memory (30), resistant to soft error from alpha particle emissions has a high density array of memory cells (44) coupled to word lines (73 and 74) and bit line pairs (68), and operates at low power supply voltages (for example, 3.3 volts). A charging circuit (55) |
| 5278464 |
Using delay to obtain high speed current driver circuit |
January 11, 1994 |
| A current driver circuit (10) sources current to an output node (N4) in response to an input signal (VI) being a logic high. The current driver circuit (10) utilizes a current source (16) which sinks current from the output node (N4) in response to the input signal (VI) switching from a |
| 5140191 |
Low di/dt BiCMOS output buffer with improved speed |
August 18, 1992 |
| An output buffer for a device such as a memory comprises a voltage regulator, a current source portion, a switching portion, and an output portion. The voltage regulator provides a constant voltage independent of fluctuations between first and second power supply voltages. The current |
| 4943743 |
TTL to ECL input buffer |
July 24, 1990 |
| An input buffer for translating TTL level signals to ECL level signals has a level shifter having a first and a second inupt transistor. The first input transistor receives the input signal and the second transistor receives a reference voltage. First and second transistor loads are |
| 4928268 |
Memory using distributed data line loading |
May 22, 1990 |
| A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a |
| 4806799 |
ECL to CMOS translator |
February 21, 1989 |
| In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. Th |
| 4802129 |
RAM with dual precharge circuit and write recovery circuitry |
January 31, 1989 |
| A memory is written via data lines which are driven by a write driver. The data lines are coupled to a selected bit line pair as determined by a column address. The data lines are driven to a logic state representative of a data input signal by a write driver. The write driver is enabled |
| 4800531 |
Address buffer circuit for a dram |
January 24, 1989 |
| A DRAM has an input address buffer in which the first stage is a NOR gate. The output of the NOR gate is clocked to a latch which is preset to the slow condition of the NOR gate. The NOR gate is clocked separately from the clocking of the output of the NOR gate to the latch. A refresh co |
| 4794434 |
Trench cell for a dram |
December 27, 1988 |
| A DRAM memory cell has a trench capacitor and a transistor. The trench of the trench capacitor penetrates to a buried layer which acts as the primary portion of one of the plates of the capacitor. When the buried layer is the same conductivity type as the transistor of the memory cell, |
| 4791615 |
Memory with redundancy and predecoded signals |
December 13, 1988 |
| A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column from a main array. A redundant row |
| 4758743 |
Output buffer with improved di/dt |
July 19, 1988 |
| An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the |
| 4740921 |
Precharge of a dram data line to an intermediate voltage |
April 26, 1988 |
| A dynamic random access memory has data line pair which receives data from a selected pair of bit lines. Coupled to the data line pair is a secondary amplifier for amplifying the data provided to the data line pair from the bit line pair. The secondary amplifier has a maximum gain when t |
| 4710902 |
Technique restore for a dynamic random access memory |
December 1, 1987 |
| Memory cells in a dynamic random access memory are coupled to bit lines which are coupled to sense amplifiers. Memory cells are enabled by an enabled word line which causes the memory cells to output data onto the bit lines to which they are coupled. A selected bit line is coupled to a |
| 4691300 |
Redundant column substitution architecture with improved column access time |
September 1, 1987 |
| An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redunda |
| 4551641 |
Sense amplifier |
November 5, 1985 |
| A sense amplifier is coupled to a pair of bit lines for detecting and amplifying a voltage differential therebetween. The sense amplifier has a first differential amplifier coupled to the pair of bit lines enabled in response to a first signal. The sense amplifier also has a second d |
| 4449207 |
Byte-wide dynamic RAM with multiplexed internal buses |
May 15, 1984 |
| An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators |
