| Patent Number |
Title Of Patent |
Date Issued |
| 7448005 |
Method and system for performing utilization of traces for incremental refinement in coupling a |
November 4, 2008 |
| A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable |
| 7437690 |
Method for predicate-based compositional minimization in a verification environment |
October 14, 2008 |
| A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output functions and one or |
| 7421669 |
Using constraints in design verification |
September 2, 2008 |
| A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N') of the netlist. A space state (S') is created by enumerating the states of N' |
| 7398488 |
Trace equivalence identification through structural isomorphism detection with on the fly logic |
July 8, 2008 |
| A method for performing trace equivalent identification by structural isomorphism detection, the method comprising: synthesizing a first netlist into a second netlist, the second netlist including two-input AND gates, inversions, inputs, constants, and registers; constructing a third |
| 7380222 |
Method and system for performing minimization of input count during structural netlist overappro |
May 27, 2008 |
| A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or m |
| 7380221 |
Method and system for reduction of and/or subexpressions in structural design representations |
May 27, 2008 |
| A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate |
| 7373624 |
Method and system for performing target enlargement in the presence of constraints |
May 13, 2008 |
| A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers an |
| 7370298 |
Method for heuristic preservation of critical inputs during sequential reparameterization |
May 6, 2008 |
| A method, system, and computer program product for preserving critical inputs. According to an embodiment of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, |
| 7370292 |
Method for incremental design reduction via iterative overapproximation and re-encoding strategi |
May 6, 2008 |
| A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool the |
| 7367002 |
Method and system for parametric reduction of sequential designs |
April 29, 2008 |
| A method, system and computer program product for performing parametric reduction of sequential designs. According to an embodiment of the present invention, the method includes receiving an initial design including one or more primary inputs, one or more targets, and one or more sta |
| 7367001 |
Method, system and computer program product for verification of digital designs using case-split |
April 29, 2008 |
| A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logi |
| 7363603 |
Method and system for case-splitting on nodes in a symbolic simulation framework |
April 22, 2008 |
| A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the o |
| 7360185 |
Design verification using sequential and combinational transformations |
April 15, 2008 |
| System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circ |
| 7360181 |
Enhanced structural redundancy detection |
April 15, 2008 |
| A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection a |
| 7356792 |
Method and system for enhanced verification by closely coupling a structural overapproximation a |
April 8, 2008 |
| A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A com |
| 7350179 |
Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable a |
March 25, 2008 |
| A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representatio |
| 7350169 |
Method and system for enhanced verification through structural target decomposition |
March 25, 2008 |
| A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extrac |
| 7350166 |
Method and system for reversing the effects of sequential reparameterization on traces |
March 25, 2008 |
| A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first t |
| 7343573 |
Method and system for enhanced verification through binary decision diagram-based target decompo |
March 11, 2008 |
| A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram |
| 7340704 |
Method and system for optimized automated case-splitting via constraints in a symbolic simulatio |
March 4, 2008 |
| A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding |
| 7340694 |
Method and system for reduction of XOR/XNOR subexpressions in structural design representations |
March 4, 2008 |
| A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplif |
| 7340473 |
Method and system for building binary decision diagrams efficiently in a structural network repr |
March 4, 2008 |
| A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The me |
| 7322017 |
Method for verification using reachability overapproximation |
January 22, 2008 |
| A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of |
| 7315996 |
Method and system for performing heuristic constraint simplification |
January 1, 2008 |
| A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the first computer-design constraint. In response to determining that the first computer-desig |
| 7302656 |
Method and system for performing functional verification of logic circuits |
November 27, 2007 |
| A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is ap |
| 7299432 |
Method for preserving constraints during sequential reparameterization |
November 20, 2007 |
| A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including |
| 7290229 |
Method and system for optimized handling of constraints during symbolic simulation |
October 30, 2007 |
| A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one |
| 7266795 |
System and method for engine-controlled case splitting within multiple-engine based verification |
September 4, 2007 |
| A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of verification engines divides the verification problem into a set of partitions and passes at least |
| 7260799 |
Exploiting suspected redundancy for enhanced design verification |
August 21, 2007 |
| A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of |
| 7203915 |
Method for retiming in the presence of verification constraints |
April 10, 2007 |
| A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or m |
| 7093218 |
Incremental, assertion-based design verification |
August 15, 2006 |
| A design verification system includes a first verification engine to model the operation of a first design of an integrated circuit to obtain verification results including the model's adherence to a property during N time steps of its operation, proofs that one or more verification |
| 6993734 |
Use of time step information in a design verification system |
January 31, 2006 |
| The disclosed design verification system includes a verification engine to model the operation of an integrated circuit and to assess the model's adherence to a property during N time steps of its operation. The value of N is recorded and propagated. The propagated value of N is used to |
| 6983435 |
Integrated design verification and design simplification system |
January 3, 2006 |
| A design model verification method includes performing under approximation (UAV) processing to potentially resolve a defined verification problem and to identify a set of reachable states for the design model. If UAV processing fails to resolve the defined verification problem, coverage |
| 6698003 |
Framework for multiple-engine based verification tools for integrated circuits |
February 24, 2004 |
| A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a |
| 6473884 |
Method and system for equivalence-checking combinatorial circuits using interative binary-decisi |
October 29, 2002 |
| A method and system for equivalence checking of logical circuits using iterative circuit reduction and satisfiability techniques provide improved performance in computer-based verification and design tools. By intertwining a structural satisfiability solver and binary decision diagra |
