| Patent Number |
Title Of Patent |
Date Issued |
| 6002618 |
NMOS input receiver circuit |
December 14, 1999 |
| An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed b |
| 5907517 |
Memory circuit yield generator and timing adjustor |
May 25, 1999 |
| Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the wor |
| 5870346 |
VLSI memory circuit |
February 9, 1999 |
| A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge volt |
| 5812461 |
Driver circuit for addressing core memory and a method for the same |
September 22, 1998 |
| The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtu |
| 5793698 |
Semiconductor read-only VLSI memory |
August 11, 1998 |
| The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal. |
| 5732035 |
Very large scale integrated planar read only memory |
March 24, 1998 |
| An improved precharge timing control is provided by turning off the first one of a series of precharge clocks PC0 by means of discharging a single dummy word line. The dummy word line is comprised of a plurality of dummy word line segments wherein each of the segments are charged in para |
| 5650979 |
Semiconductor read-only VLSI memory |
July 22, 1997 |
| The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable |
| 5608687 |
Output driver control for ROM and RAM devices |
March 4, 1997 |
| The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an ou |
| 5596544 |
Very large scale integrated planar read only memory |
January 21, 1997 |
| Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevent |
| 5594696 |
Improvemetns in a detection circuit with a level shifting circuit |
January 14, 1997 |
| A circuit which differentially amplifies voltages that are close to ground with differences of about 0.15 volts uses voltage level shifters, a cross coupled current source and inverters to provide increased speed, accuracy, and gain. Symmetric cross coupled current sources are used in a |
| 5581203 |
Semiconductor read-only VLSI memory |
December 3, 1996 |
| The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperat |
| 5487038 |
Method for read cycle interrupts in a dynamic read-only memory |
January 23, 1996 |
| The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot |
| 5467300 |
Grounded memory core for Roms, Eproms, and EEpproms having an address decoder, and sense amplifi |
November 14, 1995 |
| The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are all precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected |
| 5459693 |
Very large scale integrated planar read only memory |
October 17, 1995 |
| In a read-only memory core improved generation of a trigger signal, TRIG, is achieved through the use of a pair of cascaded CMOS differential amplifiers which are directly interconnected and directly coupled to a CMOS inverter from which the trigger signal, TRIG, is derived. The casc |
| 5414663 |
VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit l |
May 9, 1995 |
| The operation of the sense amplifier in a VLSI memory is improved by providing dummy bit lines corresponding to the ON state and OFF state of the memory cells, averaging the voltage on the dummy bit lines, and comparing that average to the bit line voltage to generate a differential |
| 4274147 |
Static read only memory |
June 16, 1981 |
| A static read only memory fabricated with field effect transistors of either the depletion type or the enhancement type connected in series. The read only memory includes a compact sensing circuit for detecting relatively small voltage swings at each node corresponding to a bit line |
| 4256974 |
Metal oxide semiconductor (MOS) input circuit with hysteresis |
March 17, 1981 |
| An improved static metal oxide semiconductor (MOS) input circuit having particular utility as a TTL input receiver, is fabricated from enhancement and depletion-type field effect transistors (FETs). The input circuit is adapted to produce positive feedback to adjust the on-resistance rat |
| 4232270 |
High gain differential amplifier with positive feedback |
November 4, 1980 |
| An improved high gain, field effect transistor differential amplifier including first and second cascade connected inverter stages, a feedback controlled source of current connected to each of the stages, including a source of controlled positive feedback for increasing the voltage gain. |
| 4079332 |
High gain differential amplifier |
March 14, 1978 |
| A high gain, field effect transistor differential amplifier including first and second cascade connected inverter stages and a feedback controlled source of current connected to each of the stages. High voltage gain is achieved by virtue of a positive feedback path connected between an o |
| 4042838 |
MOS inverting power driver circuit |
August 16, 1977 |
| An improved, compact high-speed inverting power driver fabricated from field effect transistors and capable of driving a relatively heavy load to full -V.sub.DD power supply voltage. The power driver includes a pair of positive feedback circuits having respective bootstrap capacitors arr |
| 3992703 |
Memory output circuit |
November 16, 1976 |
| A unique memory output integrated circuit disclosed including a memory output driver having an output terminal at which data may be read, a gated power amplifier, and a single ended multiplexer stage which, in the preferred embodiment, is adapted to be interfaced with a random access |
| 3990056 |
High speed memory cell |
November 2, 1976 |
| An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operation while, at the same time, d |
| 3986042 |
CMOS Boolean logic mechanization |
October 12, 1976 |
| Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A.sup.. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by sili |
| 3982138 |
High speed-low cost, clock controlled CMOS logic implementation |
September 21, 1976 |
| A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inve |
| 3943496 |
Memory clocking system |
March 9, 1976 |
| A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the two different binary values which |
