| Patent Number |
Title Of Patent |
Date Issued |
| 7329586 |
Gapfill using deposition-etch sequence |
February 12, 2008 |
| Methods deposit a film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. Flows of first precursor deposition gases are provided to the substrate processing chamber. A first high-density plasma is formed from the fl |
| 7276769 |
Semiconductor integrated circuit device |
October 2, 2007 |
| In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit formation portion are not electrically driven, while only semiconductor elements of a second |
| 7253436 |
Resistance defect assessment device, resistance defect assessment method, and method for manufac |
August 7, 2007 |
| A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resist |
| 7249343 |
In-plane distribution data compression method, in-plane distribution measurement method, in-plan |
July 24, 2007 |
| After a process is performed on a substrate, the in-plane distribution over the substrate is measured. Measured data of the in-plane distribution which is obtained by the measurement is stored. A model formula of the in-plane distribution is calculated from the stored measured data. |
| 7202147 |
Semiconductor device and method for fabricating the same |
April 10, 2007 |
| A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainl |
| 7202095 |
Method for measuring silicide proportion, method for measuring annealing temperature, method for |
April 10, 2007 |
| A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irradiated with X-rays so that the proportions of three types o |
| 7196346 |
Semiconductor memory device and method for fabricating the same |
March 27, 2007 |
| In a fabrication method according to the present invention, a first insulating film and tungsten plugs are formed over a substrate including a logic section and a memory section. An upper portion of one of the tungsten plug located in a memory section is removed, thereby forming a re |
| 6884674 |
Method for fabricating a semiconductor device including a capacitance insulating film having a p |
April 26, 2005 |
| A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO.sub.3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebe |
| 6773979 |
Method for fabricating semiconductor device |
August 10, 2004 |
| The invention provides a method for fabricating a semiconductor device including a concaved capacitor device having a lower electrode, a capacitor dielectric film of a perovskite type high dielectric constant or ferroelectric material formed on the lower electrode and an upper electr |
| 6645807 |
Method for manufacturing semiconductor device |
November 11, 2003 |
| After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer. |
| 6531729 |
Semiconductor device and method for fabricating the same |
March 11, 2003 |
| A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces. |
| 6501113 |
Semiconductor device with capacitor using high dielectric constant film or ferroelectric film |
December 31, 2002 |
| A semiconductor device including a semiconductor substrate having a main surface, an insulating layer formed on the main surface of the semiconductor substrate, and lower electrode film embedded in the insulating layer. A dielectric film embedded in the insulating layer covers the lo |
| 6486520 |
Structure and method for a large-permittivity gate using a germanium layer |
November 26, 2002 |
| A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate diel |
| 6436786 |
Method for fabricating a semiconductor device |
August 20, 2002 |
| A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces. |
| 6342420 |
Hexagonally symmetric integrated circuit cell |
January 29, 2002 |
| An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitl |
| 6335238 |
Integrated dielectric and method |
January 1, 2002 |
| This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are |
| 6287903 |
Structure and method for a large-permittivity dielectric using a germanium layer |
September 11, 2001 |
| A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate diel |
| 6265262 |
Semiconductor device and method of fabricating the same |
July 24, 2001 |
| A silicon film is formed within a contact hole formed in a first insulating film on a semiconductor substrate in a manner that an upper portion of the contact hole remains, and a cobalt film is then deposited on the silicon film. Thereafter, a heat treatment is carried out so as to react |
| 6251749 |
Shallow trench isolation formation with sidewall spacer |
June 26, 2001 |
| An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure. |
| 6166408 |
Hexagonally symmetric integrated circuit cell |
December 26, 2000 |
| An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitl |
| 6110842 |
Method of forming multiple gate oxide thicknesses using high density plasma nitridation |
August 29, 2000 |
| A method for forming integrated circuits having multiple gate oxide thicknesses. A high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only. In one embodiment, a pattern (12) is formed over a substrate (10) |
| 6033953 |
Method for manufacturing dielectric capacitor, dielectric memory device |
March 7, 2000 |
| A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the |
| 5814888 |
Semiconductor device having a multilayer wiring and the method for fabricating the device |
September 29, 1998 |
| A semiconductor device with a multilayer wiring structure has an insulating substrate and first conductors formed on top of the insulating substrate with a groove between neighboring first conductors. An insulating film covers the first conductors as well as the grooves between the neigh |
| 5616515 |
Silicon oxide germanium resonant tunneling |
April 1, 1997 |
| A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides. |
| 5466949 |
Silicon oxide germanium resonant tunneling |
November 14, 1995 |
| A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides. |
| 5466949 |
Silicon oxide germanium resonant tunneling |
November 14, 1995 |
| A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides. |
