| Patent Number |
Title Of Patent |
Date Issued |
| 7279410 |
Method for forming inlaid structures for IC interconnections |
October 9, 2007 |
| A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and |
| 7256499 |
Ultra low dielectric constant integrated circuit system |
August 14, 2007 |
| An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in |
| 7208418 |
Sealing sidewall pores in low-k dielectrics |
April 24, 2007 |
| Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k |
| 6872663 |
Method for reworking a multi-layer photoresist following an underlayer development |
March 29, 2005 |
| A method of processing a semiconductor device is disclosed and comprises patterning a multi-layer photoresist which comprises an imaging layer overlying an underlying layer. The patterning of the resist defines an exposed portion of an underlying process layer. The method further com |
| 6846749 |
N-containing plasma etch process with reduced resist poisoning |
January 25, 2005 |
| A method for forming a metal interconnect comprises exposing a dielectric layer to an etch chemistry containing nitrogen-containing compound such as NH.sub.3, NF.sub.3 or N.sub.2 O. The nitrogen-containing compound provides selectivity and/or profile control comparable to that provided b |
| 6767827 |
Method for forming dual inlaid structures for IC interconnections |
July 27, 2004 |
| A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer ther |
| 6756300 |
Method for forming dual damascene interconnect structure |
June 29, 2004 |
| For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material dispo |
| 6713382 |
Vapor treatment for repairing damage of low-k dielectric |
March 30, 2004 |
| A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier |
| 6660619 |
Dual damascene metal interconnect structure with dielectric studs |
December 9, 2003 |
| A method for forming a dual damascene conductive line and conductive plug using porous low k dielectric materials in the via and trench layers. The via layer is provided with dense low k dielectric plugs that increase the mechanical strength of the porous low k dielectric layer that form |
| 6656830 |
Dual damascene with silicon carbide middle etch stop layer/ARC |
December 2, 2003 |
| The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop l |
| 6632707 |
Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning |
October 14, 2003 |
| A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the |
| 6610608 |
Plasma etching using combination of CHF3 and CH3F |
August 26, 2003 |
| A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening through the dielectric layer, etching the first barrier layer, and filling the |
| 6603206 |
Slot via filled dual damascene interconnect structure without middle etch stop layer |
August 5, 2003 |
| An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first diele |
| 6599839 |
Plasma etch process for nonhomogenous film |
July 29, 2003 |
| A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an et |
| 6583046 |
Post-treatment of low-k dielectric for prevention of photoresist poisoning |
June 24, 2003 |
| Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers in a nitrogen-containing atmosphere is eliminated, or at least substantially reduced, by post-treating exposed surfaces of the low-k dielectric |
| 6534397 |
Pre-treatment of low-k dielectric for prevention of photoresist poisoning |
March 18, 2003 |
| Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers is eliminated, or at least substantially reduced, by pretreating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g., by contac |
| 6521524 |
Via filled dual damascene structure with middle stop layer and method for making the same |
February 18, 2003 |
| An interconnect structure and method of forming the same in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer |
| 6514860 |
Integration of organic fill for dual damascene process |
February 4, 2003 |
| A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers t |
| 6495447 |
Use of hydrogen doping for protection of low-k dielectric layers |
December 17, 2002 |
| A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer; decreasing the hydrophilic properties of a first portion of the dielectric layer, forming an openi |
| 6492272 |
Carrier gas modification for use in plasma ashing of photoresist |
December 10, 2002 |
| Deleterious physical sputtering of workpiece layers accompanying removal of photoresist layers from the workpiece by plasma ashing utilizing an active plasma ashing gas such as O.sub.2, N.sub.2, N.sub.2 /O.sub.2, or H.sub.2 /N.sub.2 gas mixtures admixed with Ar inert carrier gas/diluent, |
| 6475929 |
Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer produ |
November 5, 2002 |
| A method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial e |
| 6472231 |
Dielectric layer with treated top surface forming an etch stop layer and method of making the sa |
October 29, 2002 |
| A metal interconnect arrangement provides a dielectric layer that has its upper surface treated to provide an etch stop etch stop layer. The upper surface is subjected to a plasma etch that treats, such as by carbonization, the dielectric material in a manner that alters the etch cha |
| 6465889 |
Silicon carbide barc in dual damascene processing |
October 15, 2002 |
| The dimensional accuracy of trenches and, hence, the width of metal lines, in damascene interconnection structures is improved by employing silicon carbide as a capping layer/BARC on an underlying metal feature, e.g., Cu. Embodiments include via first-trench last dual damascene technique |
| 6465340 |
Via filled dual damascene structure with middle stop layer and method for making the same |
October 15, 2002 |
| An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric la |
| 6451673 |
Carrier gas modification for preservation of mask layer during plasma etching |
September 17, 2002 |
| Deleterious physical sputtering of patterned masking layers accompanying formation of recesses in, e.g., dielectric layers, by reactive plasma etching utilizing a gas mixture of at least one halogen-containing reactive plasma etching gas and Ar as an inert carrier gas/diluent for the |
| 6448654 |
Ultra thin etch stop layer for damascene process |
September 10, 2002 |
| A metal interconnect structure and method of making the same provides an ultra thin etch stop layer employed in conjunction with low k dielectric layers. The thinness of the etch stop layer allows higher k dielectric materials to be used as the etch stop material without increasing the |
| 6444573 |
Method of making a slot via filled dual damascene structure with a middle stop layer |
September 3, 2002 |
| An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric la |
| 6429116 |
Method of fabricating a slot dual damascene structure without middle stop layer |
August 6, 2002 |
| An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer is deposited over a conductive layer. An organic low k dielectric material is deposited over the diffusin barrier/etch stop layer to form a first dielectric layer. The first dielectr |
| 6391766 |
Method of making a slot via filled dual damascene structure with middle stop layer |
May 21, 2002 |
| A method of forming an interconnect structure in which an organic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to |
| 6383919 |
Method of making a dual damascene structure without middle stop layer |
May 7, 2002 |
| An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An organic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielect |
| 6372635 |
Method for making a slot via filled dual damascene low k interconnect structure without middle s |
April 16, 2002 |
| An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first diele |
| 6372631 |
Method of making a via filled dual damascene structure without middle stop layer |
April 16, 2002 |
| An interconnect structure and method of forming the same in which a barrier diffusion layer/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the barrier diffusion layer/etch stop layer to form a first dielectric layer. The |
| 6365505 |
Method of making a slot via filled dual damascene structure with middle stop layer |
April 2, 2002 |
| A method of forming an interconnect structure in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched t |
| 6340395 |
Salsa clean process |
January 22, 2002 |
| A wet spray cleaning process for removing thick organic layers including hardened photoresist from the surface of silicon wafers yields low residual particle counts for photoresist thicknesses up to 3 microns, and maintains low residual particle density for oxide-covered wafer regions. |
| 6309955 |
Method for using a CVD organic barc as a hard mask during via etch |
October 30, 2001 |
| A method for forming a via of a metal interconnect structure in a semiconductor device employs a CVD organic BARC between a low k dielectric material and a via photoresist mask. The CVD organic BARC is deposited over the low k dielectric film and protects the film during formation and |
