| Patent Number |
Title Of Patent |
Date Issued |
| 7328359 |
Technique to create link determinism |
February 5, 2008 |
| A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agen |
| 6704892 |
Automated clock alignment for testing processors in a bypass mode |
March 9, 2004 |
| In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock signals may be used to generate aligned high frequency signals to replace those generated |
| 6477674 |
Method and apparatus for conducting input/output loop back tests using a local pattern generator |
November 5, 2002 |
| In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circu |
| 6262585 |
Apparatus for I/O leakage self-test in an integrated circuit |
July 17, 2001 |
| According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O circuit. In a test mode of operation, the leakage detection circuit tests the first I/O circuit for excessive leak |
