| Patent Number |
Title Of Patent |
Date Issued |
| 6740566 |
Ultra-thin resist shallow trench process using high selectivity nitride etch |
May 25, 2004 |
| In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra- |
| 6544885 |
Polished hard mask process for conductor layer patterning |
April 8, 2003 |
| A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask m |
| 6492067 |
Removable pellicle for lithographic mask protection and handling |
December 10, 2002 |
| A removable pellicle for a lithographic mask that provides active and robust particle protection, and which utilizes a traditional pellicle and two deployments of thermophoretic protection to keep particles off the mask. The removable pellicle is removably attached via a retaining st |
| 6440640 |
Thin resist with transition metal hard mask for via etch application |
August 27, 2002 |
| A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transi |
| 6414326 |
Technique to separate dose-induced vs. focus-induced CD or linewidth variation |
July 2, 2002 |
| A method of identifying a change in focus and a change in illumination from a best focus and a best dose at a region on a substrate corresponding to a point in the image field of a lithographic printing tool is disclosed. The method includes forming a feature having a first pitch and a f |
| 6370680 |
Device to determine line edge roughness effect on device performance |
April 9, 2002 |
| A structure (300) for determining an amount of line edge roughness (LER) on a patterned feature (310) includes a plurality of source regions (304) and drain regions (306) formed in a semiconductor substrate (303), with each of the source and drain regions (304, 306) having a channel (320 |
| 6326319 |
Method for coating ultra-thin resist films |
December 4, 2001 |
| There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 1 |
| 6316277 |
Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist |
November 13, 2001 |
| There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film |
| 6309926 |
Thin resist with nitride hard mask for gate etch application |
October 30, 2001 |
| A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the |
| 6306560 |
Ultra-thin resist and SiON/oxide hard mask for metal etch |
October 23, 2001 |
| In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon oxynitride layer over the oxide layer; depositing an ultra-thin |
| 6271602 |
Method for reducing the susceptibility to chemical-mechanical polishing damage of an alignment m |
August 7, 2001 |
| A method for processing a semiconductor substrate is presented wherein an alignment mark is formed in an alignment mark area of the semiconductor substrate. The alignment mark area is contained within a window area of the semiconductor substrate. The upper surface of the semiconductor |
| 6255125 |
Method and apparatus for compensating for critical dimension variations in the production of a s |
July 3, 2001 |
| Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insula |
| 6208747 |
Determination of scanning error in scanner by reticle rotation |
March 27, 2001 |
| A method (300) of characterizing a lithographic scanning system includes the steps of printing a first pattern (302) using a reticle (220) having a first orientation with respect to the lithographic scanning system and measuring a critical dimension of the first pattern at a plurality of |
| 6207966 |
Mark protection with transparent film |
March 27, 2001 |
| An alignment mark protection structure (95) is disclosed which is used to ensure an integrity of an alignment scheme for a substrate (50) which is to be subjected to lithographic processing. The alignment mark protection structure (95) comprises the substrate (50) and an alignment mark ( |
| 6200907 |
Ultra-thin resist and barrier metal/oxide hard mask for metal etch |
March 13, 2001 |
| In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin pho |
| 6184128 |
Method using a thin resist mask for dual damascene stop layer etch |
February 6, 2001 |
| In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first |
| 6178256 |
Removal of reticle effect on critical dimension by reticle rotation |
January 23, 2001 |
| A method (200) of characterizing a lithographic printer includes the steps of printing a first and second pattern (202, 228) on substrates (214) using a reticle (220) having a first and second orientation. The method (200) further includes measuring a critical dimension of the first and |
| 6178221 |
Lithography reflective mask |
January 23, 2001 |
| A reflective lithography mask (12) including a substrate (40); a reflective coating (42); a plurality of absorbing blocks (44) covering certain regions of the reflective coating (42) in a manner corresponding to a desired circuit pattern; and a plurality of buffer blocks (46) situated |
| 6171763 |
Ultra-thin resist and oxide/nitride hard mask for metal etch |
January 9, 2001 |
| In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, a silicon nitride layer over the metal layer, and an oxide layer over the silicon nitride layer; depositing an ul |
| 6165695 |
Thin resist with amorphous silicon hard mask for via etch application |
December 26, 2000 |
| A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amor |
| 6162587 |
Thin resist with transition metal hard mask for via etch application |
December 19, 2000 |
| A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transi |
| 6159643 |
Extreme ultraviolet lithography reflective mask |
December 12, 2000 |
| A reflective lithography mask (12) includes a pattern-producing portion (200) and a substrate (300) supporting the pattern-producing portion on its top surface. The pattern-producing portion has reflective regions and non-reflective regions corresponding to a desired circuit pattern. The |
| 6156658 |
Ultra-thin resist and silicon/oxide hard mask for metal etch |
December 5, 2000 |
| In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist |
| 6140023 |
Method for transferring patterns created by lithography |
October 31, 2000 |
| A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresi |
| 6127070 |
Thin resist with nitride hard mask for via etch application |
October 3, 2000 |
| A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a nitride layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the nitride layer, |
| 6098408 |
System for controlling reflection reticle temperature in microlithography |
August 8, 2000 |
| A system for regulating reticle temperature is provided. The system includes a reticle for use in a lithographic process and a chuck assembly for supporting the reticle. The chuck assembly includes: a backplate having front and back surfaces, the front surface engaging with a backside |
| 6057206 |
Mark protection scheme with no masking |
May 2, 2000 |
| A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protect |
| 6048652 |
Backside polish EUV mask and method of manufacture |
April 11, 2000 |
| A method (100) of forming a reflective reticle blank includes forming (106) a reflective layer (108) over a flat substrate (104) and coupling a low thermal expansion material (112) to the reflective layer (108). After coupling the low thermal expansion material (112) to the reflective la |
| 6020269 |
Ultra-thin resist and nitride/oxide hard mask for metal etch |
February 1, 2000 |
| In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon nitride layer over the oxide layer; depositing an ultra-thin p |
| 6013399 |
Reworkable EUV mask materials |
January 11, 2000 |
| A reworkable EUV mask (100) includes a substrate (40), a reflective layer (42) overlying the substrate (40), and a buffer layer (44) overlying the reflective layer (42). An absorbing layer (102) composed of primarily a non-heavy metal material overlies the buffer layer (44) for absorbing |
| 5985498 |
Method of characterizing linewidth errors in a scanning lithography system |
November 16, 1999 |
| A method of characterizing linewidth errors in a lithography system 30 used to delineate a desired pattern onto an exposure site of a wafer 32. The pattern of a reticle 34 is transferred onto an exposure site 56 of a wafer 32 by projecting a slit of light extending in a slit direction y |
