| Patent Number |
Title Of Patent |
Date Issued |
| 7402535 |
Method of incorporating stress into a transistor channel by use of a backside layer |
July 22, 2008 |
| The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located be |
| 7393787 |
Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therei |
July 1, 2008 |
| The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided d |
| 7211481 |
Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly lay |
May 1, 2007 |
| The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PM |
| 6960499 |
Dual-counterdoped channel field effect transistor and method |
November 1, 2005 |
| A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment |
| 6882013 |
Transistor with reduced short channel effects and method |
April 19, 2005 |
| A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) an |
| 6822297 |
Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness |
November 23, 2004 |
| A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and bot |
| 6713334 |
Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask |
March 30, 2004 |
| An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transisto |
| 6617217 |
Reduction in well implant channeling and resulting latchup characteristics in shallow trench iso |
September 9, 2003 |
| Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, and 60) the channeling of the |
| 6579770 |
Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved |
June 17, 2003 |
| A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking |
| 6479339 |
Use of a thin nitride spacer in a split gate embedded analog process |
November 12, 2002 |
| A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the formation of the LDD regions 180, 2 |
| 6362062 |
Disposable sidewall spacer process for integrated circuits |
March 26, 2002 |
| A method for forming a MOS transistor using a disposable sidewall spacer process. A gate dielectric (20) and a gate structure (25) is formed on a semiconductor substrate (10). Insulator films (30) and (35) and formed and a LOCOS type film (80) is formed on the substrate (10). A spacer st |
| 6326281 |
Integrated circuit isolation |
December 4, 2001 |
| Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate. |
| 6306712 |
Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved |
October 23, 2001 |
| A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking |
| 6287920 |
Method of making multiple threshold voltage integrated of circuit transistors |
September 11, 2001 |
| A method for forming multiple threshold voltage integrated circuit transistors. Angled pocket type implants (80) are performed to form asymmetric regions (90) and (95). The source and drain regions (120, 121, 122, and 123) are connected such that multiple threshold voltage transistor |
| 6274449 |
Method of pocket implant modeling for a CMOS process |
August 14, 2001 |
| The invention comprises a method of determining the thermal straggle of microelectronic devices having a pocket dopant implant that is formed under substantially the same doping conditions. The method comprises measuring the operating characteristics of each device (32) and obtaining |
| 6258644 |
Mixed voltage CMOS process for high reliability and high performance core and I/O transistors wi |
July 10, 2001 |
| A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the |
| 6228725 |
Semiconductor devices with pocket implant and counter doping |
May 8, 2001 |
| A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adj |
| 6204073 |
Shallow trench isolation with conductive hard mask for in-line moat/trench width electrical meas |
March 20, 2001 |
| A method for forming STI that allows for in-situ moat/trench width electrical measurement is disclosed herein. A conductive layer (18) is used in the hard mask (20) for trench etch. After the hard mask (20) is formed and the trench (12) is etched, the resistance of the conductive lay |
| 6150669 |
Combination test structures for in-situ measurements during fabrication of semiconductor devices |
November 21, 2000 |
| A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe |
| 5976937 |
Transistor having ultrashallow source and drain junctions with reduced gate overlap and method |
November 2, 1999 |
| Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) ma |
| 5917219 |
Semiconductor devices with pocket implant and counter doping |
June 29, 1999 |
| A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adj |
| 5296725 |
Integrated multicelled semiconductor switching device for high current applications |
March 22, 1994 |
| An integrated multicelled thyristor includes a plurality of main thyristor cells and a plurality of edge thyristor cells. The main thyristor cells comprise source cells located in the center or innermost portion of an integrated thyristor and the edge cells are located at the periphery. |
| 5294816 |
Unit cell arrangement for emitter switched thyristor with base resistance control |
March 15, 1994 |
| An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ |
