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Tomohiro Nagano Patents |
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Inventor: Nagano; Tomohiro
Address: Akishima, JP
No. of patents: 4
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6271687 |
Sense amplifier circuit |
August 7, 2001 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 6046609 |
Sense amplifier circuit |
April 4, 2000 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 5936909 |
Static random access memory |
August 10, 1999 |
| A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address sel |
| 5854562 |
Sense amplifier circuit |
December 29, 1998 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
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