| Patent Number |
Title Of Patent |
Date Issued |
| 7415531 |
Method and apparatus for predicting characteristics of incoming data packets to enable speculati |
August 19, 2008 |
| A system for processing data packets in a data packet network has at least one input port for receiving data packets, at least one output port for sending out data packets, a processor for processing packet data, and a packet predictor for predicting a future packet based on a received |
| 7406586 |
Fetch and dispatch disassociation apparatus for multi-streaming processors |
July 29, 2008 |
| A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated w |
| 7360217 |
Multi-threaded packet processing engine for stateful packet processing |
April 15, 2008 |
| A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to accomplish the tasks, |
| 7280548 |
Method and apparatus for non-speculative pre-fetch operation in data packet processing |
October 9, 2007 |
| A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them fo |
| 7197043 |
Method for allocating memory space for limited packet head and/or tail growth |
March 27, 2007 |
| A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory |
| 7165257 |
Context selection and activation mechanism for activating one of a group of inactive contexts in |
January 16, 2007 |
| A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing a |
| 7155516 |
Method and apparatus for overflowing data packets to a software-controlled memory when they do n |
December 26, 2006 |
| A system for managing packets incoming to a data router has a local packet memory (LPM) mapped into pre-configured memory units, to store packets for processing, an external packet memory (EPM), a first storage system to store packets in the LPM, and a second storage system to store pack |
| 7139901 |
Extended instruction set for packet processing applications |
November 21, 2006 |
| A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a po |
| 7139898 |
Fetch and dispatch disassociation apparatus for multistreaming processors |
November 21, 2006 |
| A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated w |
| 7082552 |
Functional validation of a packet management unit |
July 25, 2006 |
| A validation system is disclosed for validating function of a packet-management unit operationally coupled through a system interface to a processing unit of a processor system. The validation system comprises a user interface for creating an inputting test parameters and test code i |
| 7076630 |
Method and apparatus for allocating and de-allocating consecutive blocks of memory in background |
July 11, 2006 |
| A system for allocating storage of incoming data packets into a memory of a packet processor has a first facility mapping a first block of memory of a fixed block size in bytes into an ordered plurality of atomic pages comprising each a fixed byte size, a second facility mapping the same |
| 7065096 |
Method for allocating memory space for limited packet head and/or tail growth |
June 20, 2006 |
| A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory |
| 7058065 |
Method and apparatus for preventing undesirable packet download with pending read/write operatio |
June 6, 2006 |
| A logic system for resolving port contentions associated with memory-access requests in data packet routing is provided. The logic system comprises a determination logic for assessing and reporting port status of busy or not busy, a command mechanism for issuing commands contingent o |
| 7042887 |
Method and apparatus for non-speculative pre-fetch operation in data packet processing |
May 9, 2006 |
| A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them f |
| 7035998 |
Clustering stream and/or instruction queues for multi-streaming processors |
April 25, 2006 |
| A pipelined multistreaming processor has an instruction source, a first cluster of a plurality of streams fetching instructions from the instruction source, a second cluster of a plurality of streams fetching instructions from the instruction source, dedicated instruction queues for |
| 6282614 |
Apparatus and method for reducing the power consumption of a microprocessor with multiple levels |
August 28, 2001 |
| An apparatus and method for reducing the power consumption of a multi-cache microprocessor dynamically predicts the misses of an i.sup.th -level (L.sub.i) cache. This method predicts the misses in L.sub.i and accesses the i+1 level cache (L.sub.i+1) concurrently with L.sub.i only if a mi |
