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Thomas Mountsier Patents |
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Inventor: Mountsier; Thomas
Address: San Jose, CA
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7338908 |
Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage |
March 4, 2008 |
| An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently remove |
| 6613199 |
Apparatus and method for physical vapor deposition using an open top hollow cathode magnetron |
September 2, 2003 |
| A hollow cathode magnetron comprises an open top target within a hollow cathode. The open top target can be biased to a negative potential so as to form an electric field within the cathode to generate a plasma. The magnetron uses at least one electromagnetic coil to shape and maintain a |
| 5810933 |
Wafer cooling device |
September 22, 1998 |
| A wafer cooling device (WCD) for cooling a substrate, such as a wafer, during processing is presented. The substrate is mounted to an WCD heat transfer surface, thereby forming a cavity in between the substrate and the heat transfer surface into which gas is incorporated. An array of |
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