| Patent Number |
Title Of Patent |
Date Issued |
| 7379377 |
Memory array decoder |
May 27, 2008 |
| An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the |
| 7362619 |
Data strobe synchronization circuit and method for double data rate, multi-bit writes |
April 22, 2008 |
| A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data stro |
| 7358872 |
Method and apparatus for converting parallel data to serial data in high speed applications |
April 15, 2008 |
| A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel |
| 7330393 |
Memory array decoder |
February 12, 2008 |
| An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the |
| 7318167 |
DDR II write data capture calibration |
January 8, 2008 |
| A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100," is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the prede |
| 7245550 |
Memory array decoder |
July 17, 2007 |
| An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the |
| 7227812 |
Write address synchronization useful for a DDR prefetch SDRAM |
June 5, 2007 |
| Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to |
| 7165185 |
DDR II write data capture calibration |
January 16, 2007 |
| A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100," is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the prede |
| 7142543 |
High speed programmable counter |
November 28, 2006 |
| A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and c |
| 7116133 |
Apparatus and method for adjusting clock skew |
October 3, 2006 |
| The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external |
| 7102937 |
Solution to DQS postamble ringing problem in memory chips |
September 5, 2006 |
| The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two der |
| 7099989 |
System and technique to reduce cycle time by performing column redundancy checks during a delay |
August 29, 2006 |
| A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals |
| 7054222 |
Write address synchronization useful for a DDR prefetch SDRAM |
May 30, 2006 |
| Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to |
| 7019553 |
Method and circuit for off chip driver control, and memory device using same |
March 28, 2006 |
| An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to th |
| 7009911 |
Memory array decoder |
March 7, 2006 |
| An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the |
| 6922367 |
Data strobe synchronization circuit and method for double data rate, multi-bit writes |
July 26, 2005 |
| A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe |
| 6791370 |
Apparatus and method for adjusting clock skew |
September 14, 2004 |
| The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external in |
| 6763444 |
Read/write timing calibration of a memory array using a row or a redundant row |
July 13, 2004 |
| A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to |
| 6727739 |
Compensation for a delay locked loop |
April 27, 2004 |
| A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plural |
| 6691214 |
DDR II write data capture calibration |
February 10, 2004 |
| A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100," is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predeterm |
| 6643194 |
Write data masking for higher speed drams |
November 4, 2003 |
| A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the marg |
| 6636093 |
Compensation for a delay locked loop |
October 21, 2003 |
| A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plural |
| 6633503 |
Voltage differential sensing circuit and methods of using same |
October 14, 2003 |
| A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transitio |
| 6615331 |
System and method to reduce cycle time by performing column redundancy checks during a delay to |
September 2, 2003 |
| A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals t |
| 6600691 |
High frequency range four bit prefetch output data path |
July 29, 2003 |
| A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an out |
| 6556494 |
High frequency range four bit prefetch output data path |
April 29, 2003 |
| A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an out |
| 6532180 |
Write data masking for higher speed DRAMs |
March 11, 2003 |
| A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the marg |
| 6446180 |
Memory device with synchronized output path |
September 3, 2002 |
| A memory device includes a data array, array control logic, a delay locked loop circuit, timing control logic, and a first storage device. The array control logic is adapted to receive a read command synchronized with an external clock signal and to read at least a first data element fro |
| 6392453 |
Differential input buffer bias circuit |
May 21, 2002 |
| An integrated differential buffer circuit and its method of operation are described in which the buffer circuit has an internal bias line for controlling the supply of voltage to the buffer circuit. When the buffer circuit is first enabled, a start voltage is initially applied to the bia |
| 6385108 |
Voltage differential sensing circuit and methods of using same |
May 7, 2002 |
| A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transitio |
| 6226295 |
High speed programmable counter |
May 1, 2001 |
| A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and conti |
| 6202179 |
Method and apparatus for testing cells in a memory device with compressed data and for replacing |
March 13, 2001 |
| A compression test mode, independent of redundancy, for a memory device is disclosed. In one embodiment, a method for testing a memory array of a memory device includes outputting individually the output bits of a predetermined number of memory cells, upon failure of a compression mode. |
| 6188623 |
Voltage differential sensing circuit and methods of using same |
February 13, 2001 |
| A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transitio |
| 6150856 |
Delay lock loops, signal locking methods and methods of implementing delay lock loops |
November 21, 2000 |
| Delay lock loops, signal locking methods, and methods of implementing delay lock loops are described. In one embodiment, a delay lock loop comprises a delay line having first and second inputs and an output. The first input is configured to receive a clock signal. An output model has an |
| 5913928 |
Data compression test mode independent of redundancy |
June 22, 1999 |
| A method and circuit for testing cells in a memory device is disclosed. Data is written to the cells and then the cells are read in groups. For example, groups of four cells are read together. Output bits of the four cells are compressed in a compression circuit to generate compressed da |
| 5907591 |
High speed programmable counter |
May 25, 1999 |
| A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and conti |
| 5805931 |
Programmable bandwidth I/O port and a communication interface using the same port having a plura |
September 8, 1998 |
| A programmable bandwidth I/O port using a DRAM connected to a plurality of serial access memories. Data is synchronously transferred between the DRAM and the serial access memories and is asynchronously transferred between the serial access memories and a plurality of single or multiple |
| 5802131 |
Multiport serial access self-queuing memory switch |
September 1, 1998 |
| A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferr |
| 5680425 |
Self-queuing serial output port |
October 21, 1997 |
| A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferr |
| 5666390 |
High speed programmable counter |
September 9, 1997 |
| A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and conti |
