| Patent Number |
Title Of Patent |
Date Issued |
| 5700705 |
Semiconductor integrated circuit device |
December 23, 1997 |
| The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, dra |
| 5646423 |
Semiconductor integrated circuit device |
July 8, 1997 |
| A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the s |
| 5619055 |
Semiconductor integrated circuit device |
April 8, 1997 |
| A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of |
| 5483083 |
Semiconductor integrated circuit device |
January 9, 1996 |
| A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of |
| 5237528 |
Semiconductor memory |
August 17, 1993 |
| A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on |
| 5214496 |
Semiconductor memory |
May 25, 1993 |
| A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on |
| 5194749 |
Semiconductor integrated circuit device |
March 16, 1993 |
| In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source an |
| 5172335 |
Semiconductor memory with divided bit load and data bus lines |
December 15, 1992 |
| A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, |
| 5148387 |
Logic circuit and data processing apparatus using the same |
September 15, 1992 |
| A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are |
| 5132771 |
Semiconductor memory device having flip-flop circuits |
July 21, 1992 |
| A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage n |
| 5079611 |
Semiconductor integrated circuit device and process for fabricating the same |
January 7, 1992 |
| Herein disclosed is a semiconductor integrated circuit device having a SRAM, in which two MISFETs of a flip-flop circuit of a memory cell are connected directly with an n.sup.+ -type drain region so that they are cross coupled; and in which a p.sup.+ -type semiconductor region is formed |
| 5028975 |
Semiconductor devices and a process for producing the same |
July 2, 1991 |
| Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to |
| 4992677 |
High speed MOSFET output buffer with low noise |
February 12, 1991 |
| A semiconductor integrated circuit includes: a data output terminal; a first semiconductor element connected between a first operating potential point and the data output terminal; a second semiconductor element connected between the data output terminal and a second operating potent |
| 4937790 |
Semiconductor memory device |
June 26, 1990 |
| A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line |
| 4935901 |
Semiconductor memory with divided bit load and data bus lines |
June 19, 1990 |
| A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, |
| 4901128 |
Semiconductor memory |
February 13, 1990 |
| A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on |
| 4876669 |
MOS static type RAM having a variable load |
October 24, 1989 |
| An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminal |
| 4853894 |
Static random-access memory having multilevel conductive layer |
August 1, 1989 |
| A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectivel |
| 4849801 |
Semiconductor memory device having increased capacitance for the storing nodes of the memory cel |
July 18, 1989 |
| A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to incr |
| 4841486 |
Semiconductor memory device and sense amplifier |
June 20, 1989 |
| A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on |
| 4805147 |
Stacked static random access memory cell having capacitor |
February 14, 1989 |
| A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon l |
| 4797717 |
Semiconductor memory device |
January 10, 1989 |
| Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The so |
| 4792841 |
Semiconductor devices and a process for producing the same |
December 20, 1988 |
| Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as |
| 4785342 |
Static random access memory having structure of first-, second- and third-level conductive films |
November 15, 1988 |
| A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area is formed using a relatively thick |
| 4760561 |
MOS static type RAM having a variable load |
July 26, 1988 |
| An MOS static type RAM has a memory cell array comprising a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals |
| 4747082 |
Semiconductor memory with automatic refresh means |
May 24, 1988 |
| A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock s |
| 4701884 |
Semiconductor memory for serial data access |
October 20, 1987 |
| A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data |
| 4672586 |
Semiconductor memory having circuit effecting refresh on variable cycles |
June 9, 1987 |
| A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the |
| 4653025 |
Random access memory with high density and low power |
March 24, 1987 |
| A static RAM having a plurality of memory cells. Each memory cell consists of driver MOST's that are connected to each other in a crossing manner, and transfer MOST's that connect storage nodes of the memory cell to the data lines. The driver MOST's are comprised of n-channel MOST's, and |
| 4641285 |
Line change-over circuit and semiconductor memory using the same |
February 3, 1987 |
| The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch |
| 4616243 |
Gate protection for a MOSFET |
October 7, 1986 |
| This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the volta |
| 4609835 |
Semiconductor integrated circuit |
September 2, 1986 |
| Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended |
| 4609407 |
Method of making three dimensional semiconductor devices in selectively laser regrown polysilico |
September 2, 1986 |
| Herein disclosed is a semiconductor device having at least one lower resistance region formed in the single-crystalline semiconductor film which is so formed to continuously coat both a single-crystalline semiconductor substrate and an insulating film formed on the surface of the sub |
| 4539660 |
Semiconductor integrated circuit |
September 3, 1985 |
| A nonvolatile memory in which at least one power supply element is carried with an integrated circuit chip containing the memory and connected to power supply terminals of the integrated circuit chip having a memory cell array in which a plurality of memory elements or memory circuits ar |
| 4507759 |
Static memory |
March 26, 1985 |
| In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by |
| 4492974 |
DMOS With gate protection diode formed over base region |
January 8, 1985 |
| A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conduc |
| 4455495 |
Programmable semiconductor integrated circuitry including a programming semiconductor element |
June 19, 1984 |
| A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its orig |
| 4377819 |
Semiconductor device |
March 22, 1983 |
| A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetw |
| 4280065 |
Tri-state type driver circuit |
July 21, 1981 |
| This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output invert |
| 4261004 |
Semiconductor device |
April 7, 1981 |
| On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./. |
| 4086642 |
Protective circuit and device for metal-oxide-semiconductor field effect transistor and method f |
April 25, 1978 |
| A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the |
